add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/pinctrl/pinctrl-coh901.c
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@@ -1,8 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * U300 GPIO module.
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  *
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  * Copyright (C) 2007-2012 ST-Ericsson AB
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- * License terms: GNU General Public License (GPL) version 2
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  * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
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  * Author: Linus Walleij <linus.walleij@linaro.org>
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  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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@@ -15,7 +15,7 @@
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 #include <linux/clk.h>
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 #include <linux/err.h>
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 #include <linux/platform_device.h>
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-#include <linux/gpio.h>
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+#include <linux/gpio/driver.h>
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 #include <linux/slab.h>
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 #include <linux/pinctrl/consumer.h>
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 #include <linux/pinctrl/pinconf-generic.h>
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@@ -615,7 +615,7 @@
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 static int __init u300_gpio_probe(struct platform_device *pdev)
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 {
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 	struct u300_gpio *gpio;
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-	struct resource *memres;
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+	struct gpio_irq_chip *girq;
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 	int err = 0;
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 	int portno;
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 	u32 val;
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@@ -632,8 +632,7 @@
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 	gpio->chip.base = 0;
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 	gpio->dev = &pdev->dev;
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-	memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	gpio->base = devm_ioremap_resource(&pdev->dev, memres);
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+	gpio->base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(gpio->base))
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 		return PTR_ERR(gpio->base);
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638
 
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@@ -672,26 +671,17 @@
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 	       gpio->base + U300_GPIO_CR);
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 	u300_gpio_init_coh901571(gpio);
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673
 
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-#ifdef CONFIG_OF_GPIO
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-	gpio->chip.of_node = pdev->dev.of_node;
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-#endif
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-	err = gpiochip_add_data(&gpio->chip, gpio);
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-	if (err) {
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-		dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
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-		goto err_no_chip;
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+	girq = &gpio->chip.irq;
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+	girq->chip = &u300_gpio_irqchip;
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+	girq->parent_handler = u300_gpio_irq_handler;
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+	girq->num_parents = U300_GPIO_NUM_PORTS;
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+	girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
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+				     sizeof(*girq->parents),
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+				     GFP_KERNEL);
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+	if (!girq->parents) {
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+		err = -ENOMEM;
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+		goto err_dis_clk;
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 	}
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-
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-	err = gpiochip_irqchip_add(&gpio->chip,
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-				   &u300_gpio_irqchip,
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-				   0,
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-				   handle_simple_irq,
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-				   IRQ_TYPE_EDGE_FALLING);
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-	if (err) {
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-		dev_err(gpio->dev, "no GPIO irqchip\n");
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-		goto err_no_irqchip;
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-	}
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-
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-	/* Add each port with its IRQ separately */
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 	for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
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 		struct u300_gpio_port *port = &gpio->ports[portno];
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687
 
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@@ -700,16 +690,21 @@
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 		port->gpio = gpio;
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691
 
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 		port->irq = platform_get_irq(pdev, portno);
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-
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-		gpiochip_set_chained_irqchip(&gpio->chip,
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-					     &u300_gpio_irqchip,
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-					     port->irq,
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-					     u300_gpio_irq_handler);
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+		girq->parents[portno] = port->irq;
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 		/* Turns off irq force (test register) for this port */
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 		writel(0x0, gpio->base + portno * gpio->stride + ifr);
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 	}
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-	dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
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+	girq->default_type = IRQ_TYPE_EDGE_FALLING;
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+	girq->handler = handle_simple_irq;
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+#ifdef CONFIG_OF_GPIO
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+	gpio->chip.of_node = pdev->dev.of_node;
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+#endif
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+	err = gpiochip_add_data(&gpio->chip, gpio);
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+	if (err) {
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+		dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
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+		goto err_dis_clk;
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+	}
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708
 
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 	/*
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 	 * Add pinctrl pin ranges, the pin controller must be registered
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@@ -729,9 +724,8 @@
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 	return 0;
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 err_no_range:
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-err_no_irqchip:
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 	gpiochip_remove(&gpio->chip);
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-err_no_chip:
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+err_dis_clk:
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 	clk_disable_unprepare(gpio->clk);
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 	dev_err(&pdev->dev, "module ERROR:%d\n", err);
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 	return err;