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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/pinctrl/mediatek/pinctrl-mt7622.c
....@@ -1,297 +1,140 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * MediaTek MT7622 Pinctrl Driver
3
+ * Copyright (C) 2017-2018 MediaTek Inc.
34  *
4
- * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5
+ * Author: Sean Wang <sean.wang@mediatek.com>
56  *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
147  */
158 
16
-#include <linux/gpio.h>
17
-#include <linux/gpio/driver.h>
18
-#include <linux/io.h>
19
-#include <linux/init.h>
20
-#include <linux/mfd/syscon.h>
21
-#include <linux/of.h>
22
-#include <linux/of_irq.h>
23
-#include <linux/of_platform.h>
24
-#include <linux/platform_device.h>
25
-#include <linux/pinctrl/pinctrl.h>
26
-#include <linux/pinctrl/pinmux.h>
27
-#include <linux/pinctrl/pinconf.h>
28
-#include <linux/pinctrl/pinconf-generic.h>
29
-#include <linux/regmap.h>
9
+#include "pinctrl-moore.h"
3010 
31
-#include "../core.h"
32
-#include "../pinconf.h"
33
-#include "../pinmux.h"
34
-#include "mtk-eint.h"
35
-
36
-#define PINCTRL_PINCTRL_DEV		KBUILD_MODNAME
37
-#define MTK_RANGE(_a)		{ .range = (_a), .nranges = ARRAY_SIZE(_a), }
38
-#define PINCTRL_PIN_GROUP(name, id)			\
39
-	{						\
40
-		name,					\
41
-		id##_pins,				\
42
-		ARRAY_SIZE(id##_pins),			\
43
-		id##_funcs,				\
44
-	}
45
-
46
-#define MTK_GPIO_MODE	1
47
-#define MTK_INPUT	0
48
-#define MTK_OUTPUT	1
49
-#define MTK_DISABLE	0
50
-#define MTK_ENABLE	1
51
-
52
-/* Custom pinconf parameters */
53
-#define MTK_PIN_CONFIG_TDSEL	(PIN_CONFIG_END + 1)
54
-#define MTK_PIN_CONFIG_RDSEL	(PIN_CONFIG_END + 2)
55
-
56
-/* List these attributes which could be modified for the pin */
57
-enum {
58
-	PINCTRL_PIN_REG_MODE,
59
-	PINCTRL_PIN_REG_DIR,
60
-	PINCTRL_PIN_REG_DI,
61
-	PINCTRL_PIN_REG_DO,
62
-	PINCTRL_PIN_REG_SR,
63
-	PINCTRL_PIN_REG_SMT,
64
-	PINCTRL_PIN_REG_PD,
65
-	PINCTRL_PIN_REG_PU,
66
-	PINCTRL_PIN_REG_E4,
67
-	PINCTRL_PIN_REG_E8,
68
-	PINCTRL_PIN_REG_TDSEL,
69
-	PINCTRL_PIN_REG_RDSEL,
70
-	PINCTRL_PIN_REG_MAX,
71
-};
72
-
73
-/* struct mtk_pin_field - the structure that holds the information of the field
74
- *			  used to describe the attribute for the pin
75
- * @offset:		the register offset relative to the base address
76
- * @mask:		the mask used to filter out the field from the register
77
- * @bitpos:		the start bit relative to the register
78
- * @next:		the indication that the field would be extended to the
79
-			next register
80
- */
81
-struct mtk_pin_field {
82
-	u32 offset;
83
-	u32 mask;
84
-	u8  bitpos;
85
-	u8  next;
86
-};
87
-
88
-/* struct mtk_pin_field_calc - the structure that holds the range providing
89
- *			       the guide used to look up the relevant field
90
- * @s_pin:		the start pin within the range
91
- * @e_pin:		the end pin within the range
92
- * @s_addr:		the start address for the range
93
- * @x_addrs:		the address distance between two consecutive registers
94
- *			within the range
95
- * @s_bit:		the start bit for the first register within the range
96
- * @x_bits:		the bit distance between two consecutive pins within
97
- *			the range
98
- */
99
-struct mtk_pin_field_calc {
100
-	u16 s_pin;
101
-	u16 e_pin;
102
-	u32 s_addr;
103
-	u8  x_addrs;
104
-	u8  s_bit;
105
-	u8  x_bits;
106
-};
107
-
108
-/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
109
- *			     determine which register the pin would make use of
110
- *			     for certain pin attribute.
111
- * @range:		     the start address for the range
112
- * @nranges:		     the number of items in the range
113
- */
114
-struct mtk_pin_reg_calc {
115
-	const struct mtk_pin_field_calc *range;
116
-	unsigned int nranges;
117
-};
118
-
119
-/* struct mtk_pin_soc - the structure that holds SoC-specific data */
120
-struct mtk_pin_soc {
121
-	const struct mtk_pin_reg_calc	*reg_cal;
122
-	const struct pinctrl_pin_desc	*pins;
123
-	unsigned int			npins;
124
-	const struct group_desc		*grps;
125
-	unsigned int			ngrps;
126
-	const struct function_desc	*funcs;
127
-	unsigned int			nfuncs;
128
-	const struct mtk_eint_regs	*eint_regs;
129
-	const struct mtk_eint_hw	*eint_hw;
130
-};
131
-
132
-struct mtk_pinctrl {
133
-	struct pinctrl_dev		*pctrl;
134
-	void __iomem			*base;
135
-	struct device			*dev;
136
-	struct gpio_chip		chip;
137
-	const struct mtk_pin_soc	*soc;
138
-	struct mtk_eint			*eint;
139
-};
11
+#define MT7622_PIN(_number, _name)					\
12
+	MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
14013 
14114 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
142
-	{0, 0, 0x320, 0x10, 16, 4},
143
-	{1, 4, 0x3a0, 0x10,  16, 4},
144
-	{5, 5, 0x320, 0x10,  0, 4},
145
-	{6, 6, 0x300, 0x10,  4, 4},
146
-	{7, 7, 0x300, 0x10,  4, 4},
147
-	{8, 9, 0x350, 0x10,  20, 4},
148
-	{10, 10, 0x300, 0x10, 8, 4},
149
-	{11, 11, 0x300, 0x10, 8, 4},
150
-	{12, 12, 0x300, 0x10, 8, 4},
151
-	{13, 13, 0x300, 0x10, 8, 4},
152
-	{14, 15, 0x320, 0x10, 4, 4},
153
-	{16, 17, 0x320, 0x10, 20, 4},
154
-	{18, 21, 0x310, 0x10, 16, 4},
155
-	{22, 22, 0x380, 0x10, 16, 4},
156
-	{23, 23, 0x300,	0x10, 24, 4},
157
-	{24, 24, 0x300, 0x10, 24, 4},
158
-	{25, 25, 0x300, 0x10, 12, 4},
159
-	{25, 25, 0x300, 0x10, 12, 4},
160
-	{26, 26, 0x300, 0x10, 12, 4},
161
-	{27, 27, 0x300, 0x10, 12, 4},
162
-	{28, 28, 0x300, 0x10, 12, 4},
163
-	{29, 29, 0x300, 0x10, 12, 4},
164
-	{30, 30, 0x300, 0x10, 12, 4},
165
-	{31, 31, 0x300, 0x10, 12, 4},
166
-	{32, 32, 0x300, 0x10, 12, 4},
167
-	{33, 33, 0x300,	0x10, 12, 4},
168
-	{34, 34, 0x300,	0x10, 12, 4},
169
-	{35, 35, 0x300,	0x10, 12, 4},
170
-	{36, 36, 0x300, 0x10, 12, 4},
171
-	{37, 37, 0x300, 0x10, 20, 4},
172
-	{38, 38, 0x300, 0x10, 20, 4},
173
-	{39, 39, 0x300, 0x10, 20, 4},
174
-	{40, 40, 0x300, 0x10, 20, 4},
175
-	{41, 41, 0x300,	0x10, 20, 4},
176
-	{42, 42, 0x300, 0x10, 20, 4},
177
-	{43, 43, 0x300,	0x10, 20, 4},
178
-	{44, 44, 0x300, 0x10, 20, 4},
179
-	{45, 46, 0x300, 0x10, 20, 4},
180
-	{47, 47, 0x300,	0x10, 20, 4},
181
-	{48, 48, 0x300, 0x10, 20, 4},
182
-	{49, 49, 0x300, 0x10, 20, 4},
183
-	{50, 50, 0x300, 0x10, 20, 4},
184
-	{51, 70, 0x330, 0x10, 4, 4},
185
-	{71, 71, 0x300, 0x10, 16, 4},
186
-	{72, 72, 0x300, 0x10, 16, 4},
187
-	{73, 76, 0x310, 0x10, 0, 4},
188
-	{77, 77, 0x320, 0x10, 28, 4},
189
-	{78, 78, 0x320, 0x10, 12, 4},
190
-	{79, 82, 0x3a0, 0x10, 0, 4},
191
-	{83, 83, 0x350,	0x10, 28, 4},
192
-	{84, 84, 0x330, 0x10, 0, 4},
193
-	{85, 90, 0x360, 0x10, 4, 4},
194
-	{91, 94, 0x390, 0x10, 16, 4},
195
-	{95, 97, 0x380, 0x10, 20, 4},
196
-	{98, 101, 0x390, 0x10, 0, 4},
197
-	{102, 102, 0x360, 0x10, 0, 4},
15
+	PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
16
+	PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
17
+	PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
18
+	PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
19
+	PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
20
+	PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
21
+	PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
22
+	PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
23
+	PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
24
+	PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
25
+	PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
26
+	PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
27
+	PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
28
+	PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
29
+	PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
30
+	PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
31
+	PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
32
+	PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
33
+	PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
34
+	PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
35
+	PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
36
+	PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
37
+	PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
38
+	PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
39
+	PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
40
+	PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
19841 };
19942 
20043 static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
201
-	{0, 102, 0x0, 0x10, 0, 1},
44
+	PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
20245 };
20346 
20447 static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
205
-	{0, 102, 0x200, 0x10, 0, 1},
48
+	PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
20649 };
20750 
20851 static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
209
-	{0, 102, 0x100, 0x10, 0, 1},
52
+	PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
21053 };
21154 
21255 static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
213
-	{0, 31, 0x910, 0x10, 0, 1},
214
-	{32, 50, 0xa10, 0x10, 0, 1},
215
-	{51, 70, 0x810, 0x10, 0, 1},
216
-	{71, 72, 0xb10, 0x10, 0, 1},
217
-	{73, 86, 0xb10, 0x10, 4, 1},
218
-	{87, 90, 0xc10, 0x10, 0, 1},
219
-	{91, 102, 0xb10, 0x10, 18, 1},
56
+	PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
57
+	PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
58
+	PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
59
+	PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
60
+	PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
61
+	PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
62
+	PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
22063 };
22164 
22265 static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
223
-	{0, 31, 0x920, 0x10, 0, 1},
224
-	{32, 50, 0xa20, 0x10, 0, 1},
225
-	{51, 70, 0x820, 0x10, 0, 1},
226
-	{71, 72, 0xb20, 0x10, 0, 1},
227
-	{73, 86, 0xb20, 0x10, 4, 1},
228
-	{87, 90, 0xc20, 0x10, 0, 1},
229
-	{91, 102, 0xb20, 0x10, 18, 1},
66
+	PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
67
+	PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
68
+	PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
69
+	PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
70
+	PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
71
+	PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
72
+	PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
23073 };
23174 
23275 static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
233
-	{0, 31, 0x930, 0x10, 0, 1},
234
-	{32, 50, 0xa30, 0x10, 0, 1},
235
-	{51, 70, 0x830, 0x10, 0, 1},
236
-	{71, 72, 0xb30, 0x10, 0, 1},
237
-	{73, 86, 0xb30, 0x10, 4, 1},
238
-	{87, 90, 0xc30, 0x10, 0, 1},
239
-	{91, 102, 0xb30, 0x10, 18, 1},
76
+	PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
77
+	PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
78
+	PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
79
+	PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
80
+	PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
81
+	PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
82
+	PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
24083 };
24184 
24285 static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
243
-	{0, 31, 0x940, 0x10, 0, 1},
244
-	{32, 50, 0xa40, 0x10, 0, 1},
245
-	{51, 70, 0x840, 0x10, 0, 1},
246
-	{71, 72, 0xb40, 0x10, 0, 1},
247
-	{73, 86, 0xb40, 0x10, 4, 1},
248
-	{87, 90, 0xc40, 0x10, 0, 1},
249
-	{91, 102, 0xb40, 0x10, 18, 1},
86
+	PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
87
+	PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
88
+	PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
89
+	PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
90
+	PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
91
+	PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
92
+	PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
25093 };
25194 
25295 static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
253
-	{0, 31, 0x960, 0x10, 0, 1},
254
-	{32, 50, 0xa60, 0x10, 0, 1},
255
-	{51, 70, 0x860, 0x10, 0, 1},
256
-	{71, 72, 0xb60, 0x10, 0, 1},
257
-	{73, 86, 0xb60, 0x10, 4, 1},
258
-	{87, 90, 0xc60, 0x10, 0, 1},
259
-	{91, 102, 0xb60, 0x10, 18, 1},
96
+	PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
97
+	PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
98
+	PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
99
+	PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
100
+	PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
101
+	PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
102
+	PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
260103 };
261104 
262105 static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
263
-	{0, 31, 0x970, 0x10, 0, 1},
264
-	{32, 50, 0xa70, 0x10, 0, 1},
265
-	{51, 70, 0x870, 0x10, 0, 1},
266
-	{71, 72, 0xb70, 0x10, 0, 1},
267
-	{73, 86, 0xb70, 0x10, 4, 1},
268
-	{87, 90, 0xc70, 0x10, 0, 1},
269
-	{91, 102, 0xb70, 0x10, 18, 1},
106
+	PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
107
+	PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
108
+	PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
109
+	PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
110
+	PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
111
+	PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
112
+	PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
270113 };
271114 
272115 static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
273
-	{0, 31, 0x980, 0x4, 0, 4},
274
-	{32, 50, 0xa80, 0x4, 0, 4},
275
-	{51, 70, 0x880, 0x4, 0, 4},
276
-	{71, 72, 0xb80, 0x4, 0, 4},
277
-	{73, 86, 0xb80, 0x4, 16, 4},
278
-	{87, 90, 0xc80, 0x4, 0, 4},
279
-	{91, 102, 0xb88, 0x4, 8, 4},
116
+	PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
117
+	PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
118
+	PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
119
+	PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
120
+	PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
121
+	PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
122
+	PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
280123 };
281124 
282125 static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
283
-	{0, 31, 0x990, 0x4, 0, 6},
284
-	{32, 50, 0xa90, 0x4, 0, 6},
285
-	{51, 58, 0x890, 0x4, 0, 6},
286
-	{59, 60, 0x894, 0x4, 28, 6},
287
-	{61, 62, 0x894, 0x4, 16, 6},
288
-	{63, 66, 0x898, 0x4, 8, 6},
289
-	{67, 68, 0x89c, 0x4, 12, 6},
290
-	{69, 70, 0x89c, 0x4, 0, 6},
291
-	{71, 72, 0xb90, 0x4, 0, 6},
292
-	{73, 86, 0xb90, 0x4, 24, 6},
293
-	{87, 90, 0xc90, 0x4, 0, 6},
294
-	{91, 102, 0xb9c, 0x4, 12, 6},
126
+	PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
127
+	PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
128
+	PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
129
+	PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
130
+	PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
131
+	PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
132
+	PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
133
+	PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
134
+	PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
135
+	PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
136
+	PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
137
+	PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
295138 };
296139 
297140 static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
....@@ -309,116 +152,178 @@
309152 	[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
310153 };
311154 
312
-static const struct pinctrl_pin_desc mt7622_pins[] = {
313
-	PINCTRL_PIN(0, "GPIO_A"),
314
-	PINCTRL_PIN(1, "I2S1_IN"),
315
-	PINCTRL_PIN(2, "I2S1_OUT"),
316
-	PINCTRL_PIN(3, "I2S_BCLK"),
317
-	PINCTRL_PIN(4, "I2S_WS"),
318
-	PINCTRL_PIN(5, "I2S_MCLK"),
319
-	PINCTRL_PIN(6, "TXD0"),
320
-	PINCTRL_PIN(7, "RXD0"),
321
-	PINCTRL_PIN(8, "SPI_WP"),
322
-	PINCTRL_PIN(9, "SPI_HOLD"),
323
-	PINCTRL_PIN(10, "SPI_CLK"),
324
-	PINCTRL_PIN(11, "SPI_MOSI"),
325
-	PINCTRL_PIN(12, "SPI_MISO"),
326
-	PINCTRL_PIN(13, "SPI_CS"),
327
-	PINCTRL_PIN(14, "I2C_SDA"),
328
-	PINCTRL_PIN(15, "I2C_SCL"),
329
-	PINCTRL_PIN(16, "I2S2_IN"),
330
-	PINCTRL_PIN(17, "I2S3_IN"),
331
-	PINCTRL_PIN(18, "I2S4_IN"),
332
-	PINCTRL_PIN(19, "I2S2_OUT"),
333
-	PINCTRL_PIN(20, "I2S3_OUT"),
334
-	PINCTRL_PIN(21, "I2S4_OUT"),
335
-	PINCTRL_PIN(22, "GPIO_B"),
336
-	PINCTRL_PIN(23, "MDC"),
337
-	PINCTRL_PIN(24, "MDIO"),
338
-	PINCTRL_PIN(25, "G2_TXD0"),
339
-	PINCTRL_PIN(26, "G2_TXD1"),
340
-	PINCTRL_PIN(27, "G2_TXD2"),
341
-	PINCTRL_PIN(28, "G2_TXD3"),
342
-	PINCTRL_PIN(29, "G2_TXEN"),
343
-	PINCTRL_PIN(30, "G2_TXC"),
344
-	PINCTRL_PIN(31, "G2_RXD0"),
345
-	PINCTRL_PIN(32, "G2_RXD1"),
346
-	PINCTRL_PIN(33, "G2_RXD2"),
347
-	PINCTRL_PIN(34, "G2_RXD3"),
348
-	PINCTRL_PIN(35, "G2_RXDV"),
349
-	PINCTRL_PIN(36, "G2_RXC"),
350
-	PINCTRL_PIN(37, "NCEB"),
351
-	PINCTRL_PIN(38, "NWEB"),
352
-	PINCTRL_PIN(39, "NREB"),
353
-	PINCTRL_PIN(40, "NDL4"),
354
-	PINCTRL_PIN(41, "NDL5"),
355
-	PINCTRL_PIN(42, "NDL6"),
356
-	PINCTRL_PIN(43, "NDL7"),
357
-	PINCTRL_PIN(44, "NRB"),
358
-	PINCTRL_PIN(45, "NCLE"),
359
-	PINCTRL_PIN(46, "NALE"),
360
-	PINCTRL_PIN(47, "NDL0"),
361
-	PINCTRL_PIN(48, "NDL1"),
362
-	PINCTRL_PIN(49, "NDL2"),
363
-	PINCTRL_PIN(50, "NDL3"),
364
-	PINCTRL_PIN(51, "MDI_TP_P0"),
365
-	PINCTRL_PIN(52, "MDI_TN_P0"),
366
-	PINCTRL_PIN(53, "MDI_RP_P0"),
367
-	PINCTRL_PIN(54, "MDI_RN_P0"),
368
-	PINCTRL_PIN(55, "MDI_TP_P1"),
369
-	PINCTRL_PIN(56, "MDI_TN_P1"),
370
-	PINCTRL_PIN(57, "MDI_RP_P1"),
371
-	PINCTRL_PIN(58, "MDI_RN_P1"),
372
-	PINCTRL_PIN(59, "MDI_RP_P2"),
373
-	PINCTRL_PIN(60, "MDI_RN_P2"),
374
-	PINCTRL_PIN(61, "MDI_TP_P2"),
375
-	PINCTRL_PIN(62, "MDI_TN_P2"),
376
-	PINCTRL_PIN(63, "MDI_TP_P3"),
377
-	PINCTRL_PIN(64, "MDI_TN_P3"),
378
-	PINCTRL_PIN(65, "MDI_RP_P3"),
379
-	PINCTRL_PIN(66, "MDI_RN_P3"),
380
-	PINCTRL_PIN(67, "MDI_RP_P4"),
381
-	PINCTRL_PIN(68, "MDI_RN_P4"),
382
-	PINCTRL_PIN(69, "MDI_TP_P4"),
383
-	PINCTRL_PIN(70, "MDI_TN_P4"),
384
-	PINCTRL_PIN(71, "PMIC_SCL"),
385
-	PINCTRL_PIN(72, "PMIC_SDA"),
386
-	PINCTRL_PIN(73, "SPIC1_CLK"),
387
-	PINCTRL_PIN(74, "SPIC1_MOSI"),
388
-	PINCTRL_PIN(75, "SPIC1_MISO"),
389
-	PINCTRL_PIN(76, "SPIC1_CS"),
390
-	PINCTRL_PIN(77, "GPIO_D"),
391
-	PINCTRL_PIN(78, "WATCHDOG"),
392
-	PINCTRL_PIN(79, "RTS3_N"),
393
-	PINCTRL_PIN(80, "CTS3_N"),
394
-	PINCTRL_PIN(81, "TXD3"),
395
-	PINCTRL_PIN(82, "RXD3"),
396
-	PINCTRL_PIN(83, "PERST0_N"),
397
-	PINCTRL_PIN(84, "PERST1_N"),
398
-	PINCTRL_PIN(85, "WLED_N"),
399
-	PINCTRL_PIN(86, "EPHY_LED0_N"),
400
-	PINCTRL_PIN(87, "AUXIN0"),
401
-	PINCTRL_PIN(88, "AUXIN1"),
402
-	PINCTRL_PIN(89, "AUXIN2"),
403
-	PINCTRL_PIN(90, "AUXIN3"),
404
-	PINCTRL_PIN(91, "TXD4"),
405
-	PINCTRL_PIN(92, "RXD4"),
406
-	PINCTRL_PIN(93, "RTS4_N"),
407
-	PINCTRL_PIN(94, "CTS4_N"),
408
-	PINCTRL_PIN(95, "PWM1"),
409
-	PINCTRL_PIN(96, "PWM2"),
410
-	PINCTRL_PIN(97, "PWM3"),
411
-	PINCTRL_PIN(98, "PWM4"),
412
-	PINCTRL_PIN(99, "PWM5"),
413
-	PINCTRL_PIN(100, "PWM6"),
414
-	PINCTRL_PIN(101, "PWM7"),
415
-	PINCTRL_PIN(102, "GPIO_E"),
155
+static const struct mtk_pin_desc mt7622_pins[] = {
156
+	MT7622_PIN(0, "GPIO_A"),
157
+	MT7622_PIN(1, "I2S1_IN"),
158
+	MT7622_PIN(2, "I2S1_OUT"),
159
+	MT7622_PIN(3, "I2S_BCLK"),
160
+	MT7622_PIN(4, "I2S_WS"),
161
+	MT7622_PIN(5, "I2S_MCLK"),
162
+	MT7622_PIN(6, "TXD0"),
163
+	MT7622_PIN(7, "RXD0"),
164
+	MT7622_PIN(8, "SPI_WP"),
165
+	MT7622_PIN(9, "SPI_HOLD"),
166
+	MT7622_PIN(10, "SPI_CLK"),
167
+	MT7622_PIN(11, "SPI_MOSI"),
168
+	MT7622_PIN(12, "SPI_MISO"),
169
+	MT7622_PIN(13, "SPI_CS"),
170
+	MT7622_PIN(14, "I2C_SDA"),
171
+	MT7622_PIN(15, "I2C_SCL"),
172
+	MT7622_PIN(16, "I2S2_IN"),
173
+	MT7622_PIN(17, "I2S3_IN"),
174
+	MT7622_PIN(18, "I2S4_IN"),
175
+	MT7622_PIN(19, "I2S2_OUT"),
176
+	MT7622_PIN(20, "I2S3_OUT"),
177
+	MT7622_PIN(21, "I2S4_OUT"),
178
+	MT7622_PIN(22, "GPIO_B"),
179
+	MT7622_PIN(23, "MDC"),
180
+	MT7622_PIN(24, "MDIO"),
181
+	MT7622_PIN(25, "G2_TXD0"),
182
+	MT7622_PIN(26, "G2_TXD1"),
183
+	MT7622_PIN(27, "G2_TXD2"),
184
+	MT7622_PIN(28, "G2_TXD3"),
185
+	MT7622_PIN(29, "G2_TXEN"),
186
+	MT7622_PIN(30, "G2_TXC"),
187
+	MT7622_PIN(31, "G2_RXD0"),
188
+	MT7622_PIN(32, "G2_RXD1"),
189
+	MT7622_PIN(33, "G2_RXD2"),
190
+	MT7622_PIN(34, "G2_RXD3"),
191
+	MT7622_PIN(35, "G2_RXDV"),
192
+	MT7622_PIN(36, "G2_RXC"),
193
+	MT7622_PIN(37, "NCEB"),
194
+	MT7622_PIN(38, "NWEB"),
195
+	MT7622_PIN(39, "NREB"),
196
+	MT7622_PIN(40, "NDL4"),
197
+	MT7622_PIN(41, "NDL5"),
198
+	MT7622_PIN(42, "NDL6"),
199
+	MT7622_PIN(43, "NDL7"),
200
+	MT7622_PIN(44, "NRB"),
201
+	MT7622_PIN(45, "NCLE"),
202
+	MT7622_PIN(46, "NALE"),
203
+	MT7622_PIN(47, "NDL0"),
204
+	MT7622_PIN(48, "NDL1"),
205
+	MT7622_PIN(49, "NDL2"),
206
+	MT7622_PIN(50, "NDL3"),
207
+	MT7622_PIN(51, "MDI_TP_P0"),
208
+	MT7622_PIN(52, "MDI_TN_P0"),
209
+	MT7622_PIN(53, "MDI_RP_P0"),
210
+	MT7622_PIN(54, "MDI_RN_P0"),
211
+	MT7622_PIN(55, "MDI_TP_P1"),
212
+	MT7622_PIN(56, "MDI_TN_P1"),
213
+	MT7622_PIN(57, "MDI_RP_P1"),
214
+	MT7622_PIN(58, "MDI_RN_P1"),
215
+	MT7622_PIN(59, "MDI_RP_P2"),
216
+	MT7622_PIN(60, "MDI_RN_P2"),
217
+	MT7622_PIN(61, "MDI_TP_P2"),
218
+	MT7622_PIN(62, "MDI_TN_P2"),
219
+	MT7622_PIN(63, "MDI_TP_P3"),
220
+	MT7622_PIN(64, "MDI_TN_P3"),
221
+	MT7622_PIN(65, "MDI_RP_P3"),
222
+	MT7622_PIN(66, "MDI_RN_P3"),
223
+	MT7622_PIN(67, "MDI_RP_P4"),
224
+	MT7622_PIN(68, "MDI_RN_P4"),
225
+	MT7622_PIN(69, "MDI_TP_P4"),
226
+	MT7622_PIN(70, "MDI_TN_P4"),
227
+	MT7622_PIN(71, "PMIC_SCL"),
228
+	MT7622_PIN(72, "PMIC_SDA"),
229
+	MT7622_PIN(73, "SPIC1_CLK"),
230
+	MT7622_PIN(74, "SPIC1_MOSI"),
231
+	MT7622_PIN(75, "SPIC1_MISO"),
232
+	MT7622_PIN(76, "SPIC1_CS"),
233
+	MT7622_PIN(77, "GPIO_D"),
234
+	MT7622_PIN(78, "WATCHDOG"),
235
+	MT7622_PIN(79, "RTS3_N"),
236
+	MT7622_PIN(80, "CTS3_N"),
237
+	MT7622_PIN(81, "TXD3"),
238
+	MT7622_PIN(82, "RXD3"),
239
+	MT7622_PIN(83, "PERST0_N"),
240
+	MT7622_PIN(84, "PERST1_N"),
241
+	MT7622_PIN(85, "WLED_N"),
242
+	MT7622_PIN(86, "EPHY_LED0_N"),
243
+	MT7622_PIN(87, "AUXIN0"),
244
+	MT7622_PIN(88, "AUXIN1"),
245
+	MT7622_PIN(89, "AUXIN2"),
246
+	MT7622_PIN(90, "AUXIN3"),
247
+	MT7622_PIN(91, "TXD4"),
248
+	MT7622_PIN(92, "RXD4"),
249
+	MT7622_PIN(93, "RTS4_N"),
250
+	MT7622_PIN(94, "CTS4_N"),
251
+	MT7622_PIN(95, "PWM1"),
252
+	MT7622_PIN(96, "PWM2"),
253
+	MT7622_PIN(97, "PWM3"),
254
+	MT7622_PIN(98, "PWM4"),
255
+	MT7622_PIN(99, "PWM5"),
256
+	MT7622_PIN(100, "PWM6"),
257
+	MT7622_PIN(101, "PWM7"),
258
+	MT7622_PIN(102, "GPIO_E"),
416259 };
417260 
418261 /* List all groups consisting of these pins dedicated to the enablement of
419262  * certain hardware block and the corresponding mode for all of the pins. The
420263  * hardware probably has multiple combinations of these pinouts.
421264  */
265
+
266
+/* ANTSEL */
267
+static int mt7622_antsel0_pins[] = { 91, };
268
+static int mt7622_antsel0_funcs[] = { 5, };
269
+static int mt7622_antsel1_pins[] = { 92, };
270
+static int mt7622_antsel1_funcs[] = { 5, };
271
+static int mt7622_antsel2_pins[] = { 93, };
272
+static int mt7622_antsel2_funcs[] = { 5, };
273
+static int mt7622_antsel3_pins[] = { 94, };
274
+static int mt7622_antsel3_funcs[] = { 5, };
275
+static int mt7622_antsel4_pins[] = { 95, };
276
+static int mt7622_antsel4_funcs[] = { 5, };
277
+static int mt7622_antsel5_pins[] = { 96, };
278
+static int mt7622_antsel5_funcs[] = { 5, };
279
+static int mt7622_antsel6_pins[] = { 97, };
280
+static int mt7622_antsel6_funcs[] = { 5, };
281
+static int mt7622_antsel7_pins[] = { 98, };
282
+static int mt7622_antsel7_funcs[] = { 5, };
283
+static int mt7622_antsel8_pins[] = { 99, };
284
+static int mt7622_antsel8_funcs[] = { 5, };
285
+static int mt7622_antsel9_pins[] = { 100, };
286
+static int mt7622_antsel9_funcs[] = { 5, };
287
+static int mt7622_antsel10_pins[] = { 101, };
288
+static int mt7622_antsel10_funcs[] = { 5, };
289
+static int mt7622_antsel11_pins[] = { 102, };
290
+static int mt7622_antsel11_funcs[] = { 5, };
291
+static int mt7622_antsel12_pins[] = { 73, };
292
+static int mt7622_antsel12_funcs[] = { 5, };
293
+static int mt7622_antsel13_pins[] = { 74, };
294
+static int mt7622_antsel13_funcs[] = { 5, };
295
+static int mt7622_antsel14_pins[] = { 75, };
296
+static int mt7622_antsel14_funcs[] = { 5, };
297
+static int mt7622_antsel15_pins[] = { 76, };
298
+static int mt7622_antsel15_funcs[] = { 5, };
299
+static int mt7622_antsel16_pins[] = { 77, };
300
+static int mt7622_antsel16_funcs[] = { 5, };
301
+static int mt7622_antsel17_pins[] = { 22, };
302
+static int mt7622_antsel17_funcs[] = { 5, };
303
+static int mt7622_antsel18_pins[] = { 79, };
304
+static int mt7622_antsel18_funcs[] = { 5, };
305
+static int mt7622_antsel19_pins[] = { 80, };
306
+static int mt7622_antsel19_funcs[] = { 5, };
307
+static int mt7622_antsel20_pins[] = { 81, };
308
+static int mt7622_antsel20_funcs[] = { 5, };
309
+static int mt7622_antsel21_pins[] = { 82, };
310
+static int mt7622_antsel21_funcs[] = { 5, };
311
+static int mt7622_antsel22_pins[] = { 14, };
312
+static int mt7622_antsel22_funcs[] = { 5, };
313
+static int mt7622_antsel23_pins[] = { 15, };
314
+static int mt7622_antsel23_funcs[] = { 5, };
315
+static int mt7622_antsel24_pins[] = { 16, };
316
+static int mt7622_antsel24_funcs[] = { 5, };
317
+static int mt7622_antsel25_pins[] = { 17, };
318
+static int mt7622_antsel25_funcs[] = { 5, };
319
+static int mt7622_antsel26_pins[] = { 18, };
320
+static int mt7622_antsel26_funcs[] = { 5, };
321
+static int mt7622_antsel27_pins[] = { 19, };
322
+static int mt7622_antsel27_funcs[] = { 5, };
323
+static int mt7622_antsel28_pins[] = { 20, };
324
+static int mt7622_antsel28_funcs[] = { 5, };
325
+static int mt7622_antsel29_pins[] = { 21, };
326
+static int mt7622_antsel29_funcs[] = { 5, };
422327 
423328 /* EMMC */
424329 static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
....@@ -700,6 +605,36 @@
700605 static int mt7622_wled_funcs[] = { 0, };
701606 
702607 static const struct group_desc mt7622_groups[] = {
608
+	PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0),
609
+	PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1),
610
+	PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2),
611
+	PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3),
612
+	PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4),
613
+	PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5),
614
+	PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6),
615
+	PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7),
616
+	PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8),
617
+	PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9),
618
+	PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10),
619
+	PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11),
620
+	PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12),
621
+	PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13),
622
+	PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14),
623
+	PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15),
624
+	PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16),
625
+	PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17),
626
+	PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18),
627
+	PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19),
628
+	PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20),
629
+	PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21),
630
+	PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22),
631
+	PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23),
632
+	PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24),
633
+	PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25),
634
+	PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26),
635
+	PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27),
636
+	PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28),
637
+	PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29),
703638 	PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
704639 	PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
705640 	PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
....@@ -820,6 +755,16 @@
820755 /* Joint those groups owning the same capability in user point of view which
821756  * allows that people tend to use through the device tree.
822757  */
758
+static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2",
759
+					      "antsel3", "antsel4", "antsel5",
760
+					      "antsel6", "antsel7", "antsel8",
761
+					      "antsel9", "antsel10", "antsel11",
762
+					      "antsel12", "antsel13", "antsel14",
763
+					      "antsel15", "antsel16", "antsel17",
764
+					      "antsel18", "antsel19", "antsel20",
765
+					      "antsel21", "antsel22", "antsel23",
766
+					      "antsel24", "antsel25", "antsel26",
767
+					      "antsel27", "antsel28", "antsel29",};
823768 static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
824769 static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
825770 						"esw_p2_p3_p4", "mdc_mdio",
....@@ -889,6 +834,7 @@
889834 static const char *mt7622_wdt_groups[] = { "watchdog", };
890835 
891836 static const struct function_desc mt7622_functions[] = {
837
+	{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
892838 	{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
893839 	{"eth",	mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
894840 	{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
....@@ -906,18 +852,6 @@
906852 	{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
907853 };
908854 
909
-static const struct pinconf_generic_params mtk_custom_bindings[] = {
910
-	{"mediatek,tdsel",	MTK_PIN_CONFIG_TDSEL,		0},
911
-	{"mediatek,rdsel",	MTK_PIN_CONFIG_RDSEL,		0},
912
-};
913
-
914
-#ifdef CONFIG_DEBUG_FS
915
-static const struct pin_config_item mtk_conf_items[] = {
916
-	PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
917
-	PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
918
-};
919
-#endif
920
-
921855 static const struct mtk_eint_hw mt7622_eint_hw = {
922856 	.port_mask = 7,
923857 	.ports     = 7,
....@@ -934,830 +868,38 @@
934868 	.funcs = mt7622_functions,
935869 	.nfuncs = ARRAY_SIZE(mt7622_functions),
936870 	.eint_hw = &mt7622_eint_hw,
871
+	.gpio_m	= 1,
872
+	.ies_present = false,
873
+	.base_names = mtk_default_register_base_names,
874
+	.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
875
+	.bias_disable_set = mtk_pinconf_bias_disable_set,
876
+	.bias_disable_get = mtk_pinconf_bias_disable_get,
877
+	.bias_set = mtk_pinconf_bias_set,
878
+	.bias_get = mtk_pinconf_bias_get,
879
+	.drive_set = mtk_pinconf_drive_set,
880
+	.drive_get = mtk_pinconf_drive_get,
937881 };
938882 
939
-static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
940
-{
941
-	writel_relaxed(val, pctl->base + reg);
942
-}
943
-
944
-static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg)
945
-{
946
-	return readl_relaxed(pctl->base + reg);
947
-}
948
-
949
-static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set)
950
-{
951
-	u32 val;
952
-
953
-	val = mtk_r32(pctl, reg);
954
-	val &= ~mask;
955
-	val |= set;
956
-	mtk_w32(pctl, reg, val);
957
-}
958
-
959
-static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin,
960
-				   const struct mtk_pin_reg_calc *rc,
961
-				   struct mtk_pin_field *pfd)
962
-{
963
-	const struct mtk_pin_field_calc *c, *e;
964
-	u32 bits;
965
-
966
-	c = rc->range;
967
-	e = c + rc->nranges;
968
-
969
-	while (c < e) {
970
-		if (pin >= c->s_pin && pin <= c->e_pin)
971
-			break;
972
-		c++;
973
-	}
974
-
975
-	if (c >= e) {
976
-		dev_err(hw->dev, "Out of range for pin = %d\n", pin);
977
-		return -EINVAL;
978
-	}
979
-
980
-	/* Caculated bits as the overall offset the pin is located at */
981
-	bits = c->s_bit + (pin - c->s_pin) * (c->x_bits);
982
-
983
-	/* Fill pfd from bits and 32-bit register applied is assumed */
984
-	pfd->offset = c->s_addr + c->x_addrs * (bits / 32);
985
-	pfd->bitpos = bits % 32;
986
-	pfd->mask = (1 << c->x_bits) - 1;
987
-
988
-	/* pfd->next is used for indicating that bit wrapping-around happens
989
-	 * which requires the manipulation for bit 0 starting in the next
990
-	 * register to form the complete field read/write.
991
-	 */
992
-	pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0;
993
-
994
-	return 0;
995
-}
996
-
997
-static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin,
998
-				int field, struct mtk_pin_field *pfd)
999
-{
1000
-	const struct mtk_pin_reg_calc *rc;
1001
-
1002
-	if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
1003
-		dev_err(hw->dev, "Invalid Field %d\n", field);
1004
-		return -EINVAL;
1005
-	}
1006
-
1007
-	if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
1008
-		rc = &hw->soc->reg_cal[field];
1009
-	} else {
1010
-		dev_err(hw->dev, "Undefined range for field %d\n", field);
1011
-		return -EINVAL;
1012
-	}
1013
-
1014
-	return mtk_hw_pin_field_lookup(hw, pin, rc, pfd);
1015
-}
1016
-
1017
-static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
1018
-{
1019
-	*l = 32 - pf->bitpos;
1020
-	*h = get_count_order(pf->mask) - *l;
1021
-}
1022
-
1023
-static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
1024
-				     struct mtk_pin_field *pf, int value)
1025
-{
1026
-	int nbits_l, nbits_h;
1027
-
1028
-	mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
1029
-
1030
-	mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos,
1031
-		(value & pf->mask) << pf->bitpos);
1032
-
1033
-	mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1,
1034
-		(value & pf->mask) >> nbits_l);
1035
-}
1036
-
1037
-static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
1038
-				    struct mtk_pin_field *pf, int *value)
1039
-{
1040
-	int nbits_l, nbits_h, h, l;
1041
-
1042
-	mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
1043
-
1044
-	l  = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
1045
-	h  = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
1046
-
1047
-	*value = (h << nbits_l) | l;
1048
-}
1049
-
1050
-static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field,
1051
-			    int value)
1052
-{
1053
-	struct mtk_pin_field pf;
1054
-	int err;
1055
-
1056
-	err = mtk_hw_pin_field_get(hw, pin, field, &pf);
1057
-	if (err)
1058
-		return err;
1059
-
1060
-	if (!pf.next)
1061
-		mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos,
1062
-			(value & pf.mask) << pf.bitpos);
1063
-	else
1064
-		mtk_hw_write_cross_field(hw, &pf, value);
1065
-
1066
-	return 0;
1067
-}
1068
-
1069
-static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field,
1070
-			    int *value)
1071
-{
1072
-	struct mtk_pin_field pf;
1073
-	int err;
1074
-
1075
-	err = mtk_hw_pin_field_get(hw, pin, field, &pf);
1076
-	if (err)
1077
-		return err;
1078
-
1079
-	if (!pf.next)
1080
-		*value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask;
1081
-	else
1082
-		mtk_hw_read_cross_field(hw, &pf, value);
1083
-
1084
-	return 0;
1085
-}
1086
-
1087
-static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
1088
-			      unsigned int selector, unsigned int group)
1089
-{
1090
-	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1091
-	struct function_desc *func;
1092
-	struct group_desc *grp;
1093
-	int i;
1094
-
1095
-	func = pinmux_generic_get_function(pctldev, selector);
1096
-	if (!func)
1097
-		return -EINVAL;
1098
-
1099
-	grp = pinctrl_generic_get_group(pctldev, group);
1100
-	if (!grp)
1101
-		return -EINVAL;
1102
-
1103
-	dev_dbg(pctldev->dev, "enable function %s group %s\n",
1104
-		func->name, grp->name);
1105
-
1106
-	for (i = 0; i < grp->num_pins; i++) {
1107
-		int *pin_modes = grp->data;
1108
-
1109
-		mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE,
1110
-				 pin_modes[i]);
1111
-	}
1112
-
1113
-	return 0;
1114
-}
1115
-
1116
-static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
1117
-					  struct pinctrl_gpio_range *range,
1118
-					  unsigned int pin)
1119
-{
1120
-	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1121
-
1122
-	return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE);
1123
-}
1124
-
1125
-static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
1126
-					 struct pinctrl_gpio_range *range,
1127
-					 unsigned int pin, bool input)
1128
-{
1129
-	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1130
-
1131
-	/* hardware would take 0 as input direction */
1132
-	return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input);
1133
-}
1134
-
1135
-static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
1136
-			   unsigned int pin, unsigned long *config)
1137
-{
1138
-	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1139
-	u32 param = pinconf_to_config_param(*config);
1140
-	int val, val2, err, reg, ret = 1;
1141
-
1142
-	switch (param) {
1143
-	case PIN_CONFIG_BIAS_DISABLE:
1144
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val);
1145
-		if (err)
1146
-			return err;
1147
-
1148
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2);
1149
-		if (err)
1150
-			return err;
1151
-
1152
-		if (val || val2)
1153
-			return -EINVAL;
1154
-
1155
-		break;
1156
-	case PIN_CONFIG_BIAS_PULL_UP:
1157
-	case PIN_CONFIG_BIAS_PULL_DOWN:
1158
-	case PIN_CONFIG_SLEW_RATE:
1159
-		reg = (param == PIN_CONFIG_BIAS_PULL_UP) ?
1160
-		      PINCTRL_PIN_REG_PU :
1161
-		      (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
1162
-		      PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR;
1163
-
1164
-		err = mtk_hw_get_value(hw, pin, reg, &val);
1165
-		if (err)
1166
-			return err;
1167
-
1168
-		if (!val)
1169
-			return -EINVAL;
1170
-
1171
-		break;
1172
-	case PIN_CONFIG_INPUT_ENABLE:
1173
-	case PIN_CONFIG_OUTPUT_ENABLE:
1174
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
1175
-		if (err)
1176
-			return err;
1177
-
1178
-		/* HW takes input mode as zero; output mode as non-zero */
1179
-		if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
1180
-		    (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
1181
-			return -EINVAL;
1182
-
1183
-		break;
1184
-	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1185
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
1186
-		if (err)
1187
-			return err;
1188
-
1189
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2);
1190
-		if (err)
1191
-			return err;
1192
-
1193
-		if (val || !val2)
1194
-			return -EINVAL;
1195
-
1196
-		break;
1197
-	case PIN_CONFIG_DRIVE_STRENGTH:
1198
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val);
1199
-		if (err)
1200
-			return err;
1201
-
1202
-		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2);
1203
-		if (err)
1204
-			return err;
1205
-
1206
-		/* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
1207
-		 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
1208
-		 */
1209
-		ret = ((val2 << 1) + val + 1) * 4;
1210
-
1211
-		break;
1212
-	case MTK_PIN_CONFIG_TDSEL:
1213
-	case MTK_PIN_CONFIG_RDSEL:
1214
-		reg = (param == MTK_PIN_CONFIG_TDSEL) ?
1215
-		       PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1216
-
1217
-		err = mtk_hw_get_value(hw, pin, reg, &val);
1218
-		if (err)
1219
-			return err;
1220
-
1221
-		ret = val;
1222
-
1223
-		break;
1224
-	default:
1225
-		return -ENOTSUPP;
1226
-	}
1227
-
1228
-	*config = pinconf_to_config_packed(param, ret);
1229
-
1230
-	return 0;
1231
-}
1232
-
1233
-static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1234
-			   unsigned long *configs, unsigned int num_configs)
1235
-{
1236
-	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1237
-	u32 reg, param, arg;
1238
-	int cfg, err = 0;
1239
-
1240
-	for (cfg = 0; cfg < num_configs; cfg++) {
1241
-		param = pinconf_to_config_param(configs[cfg]);
1242
-		arg = pinconf_to_config_argument(configs[cfg]);
1243
-
1244
-		switch (param) {
1245
-		case PIN_CONFIG_BIAS_DISABLE:
1246
-		case PIN_CONFIG_BIAS_PULL_UP:
1247
-		case PIN_CONFIG_BIAS_PULL_DOWN:
1248
-			arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1249
-			       (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2;
1250
-
1251
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU,
1252
-					       arg & 1);
1253
-			if (err)
1254
-				goto err;
1255
-
1256
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD,
1257
-					       !!(arg & 2));
1258
-			if (err)
1259
-				goto err;
1260
-			break;
1261
-		case PIN_CONFIG_OUTPUT_ENABLE:
1262
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
1263
-					       MTK_DISABLE);
1264
-			if (err)
1265
-				goto err;
1266
-			/* else: fall through */
1267
-		case PIN_CONFIG_INPUT_ENABLE:
1268
-		case PIN_CONFIG_SLEW_RATE:
1269
-			reg = (param == PIN_CONFIG_SLEW_RATE) ?
1270
-			       PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR;
1271
-
1272
-			arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 :
1273
-			      (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg;
1274
-			err = mtk_hw_set_value(hw, pin, reg, arg);
1275
-			if (err)
1276
-				goto err;
1277
-
1278
-			break;
1279
-		case PIN_CONFIG_OUTPUT:
1280
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
1281
-					       MTK_OUTPUT);
1282
-			if (err)
1283
-				goto err;
1284
-
1285
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO,
1286
-					       arg);
1287
-			if (err)
1288
-				goto err;
1289
-			break;
1290
-		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1291
-			/* arg = 1: Input mode & SMT enable ;
1292
-			 * arg = 0: Output mode & SMT disable
1293
-			 */
1294
-			arg = arg ? 2 : 1;
1295
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
1296
-					       arg & 1);
1297
-			if (err)
1298
-				goto err;
1299
-
1300
-			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
1301
-					       !!(arg & 2));
1302
-			if (err)
1303
-				goto err;
1304
-			break;
1305
-		case PIN_CONFIG_DRIVE_STRENGTH:
1306
-			/* 4mA when (e8, e4) = (0, 0);
1307
-			 * 8mA when (e8, e4) = (0, 1);
1308
-			 * 12mA when (e8, e4) = (1, 0);
1309
-			 * 16mA when (e8, e4) = (1, 1)
1310
-			 */
1311
-			if (!(arg % 4) && (arg >= 4 && arg <= 16)) {
1312
-				arg = arg / 4 - 1;
1313
-				err = mtk_hw_set_value(hw, pin,
1314
-						       PINCTRL_PIN_REG_E4,
1315
-						       arg & 0x1);
1316
-				if (err)
1317
-					goto err;
1318
-
1319
-				err = mtk_hw_set_value(hw, pin,
1320
-						       PINCTRL_PIN_REG_E8,
1321
-						       (arg & 0x2) >> 1);
1322
-				if (err)
1323
-					goto err;
1324
-			} else {
1325
-				err = -ENOTSUPP;
1326
-			}
1327
-			break;
1328
-		case MTK_PIN_CONFIG_TDSEL:
1329
-		case MTK_PIN_CONFIG_RDSEL:
1330
-			reg = (param == MTK_PIN_CONFIG_TDSEL) ?
1331
-			       PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1332
-
1333
-			err = mtk_hw_set_value(hw, pin, reg, arg);
1334
-			if (err)
1335
-				goto err;
1336
-			break;
1337
-		default:
1338
-			err = -ENOTSUPP;
1339
-		}
1340
-	}
1341
-err:
1342
-	return err;
1343
-}
1344
-
1345
-static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
1346
-				 unsigned int group, unsigned long *config)
1347
-{
1348
-	const unsigned int *pins;
1349
-	unsigned int i, npins, old = 0;
1350
-	int ret;
1351
-
1352
-	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1353
-	if (ret)
1354
-		return ret;
1355
-
1356
-	for (i = 0; i < npins; i++) {
1357
-		if (mtk_pinconf_get(pctldev, pins[i], config))
1358
-			return -ENOTSUPP;
1359
-
1360
-		/* configs do not match between two pins */
1361
-		if (i && old != *config)
1362
-			return -ENOTSUPP;
1363
-
1364
-		old = *config;
1365
-	}
1366
-
1367
-	return 0;
1368
-}
1369
-
1370
-static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
1371
-				 unsigned int group, unsigned long *configs,
1372
-				 unsigned int num_configs)
1373
-{
1374
-	const unsigned int *pins;
1375
-	unsigned int i, npins;
1376
-	int ret;
1377
-
1378
-	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1379
-	if (ret)
1380
-		return ret;
1381
-
1382
-	for (i = 0; i < npins; i++) {
1383
-		ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
1384
-		if (ret)
1385
-			return ret;
1386
-	}
1387
-
1388
-	return 0;
1389
-}
1390
-
1391
-static const struct pinctrl_ops mtk_pctlops = {
1392
-	.get_groups_count = pinctrl_generic_get_group_count,
1393
-	.get_group_name = pinctrl_generic_get_group_name,
1394
-	.get_group_pins = pinctrl_generic_get_group_pins,
1395
-	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1396
-	.dt_free_map = pinconf_generic_dt_free_map,
1397
-};
1398
-
1399
-static const struct pinmux_ops mtk_pmxops = {
1400
-	.get_functions_count = pinmux_generic_get_function_count,
1401
-	.get_function_name = pinmux_generic_get_function_name,
1402
-	.get_function_groups = pinmux_generic_get_function_groups,
1403
-	.set_mux = mtk_pinmux_set_mux,
1404
-	.gpio_request_enable = mtk_pinmux_gpio_request_enable,
1405
-	.gpio_set_direction = mtk_pinmux_gpio_set_direction,
1406
-	.strict = true,
1407
-};
1408
-
1409
-static const struct pinconf_ops mtk_confops = {
1410
-	.is_generic = true,
1411
-	.pin_config_get = mtk_pinconf_get,
1412
-	.pin_config_set = mtk_pinconf_set,
1413
-	.pin_config_group_get = mtk_pinconf_group_get,
1414
-	.pin_config_group_set = mtk_pinconf_group_set,
1415
-	.pin_config_config_dbg_show = pinconf_generic_dump_config,
1416
-};
1417
-
1418
-static struct pinctrl_desc mtk_desc = {
1419
-	.name = PINCTRL_PINCTRL_DEV,
1420
-	.pctlops = &mtk_pctlops,
1421
-	.pmxops = &mtk_pmxops,
1422
-	.confops = &mtk_confops,
1423
-	.owner = THIS_MODULE,
1424
-};
1425
-
1426
-static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
1427
-{
1428
-	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1429
-	int value, err;
1430
-
1431
-	err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
1432
-	if (err)
1433
-		return err;
1434
-
1435
-	return !!value;
1436
-}
1437
-
1438
-static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
1439
-{
1440
-	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1441
-
1442
-	mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
1443
-}
1444
-
1445
-static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
1446
-{
1447
-	return pinctrl_gpio_direction_input(chip->base + gpio);
1448
-}
1449
-
1450
-static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
1451
-				     int value)
1452
-{
1453
-	mtk_gpio_set(chip, gpio, value);
1454
-
1455
-	return pinctrl_gpio_direction_output(chip->base + gpio);
1456
-}
1457
-
1458
-static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
1459
-{
1460
-	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1461
-	unsigned long eint_n;
1462
-
1463
-	if (!hw->eint)
1464
-		return -ENOTSUPP;
1465
-
1466
-	eint_n = offset;
1467
-
1468
-	return mtk_eint_find_irq(hw->eint, eint_n);
1469
-}
1470
-
1471
-static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1472
-			       unsigned long config)
1473
-{
1474
-	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
1475
-	unsigned long eint_n;
1476
-	u32 debounce;
1477
-
1478
-	if (!hw->eint ||
1479
-	    pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1480
-		return -ENOTSUPP;
1481
-
1482
-	debounce = pinconf_to_config_argument(config);
1483
-	eint_n = offset;
1484
-
1485
-	return mtk_eint_set_debounce(hw->eint, eint_n, debounce);
1486
-}
1487
-
1488
-static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
1489
-{
1490
-	struct gpio_chip *chip = &hw->chip;
1491
-	int ret;
1492
-
1493
-	chip->label		= PINCTRL_PINCTRL_DEV;
1494
-	chip->parent		= hw->dev;
1495
-	chip->request		= gpiochip_generic_request;
1496
-	chip->free		= gpiochip_generic_free;
1497
-	chip->direction_input	= mtk_gpio_direction_input;
1498
-	chip->direction_output	= mtk_gpio_direction_output;
1499
-	chip->get		= mtk_gpio_get;
1500
-	chip->set		= mtk_gpio_set;
1501
-	chip->to_irq		= mtk_gpio_to_irq,
1502
-	chip->set_config	= mtk_gpio_set_config,
1503
-	chip->base		= -1;
1504
-	chip->ngpio		= hw->soc->npins;
1505
-	chip->of_node		= np;
1506
-	chip->of_gpio_n_cells	= 2;
1507
-
1508
-	ret = gpiochip_add_data(chip, hw);
1509
-	if (ret < 0)
1510
-		return ret;
1511
-
1512
-	/* Just for backward compatible for these old pinctrl nodes without
1513
-	 * "gpio-ranges" property. Otherwise, called directly from a
1514
-	 * DeviceTree-supported pinctrl driver is DEPRECATED.
1515
-	 * Please see Section 2.1 of
1516
-	 * Documentation/devicetree/bindings/gpio/gpio.txt on how to
1517
-	 * bind pinctrl and gpio drivers via the "gpio-ranges" property.
1518
-	 */
1519
-	if (!of_find_property(np, "gpio-ranges", NULL)) {
1520
-		ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
1521
-					     chip->ngpio);
1522
-		if (ret < 0) {
1523
-			gpiochip_remove(chip);
1524
-			return ret;
1525
-		}
1526
-	}
1527
-
1528
-	return 0;
1529
-}
1530
-
1531
-static int mtk_build_groups(struct mtk_pinctrl *hw)
1532
-{
1533
-	int err, i;
1534
-
1535
-	for (i = 0; i < hw->soc->ngrps; i++) {
1536
-		const struct group_desc *group = hw->soc->grps + i;
1537
-
1538
-		err = pinctrl_generic_add_group(hw->pctrl, group->name,
1539
-						group->pins, group->num_pins,
1540
-						group->data);
1541
-		if (err < 0) {
1542
-			dev_err(hw->dev, "Failed to register group %s\n",
1543
-				group->name);
1544
-			return err;
1545
-		}
1546
-	}
1547
-
1548
-	return 0;
1549
-}
1550
-
1551
-static int mtk_build_functions(struct mtk_pinctrl *hw)
1552
-{
1553
-	int i, err;
1554
-
1555
-	for (i = 0; i < hw->soc->nfuncs ; i++) {
1556
-		const struct function_desc *func = hw->soc->funcs + i;
1557
-
1558
-		err = pinmux_generic_add_function(hw->pctrl, func->name,
1559
-						  func->group_names,
1560
-						  func->num_group_names,
1561
-						  func->data);
1562
-		if (err < 0) {
1563
-			dev_err(hw->dev, "Failed to register function %s\n",
1564
-				func->name);
1565
-			return err;
1566
-		}
1567
-	}
1568
-
1569
-	return 0;
1570
-}
1571
-
1572
-static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
1573
-			     unsigned int *gpio_n,
1574
-			     struct gpio_chip **gpio_chip)
1575
-{
1576
-	struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
1577
-
1578
-	*gpio_chip = &hw->chip;
1579
-	*gpio_n = eint_n;
1580
-
1581
-	return 0;
1582
-}
1583
-
1584
-static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
1585
-{
1586
-	struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
1587
-	struct gpio_chip *gpio_chip;
1588
-	unsigned int gpio_n;
1589
-	int err;
1590
-
1591
-	err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
1592
-	if (err)
1593
-		return err;
1594
-
1595
-	return mtk_gpio_get(gpio_chip, gpio_n);
1596
-}
1597
-
1598
-static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
1599
-{
1600
-	struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
1601
-	struct gpio_chip *gpio_chip;
1602
-	unsigned int gpio_n;
1603
-	int err;
1604
-
1605
-	err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
1606
-	if (err)
1607
-		return err;
1608
-
1609
-	err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_MODE,
1610
-			       MTK_GPIO_MODE);
1611
-	if (err)
1612
-		return err;
1613
-
1614
-	err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_DIR, MTK_INPUT);
1615
-	if (err)
1616
-		return err;
1617
-
1618
-	err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
1619
-	if (err)
1620
-		return err;
1621
-
1622
-	return 0;
1623
-}
1624
-
1625
-static const struct mtk_eint_xt mtk_eint_xt = {
1626
-	.get_gpio_n = mtk_xt_get_gpio_n,
1627
-	.get_gpio_state = mtk_xt_get_gpio_state,
1628
-	.set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
1629
-};
1630
-
1631
-static int
1632
-mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
1633
-{
1634
-	struct device_node *np = pdev->dev.of_node;
1635
-	struct resource *res;
1636
-
1637
-	if (!IS_ENABLED(CONFIG_EINT_MTK))
1638
-		return 0;
1639
-
1640
-	if (!of_property_read_bool(np, "interrupt-controller"))
1641
-		return -ENODEV;
1642
-
1643
-	hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
1644
-	if (!hw->eint)
1645
-		return -ENOMEM;
1646
-
1647
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
1648
-	if (!res) {
1649
-		dev_err(&pdev->dev, "Unable to get eint resource\n");
1650
-		return -ENODEV;
1651
-	}
1652
-
1653
-	hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
1654
-	if (IS_ERR(hw->eint->base))
1655
-		return PTR_ERR(hw->eint->base);
1656
-
1657
-	hw->eint->irq = irq_of_parse_and_map(np, 0);
1658
-	if (!hw->eint->irq)
1659
-		return -EINVAL;
1660
-
1661
-	hw->eint->dev = &pdev->dev;
1662
-	hw->eint->hw = hw->soc->eint_hw;
1663
-	hw->eint->pctl = hw;
1664
-	hw->eint->gpio_xlate = &mtk_eint_xt;
1665
-
1666
-	return mtk_eint_do_init(hw->eint);
1667
-}
1668
-
1669
-static const struct of_device_id mtk_pinctrl_of_match[] = {
1670
-	{ .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data},
883
+static const struct of_device_id mt7622_pinctrl_of_match[] = {
884
+	{ .compatible = "mediatek,mt7622-pinctrl", },
1671885 	{ }
1672886 };
1673887 
1674
-static int mtk_pinctrl_probe(struct platform_device *pdev)
888
+static int mt7622_pinctrl_probe(struct platform_device *pdev)
1675889 {
1676
-	struct resource *res;
1677
-	struct mtk_pinctrl *hw;
1678
-	const struct of_device_id *of_id =
1679
-		of_match_device(mtk_pinctrl_of_match, &pdev->dev);
1680
-	int err;
1681
-
1682
-	hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
1683
-	if (!hw)
1684
-		return -ENOMEM;
1685
-
1686
-	hw->soc = of_id->data;
1687
-
1688
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1689
-	if (!res) {
1690
-		dev_err(&pdev->dev, "missing IO resource\n");
1691
-		return -ENXIO;
1692
-	}
1693
-
1694
-	hw->dev = &pdev->dev;
1695
-	hw->base = devm_ioremap_resource(&pdev->dev, res);
1696
-	if (IS_ERR(hw->base))
1697
-		return PTR_ERR(hw->base);
1698
-
1699
-	/* Setup pins descriptions per SoC types */
1700
-	mtk_desc.pins = hw->soc->pins;
1701
-	mtk_desc.npins = hw->soc->npins;
1702
-	mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
1703
-	mtk_desc.custom_params = mtk_custom_bindings;
1704
-#ifdef CONFIG_DEBUG_FS
1705
-	mtk_desc.custom_conf_items = mtk_conf_items;
1706
-#endif
1707
-
1708
-	err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
1709
-					     &hw->pctrl);
1710
-	if (err)
1711
-		return err;
1712
-
1713
-	/* Setup groups descriptions per SoC types */
1714
-	err = mtk_build_groups(hw);
1715
-	if (err) {
1716
-		dev_err(&pdev->dev, "Failed to build groups\n");
1717
-		return err;
1718
-	}
1719
-
1720
-	/* Setup functions descriptions per SoC types */
1721
-	err = mtk_build_functions(hw);
1722
-	if (err) {
1723
-		dev_err(&pdev->dev, "Failed to build functions\n");
1724
-		return err;
1725
-	}
1726
-
1727
-	/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
1728
-	 * until all groups and functions are being added one.
1729
-	 */
1730
-	err = pinctrl_enable(hw->pctrl);
1731
-	if (err)
1732
-		return err;
1733
-
1734
-	err = mtk_build_eint(hw, pdev);
1735
-	if (err)
1736
-		dev_warn(&pdev->dev,
1737
-			 "Failed to add EINT, but pinctrl still can work\n");
1738
-
1739
-	/* Build gpiochip should be after pinctrl_enable is done */
1740
-	err = mtk_build_gpiochip(hw, pdev->dev.of_node);
1741
-	if (err) {
1742
-		dev_err(&pdev->dev, "Failed to add gpio_chip\n");
1743
-		return err;
1744
-	}
1745
-
1746
-	platform_set_drvdata(pdev, hw);
1747
-
1748
-	return 0;
890
+	return mtk_moore_pinctrl_probe(pdev, &mt7622_data);
1749891 }
1750892 
1751
-static struct platform_driver mtk_pinctrl_driver = {
893
+static struct platform_driver mt7622_pinctrl_driver = {
1752894 	.driver = {
1753
-		.name = "mtk-pinctrl",
1754
-		.of_match_table = mtk_pinctrl_of_match,
895
+		.name = "mt7622-pinctrl",
896
+		.of_match_table = mt7622_pinctrl_of_match,
1755897 	},
1756
-	.probe = mtk_pinctrl_probe,
898
+	.probe = mt7622_pinctrl_probe,
1757899 };
1758900 
1759
-static int __init mtk_pinctrl_init(void)
901
+static int __init mt7622_pinctrl_init(void)
1760902 {
1761
-	return platform_driver_register(&mtk_pinctrl_driver);
903
+	return platform_driver_register(&mt7622_pinctrl_driver);
1762904 }
1763
-arch_initcall(mtk_pinctrl_init);
905
+arch_initcall(mt7622_pinctrl_init);