.. | .. |
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6 | 6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
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7 | 7 | */ |
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8 | 8 | |
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9 | | -#include <linux/acpi.h> |
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| 9 | +#include <linux/mod_devicetable.h> |
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10 | 10 | #include <linux/module.h> |
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11 | 11 | #include <linux/platform_device.h> |
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12 | | -#include <linux/pm.h> |
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| 12 | + |
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13 | 13 | #include <linux/pinctrl/pinctrl.h> |
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14 | 14 | |
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15 | 15 | #include "pinctrl-intel.h" |
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16 | 16 | |
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17 | 17 | #define DNV_PAD_OWN 0x020 |
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18 | | -#define DNV_HOSTSW_OWN 0x0C0 |
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19 | 18 | #define DNV_PADCFGLOCK 0x090 |
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| 19 | +#define DNV_HOSTSW_OWN 0x0C0 |
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| 20 | +#define DNV_GPI_IS 0x100 |
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20 | 21 | #define DNV_GPI_IE 0x120 |
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21 | 22 | |
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22 | 23 | #define DNV_GPP(n, s, e) \ |
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.. | .. |
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32 | 33 | .padown_offset = DNV_PAD_OWN, \ |
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33 | 34 | .padcfglock_offset = DNV_PADCFGLOCK, \ |
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34 | 35 | .hostown_offset = DNV_HOSTSW_OWN, \ |
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| 36 | + .is_offset = DNV_GPI_IS, \ |
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35 | 37 | .ie_offset = DNV_GPI_IE, \ |
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36 | 38 | .pin_base = (s), \ |
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37 | 39 | .npins = ((e) - (s) + 1), \ |
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.. | .. |
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39 | 41 | .ngpps = ARRAY_SIZE(g), \ |
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40 | 42 | } |
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41 | 43 | |
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| 44 | +/* Denverton */ |
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42 | 45 | static const struct pinctrl_pin_desc dnv_pins[] = { |
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43 | 46 | /* North ALL */ |
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44 | 47 | PINCTRL_PIN(0, "GBE0_SDP0"), |
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.. | .. |
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59 | 62 | PINCTRL_PIN(15, "NCSI_CLK_IN"), |
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60 | 63 | PINCTRL_PIN(16, "NCSI_RXD1"), |
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61 | 64 | PINCTRL_PIN(17, "NCSI_CRS_DV"), |
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62 | | - PINCTRL_PIN(18, "NCSI_ARB_IN"), |
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| 65 | + PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"), |
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63 | 66 | PINCTRL_PIN(19, "NCSI_TX_EN"), |
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64 | 67 | PINCTRL_PIN(20, "NCSI_TXD0"), |
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65 | 68 | PINCTRL_PIN(21, "NCSI_TXD1"), |
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.. | .. |
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68 | 71 | PINCTRL_PIN(24, "GBE0_LED1"), |
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69 | 72 | PINCTRL_PIN(25, "GBE1_LED0"), |
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70 | 73 | PINCTRL_PIN(26, "GBE1_LED1"), |
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71 | | - PINCTRL_PIN(27, "GPIO_0"), |
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| 74 | + PINCTRL_PIN(27, "SPARE_0"), |
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72 | 75 | PINCTRL_PIN(28, "PCIE_CLKREQ0_N"), |
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73 | 76 | PINCTRL_PIN(29, "PCIE_CLKREQ1_N"), |
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74 | 77 | PINCTRL_PIN(30, "PCIE_CLKREQ2_N"), |
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75 | 78 | PINCTRL_PIN(31, "PCIE_CLKREQ3_N"), |
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76 | 79 | PINCTRL_PIN(32, "PCIE_CLKREQ4_N"), |
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77 | | - PINCTRL_PIN(33, "GPIO_1"), |
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78 | | - PINCTRL_PIN(34, "GPIO_2"), |
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| 80 | + PINCTRL_PIN(33, "GBE_MDC"), |
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| 81 | + PINCTRL_PIN(34, "GBE_MDIO"), |
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79 | 82 | PINCTRL_PIN(35, "SVID_ALERT_N"), |
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80 | 83 | PINCTRL_PIN(36, "SVID_DATA"), |
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81 | 84 | PINCTRL_PIN(37, "SVID_CLK"), |
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.. | .. |
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102 | 105 | PINCTRL_PIN(57, "DFX_PORT14"), |
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103 | 106 | PINCTRL_PIN(58, "DFX_PORT15"), |
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104 | 107 | /* South GPP0 */ |
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105 | | - PINCTRL_PIN(59, "GPIO_12"), |
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106 | | - PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"), |
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| 108 | + PINCTRL_PIN(59, "SPI_TPM_CS_N"), |
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| 109 | + PINCTRL_PIN(60, "UART2_CTS"), |
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107 | 110 | PINCTRL_PIN(61, "PCIE_CLKREQ5_N"), |
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108 | 111 | PINCTRL_PIN(62, "PCIE_CLKREQ6_N"), |
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109 | 112 | PINCTRL_PIN(63, "PCIE_CLKREQ7_N"), |
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110 | 113 | PINCTRL_PIN(64, "UART0_RXD"), |
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111 | 114 | PINCTRL_PIN(65, "UART0_TXD"), |
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112 | | - PINCTRL_PIN(66, "SMB5_GBE_CLK"), |
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113 | | - PINCTRL_PIN(67, "SMB5_GBE_DATA"), |
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| 115 | + PINCTRL_PIN(66, "CPU_RESET_N"), |
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| 116 | + PINCTRL_PIN(67, "NMI"), |
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114 | 117 | PINCTRL_PIN(68, "ERROR2_N"), |
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115 | 118 | PINCTRL_PIN(69, "ERROR1_N"), |
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116 | 119 | PINCTRL_PIN(70, "ERROR0_N"), |
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.. | .. |
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129 | 132 | PINCTRL_PIN(83, "USB_OC0_N"), |
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130 | 133 | PINCTRL_PIN(84, "FLEX_CLK_SE0"), |
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131 | 134 | PINCTRL_PIN(85, "FLEX_CLK_SE1"), |
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132 | | - PINCTRL_PIN(86, "GPIO_4"), |
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133 | | - PINCTRL_PIN(87, "GPIO_5"), |
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134 | | - PINCTRL_PIN(88, "GPIO_6"), |
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135 | | - PINCTRL_PIN(89, "GPIO_7"), |
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| 135 | + PINCTRL_PIN(86, "SPARE_4"), |
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| 136 | + PINCTRL_PIN(87, "SMB3_IE0_CLK"), |
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| 137 | + PINCTRL_PIN(88, "SMB3_IE0_DATA"), |
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| 138 | + PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"), |
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136 | 139 | PINCTRL_PIN(90, "SATA0_LED_N"), |
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137 | 140 | PINCTRL_PIN(91, "SATA1_LED_N"), |
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138 | 141 | PINCTRL_PIN(92, "SATA_PDETECT0"), |
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139 | 142 | PINCTRL_PIN(93, "SATA_PDETECT1"), |
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140 | | - PINCTRL_PIN(94, "SATA0_SDOUT"), |
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141 | | - PINCTRL_PIN(95, "SATA1_SDOUT"), |
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| 143 | + PINCTRL_PIN(94, "UART1_RTS"), |
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| 144 | + PINCTRL_PIN(95, "UART1_CTS"), |
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142 | 145 | PINCTRL_PIN(96, "UART1_RXD"), |
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143 | 146 | PINCTRL_PIN(97, "UART1_TXD"), |
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144 | | - PINCTRL_PIN(98, "GPIO_8"), |
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145 | | - PINCTRL_PIN(99, "GPIO_9"), |
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| 147 | + PINCTRL_PIN(98, "SPARE_8"), |
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| 148 | + PINCTRL_PIN(99, "SPARE_9"), |
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146 | 149 | PINCTRL_PIN(100, "TCK"), |
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147 | 150 | PINCTRL_PIN(101, "TRST_N"), |
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148 | 151 | PINCTRL_PIN(102, "TMS"), |
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.. | .. |
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150 | 153 | PINCTRL_PIN(104, "TDO"), |
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151 | 154 | PINCTRL_PIN(105, "CX_PRDY_N"), |
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152 | 155 | PINCTRL_PIN(106, "CX_PREQ_N"), |
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153 | | - PINCTRL_PIN(107, "CTBTRIGINOUT"), |
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154 | | - PINCTRL_PIN(108, "CTBTRIGOUT"), |
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155 | | - PINCTRL_PIN(109, "DFX_SPARE2"), |
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156 | | - PINCTRL_PIN(110, "DFX_SPARE3"), |
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157 | | - PINCTRL_PIN(111, "DFX_SPARE4"), |
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| 156 | + PINCTRL_PIN(107, "TAP1_TCK"), |
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| 157 | + PINCTRL_PIN(108, "TAP1_TRST_N"), |
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| 158 | + PINCTRL_PIN(109, "TAP1_TMS"), |
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| 159 | + PINCTRL_PIN(110, "TAP1_TDI"), |
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| 160 | + PINCTRL_PIN(111, "TAP1_TDO"), |
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158 | 161 | /* South GPP1 */ |
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159 | 162 | PINCTRL_PIN(112, "SUSPWRDNACK"), |
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160 | 163 | PINCTRL_PIN(113, "PMU_SUSCLK"), |
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.. | .. |
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183 | 186 | PINCTRL_PIN(136, "ESPI_CLK"), |
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184 | 187 | PINCTRL_PIN(137, "ESPI_RST_N"), |
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185 | 188 | PINCTRL_PIN(138, "ESPI_ALRT0_N"), |
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186 | | - PINCTRL_PIN(139, "GPIO_10"), |
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187 | | - PINCTRL_PIN(140, "GPIO_11"), |
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| 189 | + PINCTRL_PIN(139, "ESPI_CS1_N"), |
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| 190 | + PINCTRL_PIN(140, "ESPI_ALRT1_N"), |
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188 | 191 | PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"), |
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189 | 192 | PINCTRL_PIN(142, "EMMC_CMD"), |
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190 | 193 | PINCTRL_PIN(143, "EMMC_STROBE"), |
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.. | .. |
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197 | 200 | PINCTRL_PIN(150, "EMMC_D5"), |
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198 | 201 | PINCTRL_PIN(151, "EMMC_D6"), |
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199 | 202 | PINCTRL_PIN(152, "EMMC_D7"), |
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200 | | - PINCTRL_PIN(153, "GPIO_3"), |
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| 203 | + PINCTRL_PIN(153, "SPARE_3"), |
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201 | 204 | }; |
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202 | 205 | |
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203 | 206 | static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 }; |
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.. | .. |
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257 | 260 | .ncommunities = ARRAY_SIZE(dnv_communities), |
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258 | 261 | }; |
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259 | 262 | |
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260 | | -static int dnv_pinctrl_probe(struct platform_device *pdev) |
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261 | | -{ |
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262 | | - return intel_pinctrl_probe(pdev, &dnv_soc_data); |
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263 | | -} |
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264 | | - |
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265 | | -static const struct dev_pm_ops dnv_pinctrl_pm_ops = { |
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266 | | - SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, |
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267 | | - intel_pinctrl_resume) |
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268 | | -}; |
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| 263 | +static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops); |
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269 | 264 | |
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270 | 265 | static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { |
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271 | | - { "INTC3000" }, |
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| 266 | + { "INTC3000", (kernel_ulong_t)&dnv_soc_data }, |
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272 | 267 | { } |
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273 | 268 | }; |
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274 | 269 | MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match); |
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275 | 270 | |
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276 | 271 | static struct platform_driver dnv_pinctrl_driver = { |
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277 | | - .probe = dnv_pinctrl_probe, |
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| 272 | + .probe = intel_pinctrl_probe_by_hid, |
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278 | 273 | .driver = { |
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279 | 274 | .name = "denverton-pinctrl", |
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280 | 275 | .acpi_match_table = dnv_pinctrl_acpi_match, |
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