.. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2016 IBM Corp. |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License as published by |
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6 | | - * the Free Software Foundation; either version 2 of the License, or |
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7 | | - * (at your option) any later version. |
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8 | 4 | */ |
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9 | 5 | |
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10 | 6 | #ifndef PINCTRL_ASPEED |
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.. | .. |
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16 | 12 | #include <linux/pinctrl/pinconf-generic.h> |
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17 | 13 | #include <linux/regmap.h> |
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18 | 14 | |
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19 | | -/* |
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20 | | - * The ASPEED SoCs provide typically more than 200 pins for GPIO and other |
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21 | | - * functions. The SoC function enabled on a pin is determined on a priority |
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22 | | - * basis where a given pin can provide a number of different signal types. |
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23 | | - * |
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24 | | - * The signal active on a pin is described by both a priority level and |
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25 | | - * compound logical expressions involving multiple operators, registers and |
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26 | | - * bits. Some difficulty arises as the pin's function bit masks for each |
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27 | | - * priority level are frequently not the same (i.e. cannot just flip a bit to |
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28 | | - * change from a high to low priority signal), or even in the same register. |
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29 | | - * Further, not all signals can be unmuxed, as some expressions depend on |
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30 | | - * values in the hardware strapping register (which is treated as read-only). |
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31 | | - * |
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32 | | - * SoC Multi-function Pin Expression Examples |
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33 | | - * ------------------------------------------ |
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34 | | - * |
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35 | | - * Here are some sample mux configurations from the AST2400 and AST2500 |
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36 | | - * datasheets to illustrate the corner cases, roughly in order of least to most |
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37 | | - * corner. The signal priorities are in decending order from P0 (highest). |
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38 | | - * |
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39 | | - * D6 is a pin with a single function (beside GPIO); a high priority signal |
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40 | | - * that participates in one function: |
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41 | | - * |
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42 | | - * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other |
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43 | | - * -----+---------+-----------+-----------------------------+-----------+---------------+---------- |
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44 | | - * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0 |
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45 | | - * -----+---------+-----------+-----------------------------+-----------+---------------+---------- |
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46 | | - * |
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47 | | - * C5 is a multi-signal pin (high and low priority signals). Here we touch |
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48 | | - * different registers for the different functions that enable each signal: |
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49 | | - * |
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50 | | - * -----+---------+-----------+-----------------------------+-----------+---------------+---------- |
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51 | | - * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4 |
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52 | | - * -----+---------+-----------+-----------------------------+-----------+---------------+---------- |
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53 | | - * |
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54 | | - * E19 is a single-signal pin with two functions that influence the active |
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55 | | - * signal. In this case both bits have the same meaning - enable a dedicated |
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56 | | - * LPC reset pin. However it's not always the case that the bits in the |
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57 | | - * OR-relationship have the same meaning. |
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58 | | - * |
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59 | | - * -----+---------+-----------+-----------------------------+-----------+---------------+---------- |
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60 | | - * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4 |
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61 | | - * -----+---------+-----------+-----------------------------+-----------+---------------+---------- |
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62 | | - * |
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63 | | - * For example, pin B19 has a low-priority signal that's enabled by two |
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64 | | - * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI |
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65 | | - * bit in the STRAP register. The ACPI bit configures signals on pins in |
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66 | | - * addition to B19. Both of the low priority functions as well as the high |
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67 | | - * priority function must be disabled for GPIOF1 to be used. |
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68 | | - * |
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69 | | - * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other |
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70 | | - * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- |
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71 | | - * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1 |
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72 | | - * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- |
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73 | | - * |
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74 | | - * For pin E18, the SoC ANDs the expected state of three bits to determine the |
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75 | | - * pin's active signal: |
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76 | | - * |
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77 | | - * * SCU3C[3]: Enable external SOC reset function |
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78 | | - * * SCU80[15]: Enable SPICS1# or EXTRST# function pin |
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79 | | - * * SCU90[31]: Select SPI interface CS# output |
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80 | | - * |
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81 | | - * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- |
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82 | | - * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7 |
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83 | | - * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- |
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84 | | - * |
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85 | | - * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for |
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86 | | - * selecting the signals on pin E18) |
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87 | | - * |
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88 | | - * Pin T5 is a multi-signal pin with a more complex configuration: |
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89 | | - * |
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90 | | - * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other |
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91 | | - * -----+---------+-----------+------------------------------+-----------+---------------+---------- |
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92 | | - * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1 |
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93 | | - * -----+---------+-----------+------------------------------+-----------+---------------+---------- |
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94 | | - * |
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95 | | - * The high priority signal configuration is best thought of in terms of its |
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96 | | - * exploded form, with reference to the SCU90[5:4] bits: |
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97 | | - * |
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98 | | - * * SCU90[5:4]=00: disable |
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99 | | - * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode. |
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100 | | - * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode. |
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101 | | - * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode. |
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102 | | - * |
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103 | | - * Re-writing: |
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104 | | - * |
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105 | | - * -----+---------+-----------+------------------------------+-----------+---------------+---------- |
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106 | | - * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1 |
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107 | | - * | (SCU90[5:4]=2 & SCU84[17]=1) |
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108 | | - * | (SCU90[5:4]=3 & SCU84[17]=1) |
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109 | | - * -----+---------+-----------+------------------------------+-----------+---------------+---------- |
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110 | | - * |
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111 | | - * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE |
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112 | | - * function pin", where the signal itself is determined by whether SCU94[5:4] |
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113 | | - * is disabled or in one of the 18, 24 or 30bit video modes. |
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114 | | - * |
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115 | | - * Other video-input-related pins require an explicit state in SCU90[5:4], e.g. |
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116 | | - * W1 and U5: |
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117 | | - * |
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118 | | - * -----+---------+-----------+------------------------------+-----------+---------------+---------- |
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119 | | - * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6 |
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120 | | - * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7 |
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121 | | - * -----+---------+-----------+------------------------------+-----------+---------------+---------- |
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122 | | - * |
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123 | | - * The examples of T5 and W1 are particularly fertile, as they also demonstrate |
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124 | | - * that despite operating as part of the video input bus each signal needs to |
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125 | | - * be enabled individually via it's own SCU84 (in the cases of T5 and W1) |
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126 | | - * register bit. This is a little crazy if the bus doesn't have optional |
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127 | | - * signals, but is used to decent effect with some of the UARTs where not all |
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128 | | - * signals are required. However, this isn't done consistently - UART1 is |
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129 | | - * enabled on a per-pin basis, and by contrast, all signals for UART6 are |
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130 | | - * enabled by a single bit. |
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131 | | - * |
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132 | | - * Further, the high and low priority signals listed in the table above share |
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133 | | - * a configuration bit. The VPI signals should operate in concert in a single |
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134 | | - * function, but the UART signals should retain the ability to be configured |
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135 | | - * independently. This pushes the implementation down the path of tagging a |
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136 | | - * signal's expressions with the function they participate in, rather than |
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137 | | - * defining masks affecting multiple signals per function. The latter approach |
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138 | | - * fails in this instance where applying the configuration for the UART pin of |
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139 | | - * interest will stomp on the state of other UART signals when disabling the |
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140 | | - * VPI functions on the current pin. |
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141 | | - * |
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142 | | - * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other |
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143 | | - * -----+------------+-----------+---------------------------+-----------+---------------+------------ |
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144 | | - * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK |
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145 | | - * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL |
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146 | | - * -----+------------+-----------+---------------------------+-----------+---------------+------------ |
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147 | | - * |
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148 | | - * A12 demonstrates that the "Other" signal isn't always GPIO - in this case |
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149 | | - * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO |
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150 | | - * should be treated like any other signal type with full function expression |
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151 | | - * requirements, and not assumed to be the default case. Separately, GPIOT0 and |
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152 | | - * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all |
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153 | | - * pins in the function's group to disable the higher-priority signals such |
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154 | | - * that the signal for the function of interest is correctly enabled. |
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155 | | - * |
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156 | | - * Finally, three priority levels aren't always enough; the AST2500 brings with |
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157 | | - * it 18 pins of five priority levels, however the 18 pins only use three of |
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158 | | - * the five priority levels. |
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159 | | - * |
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160 | | - * Ultimately the requirement to control pins in the examples above drive the |
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161 | | - * design: |
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162 | | - * |
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163 | | - * * Pins provide signals according to functions activated in the mux |
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164 | | - * configuration |
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165 | | - * |
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166 | | - * * Pins provide up to five signal types in a priority order |
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167 | | - * |
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168 | | - * * For priorities levels defined on a pin, each priority provides one signal |
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169 | | - * |
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170 | | - * * Enabling lower priority signals requires higher priority signals be |
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171 | | - * disabled |
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172 | | - * |
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173 | | - * * A function represents a set of signals; functions are distinct if their |
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174 | | - * sets of signals are not equal |
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175 | | - * |
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176 | | - * * Signals participate in one or more functions |
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177 | | - * |
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178 | | - * * A function is described by an expression of one or more signal |
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179 | | - * descriptors, which compare bit values in a register |
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180 | | - * |
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181 | | - * * A signal expression is the smallest set of signal descriptors whose |
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182 | | - * comparisons must evaluate 'true' for a signal to be enabled on a pin. |
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183 | | - * |
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184 | | - * * A function's signal is active on a pin if evaluating all signal |
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185 | | - * descriptors in the pin's signal expression for the function yields a 'true' |
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186 | | - * result |
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187 | | - * |
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188 | | - * * A signal at a given priority on a given pin is active if any of the |
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189 | | - * functions in which the signal participates are active, and no higher |
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190 | | - * priority signal on the pin is active |
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191 | | - * |
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192 | | - * * GPIO is configured per-pin |
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193 | | - * |
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194 | | - * And so: |
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195 | | - * |
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196 | | - * * To disable a signal, any function(s) activating the signal must be |
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197 | | - * disabled |
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198 | | - * |
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199 | | - * * Each pin must know the signal expressions of functions in which it |
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200 | | - * participates, for the purpose of enabling the Other function. This is done |
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201 | | - * by deactivating all functions that activate higher priority signals on the |
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202 | | - * pin. |
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203 | | - * |
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204 | | - * As a concrete example: |
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205 | | - * |
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206 | | - * * T5 provides three signals types: VPIDE, NDCD1 and GPIO |
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207 | | - * |
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208 | | - * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30 |
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209 | | - * |
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210 | | - * * The NDCD1 signal participates in just its own NDCD1 function |
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211 | | - * |
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212 | | - * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least |
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213 | | - * prioritised |
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214 | | - * |
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215 | | - * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24 |
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216 | | - * and VPI30 functions all be disabled |
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217 | | - * |
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218 | | - * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled |
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219 | | - * to provide GPIOL6 |
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220 | | - * |
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221 | | - * Considerations |
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222 | | - * -------------- |
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223 | | - * |
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224 | | - * If pinctrl allows us to allocate a pin we can configure a function without |
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225 | | - * concern for the function of already allocated pins, if pin groups are |
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226 | | - * created with respect to the SoC functions in which they participate. This is |
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227 | | - * intuitive, but it did not feel obvious from the bit/pin relationships. |
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228 | | - * |
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229 | | - * Conversely, failing to allocate all pins in a group indicates some bits (as |
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230 | | - * well as pins) required for the group's configuration will already be in use, |
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231 | | - * likely in a way that's inconsistent with the requirements of the failed |
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232 | | - * group. |
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233 | | - */ |
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234 | | - |
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235 | | -#define ASPEED_IP_SCU 0 |
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236 | | -#define ASPEED_IP_GFX 1 |
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237 | | -#define ASPEED_IP_LPC 2 |
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238 | | -#define ASPEED_NR_PINMUX_IPS 3 |
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239 | | - |
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240 | | -/* |
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241 | | - * The "Multi-function Pins Mapping and Control" table in the SoC datasheet |
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242 | | - * references registers by the device/offset mnemonic. The register macros |
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243 | | - * below are named the same way to ease transcription and verification (as |
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244 | | - * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions |
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245 | | - * reference registers beyond those dedicated to pinmux, such as the system |
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246 | | - * reset control and MAC clock configuration registers. The AST2500 goes a step |
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247 | | - * further and references registers in the graphics IP block, but that isn't |
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248 | | - * handled yet. |
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249 | | - */ |
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250 | | -#define SCU2C 0x2C /* Misc. Control Register */ |
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251 | | -#define SCU3C 0x3C /* System Reset Control/Status Register */ |
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252 | | -#define SCU48 0x48 /* MAC Interface Clock Delay Setting */ |
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253 | | -#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ |
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254 | | -#define HW_REVISION_ID 0x7C /* Silicon revision ID register */ |
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255 | | -#define SCU80 0x80 /* Multi-function Pin Control #1 */ |
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256 | | -#define SCU84 0x84 /* Multi-function Pin Control #2 */ |
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257 | | -#define SCU88 0x88 /* Multi-function Pin Control #3 */ |
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258 | | -#define SCU8C 0x8C /* Multi-function Pin Control #4 */ |
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259 | | -#define SCU90 0x90 /* Multi-function Pin Control #5 */ |
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260 | | -#define SCU94 0x94 /* Multi-function Pin Control #6 */ |
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261 | | -#define SCUA0 0xA0 /* Multi-function Pin Control #7 */ |
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262 | | -#define SCUA4 0xA4 /* Multi-function Pin Control #8 */ |
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263 | | -#define SCUA8 0xA8 /* Multi-function Pin Control #9 */ |
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264 | | -#define SCUAC 0xAC /* Multi-function Pin Control #10 */ |
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265 | | -#define HW_STRAP2 0xD0 /* Strapping */ |
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266 | | - |
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267 | | - /** |
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268 | | - * A signal descriptor, which describes the register, bits and the |
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269 | | - * enable/disable values that should be compared or written. |
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270 | | - * |
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271 | | - * @ip: The IP block identifier, used as an index into the regmap array in |
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272 | | - * struct aspeed_pinctrl_data |
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273 | | - * @reg: The register offset with respect to the base address of the IP block |
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274 | | - * @mask: The mask to apply to the register. The lowest set bit of the mask is |
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275 | | - * used to derive the shift value. |
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276 | | - * @enable: The value that enables the function. Value should be in the LSBs, |
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277 | | - * not at the position of the mask. |
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278 | | - * @disable: The value that disables the function. Value should be in the |
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279 | | - * LSBs, not at the position of the mask. |
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280 | | - */ |
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281 | | -struct aspeed_sig_desc { |
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282 | | - unsigned int ip; |
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283 | | - unsigned int reg; |
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284 | | - u32 mask; |
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285 | | - u32 enable; |
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286 | | - u32 disable; |
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287 | | -}; |
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288 | | - |
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289 | | -/** |
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290 | | - * Describes a signal expression. The expression is evaluated by ANDing the |
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291 | | - * evaluation of the descriptors. |
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292 | | - * |
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293 | | - * @signal: The signal name for the priority level on the pin. If the signal |
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294 | | - * type is GPIO, then the signal name must begin with the string |
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295 | | - * "GPIO", e.g. GPIOA0, GPIOT4 etc. |
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296 | | - * @function: The name of the function the signal participates in for the |
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297 | | - * associated expression |
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298 | | - * @ndescs: The number of signal descriptors in the expression |
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299 | | - * @descs: Pointer to an array of signal descriptors that comprise the |
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300 | | - * function expression |
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301 | | - */ |
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302 | | -struct aspeed_sig_expr { |
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303 | | - const char *signal; |
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304 | | - const char *function; |
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305 | | - int ndescs; |
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306 | | - const struct aspeed_sig_desc *descs; |
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307 | | -}; |
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308 | | - |
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309 | | -/** |
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310 | | - * A struct capturing the list of expressions enabling signals at each priority |
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311 | | - * for a given pin. The signal configuration for a priority level is evaluated |
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312 | | - * by ORing the evaluation of the signal expressions in the respective |
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313 | | - * priority's list. |
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314 | | - * |
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315 | | - * @name: A name for the pin |
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316 | | - * @prios: A pointer to an array of expression list pointers |
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317 | | - * |
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318 | | - */ |
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319 | | -struct aspeed_pin_desc { |
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320 | | - const char *name; |
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321 | | - const struct aspeed_sig_expr ***prios; |
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322 | | -}; |
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323 | | - |
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324 | | -/* Macro hell */ |
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325 | | - |
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326 | | -#define SIG_DESC_IP_BIT(ip, reg, idx, val) \ |
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327 | | - { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } |
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328 | | - |
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329 | | -/** |
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330 | | - * Short-hand macro for describing an SCU descriptor enabled by the state of |
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331 | | - * one bit. The disable value is derived. |
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332 | | - * |
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333 | | - * @reg: The signal's associated register, offset from base |
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334 | | - * @idx: The signal's bit index in the register |
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335 | | - * @val: The value (0 or 1) that enables the function |
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336 | | - */ |
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337 | | -#define SIG_DESC_BIT(reg, idx, val) \ |
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338 | | - SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) |
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339 | | - |
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340 | | -#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) |
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341 | | - |
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342 | | -/** |
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343 | | - * A further short-hand macro expanding to an SCU descriptor enabled by a set |
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344 | | - * bit. |
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345 | | - * |
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346 | | - * @reg: The register, offset from base |
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347 | | - * @idx: The bit index in the register |
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348 | | - */ |
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349 | | -#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) |
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350 | | - |
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351 | | -#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func |
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352 | | -#define SIG_DESC_LIST_DECL(sig, func, ...) \ |
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353 | | - static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \ |
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354 | | - { __VA_ARGS__ } |
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355 | | - |
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356 | | -#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func |
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357 | | -#define SIG_EXPR_DECL_(sig, func) \ |
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358 | | - static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \ |
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359 | | - { \ |
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360 | | - .signal = #sig, \ |
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361 | | - .function = #func, \ |
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362 | | - .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \ |
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363 | | - .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \ |
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364 | | - } |
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365 | | - |
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366 | | -/** |
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367 | | - * Declare a signal expression. |
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368 | | - * |
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369 | | - * @sig: A macro symbol name for the signal (is subjected to stringification |
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370 | | - * and token pasting) |
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371 | | - * @func: The function in which the signal is participating |
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372 | | - * @...: Signal descriptors that define the signal expression |
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373 | | - * |
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374 | | - * For example, the following declares the ROMD8 signal for the ROM16 function: |
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375 | | - * |
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376 | | - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); |
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377 | | - * |
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378 | | - * And with multiple signal descriptors: |
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379 | | - * |
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380 | | - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), |
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381 | | - * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); |
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382 | | - */ |
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383 | | -#define SIG_EXPR_DECL(sig, func, ...) \ |
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384 | | - SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ |
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385 | | - SIG_EXPR_DECL_(sig, func) |
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386 | | - |
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387 | | -/** |
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388 | | - * Declare a pointer to a signal expression |
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389 | | - * |
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390 | | - * @sig: The macro symbol name for the signal (subjected to token pasting) |
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391 | | - * @func: The macro symbol name for the function (subjected to token pasting) |
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392 | | - */ |
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393 | | -#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func)) |
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394 | | - |
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395 | | -#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig |
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396 | | - |
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397 | | -/** |
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398 | | - * Declare a signal expression list for reference in a struct aspeed_pin_prio. |
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399 | | - * |
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400 | | - * @sig: A macro symbol name for the signal (is subjected to token pasting) |
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401 | | - * @...: Signal expression structure pointers (use SIG_EXPR_PTR()) |
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402 | | - * |
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403 | | - * For example, the 16-bit ROM bus can be enabled by one of two possible signal |
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404 | | - * expressions: |
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405 | | - * |
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406 | | - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); |
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407 | | - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), |
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408 | | - * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); |
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409 | | - * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), |
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410 | | - * SIG_EXPR_PTR(ROMD8, ROM16S)); |
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411 | | - */ |
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412 | | -#define SIG_EXPR_LIST_DECL(sig, ...) \ |
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413 | | - static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \ |
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414 | | - { __VA_ARGS__, NULL } |
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415 | | - |
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416 | | -/** |
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417 | | - * A short-hand macro for declaring a function expression and an expression |
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418 | | - * list with a single function. |
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419 | | - * |
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420 | | - * @func: A macro symbol name for the function (is subjected to token pasting) |
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421 | | - * @...: Function descriptors that define the function expression |
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422 | | - * |
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423 | | - * For example, signal NCTS6 participates in its own function with one group: |
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424 | | - * |
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425 | | - * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); |
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426 | | - */ |
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427 | | -#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \ |
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428 | | - SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ |
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429 | | - SIG_EXPR_DECL_(sig, func); \ |
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430 | | - SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func)) |
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431 | | - |
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432 | | -#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \ |
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433 | | - SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1)) |
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434 | | - |
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435 | | -#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0]) |
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436 | | - |
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437 | | -#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin |
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438 | | -#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) |
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439 | | -#define PIN_SYM(pin) pin_ ## pin |
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440 | | - |
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441 | | -#define MS_PIN_DECL_(pin, ...) \ |
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442 | | - static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \ |
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443 | | - { __VA_ARGS__, NULL }; \ |
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444 | | - static const struct aspeed_pin_desc PIN_SYM(pin) = \ |
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445 | | - { #pin, PIN_EXPRS_PTR(pin) } |
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446 | | - |
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447 | | -/** |
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448 | | - * Declare a multi-signal pin |
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449 | | - * |
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450 | | - * @pin: The pin number |
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451 | | - * @other: Macro name for "other" functionality (subjected to stringification) |
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452 | | - * @high: Macro name for the highest priority signal functions |
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453 | | - * @low: Macro name for the low signal functions |
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454 | | - * |
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455 | | - * For example: |
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456 | | - * |
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457 | | - * #define A8 56 |
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458 | | - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); |
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459 | | - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), |
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460 | | - * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); |
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461 | | - * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), |
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462 | | - * SIG_EXPR_PTR(ROMD8, ROM16S)); |
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463 | | - * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); |
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464 | | - * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); |
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465 | | - */ |
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466 | | -#define MS_PIN_DECL(pin, other, high, low) \ |
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467 | | - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ |
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468 | | - MS_PIN_DECL_(pin, \ |
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469 | | - SIG_EXPR_LIST_PTR(high), \ |
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470 | | - SIG_EXPR_LIST_PTR(low), \ |
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471 | | - SIG_EXPR_LIST_PTR(other)) |
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472 | | - |
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473 | | -#define PIN_GROUP_SYM(func) pins_ ## func |
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474 | | -#define FUNC_GROUP_SYM(func) groups_ ## func |
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475 | | -#define FUNC_GROUP_DECL(func, ...) \ |
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476 | | - static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \ |
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477 | | - static const char *FUNC_GROUP_SYM(func)[] = { #func } |
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478 | | - |
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479 | | -/** |
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480 | | - * Declare a single signal pin |
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481 | | - * |
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482 | | - * @pin: The pin number |
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483 | | - * @other: Macro name for "other" functionality (subjected to stringification) |
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484 | | - * @sig: Macro name for the signal (subjected to stringification) |
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485 | | - * |
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486 | | - * For example: |
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487 | | - * |
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488 | | - * #define E3 80 |
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489 | | - * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); |
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490 | | - * SS_PIN_DECL(E3, GPIOK0, SCL5); |
---|
491 | | - */ |
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492 | | -#define SS_PIN_DECL(pin, other, sig) \ |
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493 | | - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ |
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494 | | - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)) |
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495 | | - |
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496 | | -/** |
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497 | | - * Single signal, single function pin declaration |
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498 | | - * |
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499 | | - * @pin: The pin number |
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500 | | - * @other: Macro name for "other" functionality (subjected to stringification) |
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501 | | - * @sig: Macro name for the signal (subjected to stringification) |
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502 | | - * @...: Signal descriptors that define the function expression |
---|
503 | | - * |
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504 | | - * For example: |
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505 | | - * |
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506 | | - * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); |
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507 | | - */ |
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508 | | -#define SSSF_PIN_DECL(pin, other, sig, ...) \ |
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509 | | - SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \ |
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510 | | - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ |
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511 | | - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \ |
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512 | | - FUNC_GROUP_DECL(sig, pin) |
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513 | | - |
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514 | | -#define GPIO_PIN_DECL(pin, gpio) \ |
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515 | | - SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \ |
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516 | | - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) |
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| 15 | +#include "pinmux-aspeed.h" |
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517 | 16 | |
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518 | 17 | /** |
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519 | 18 | * @param The pinconf parameter type |
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.. | .. |
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525 | 24 | enum pin_config_param param; |
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526 | 25 | unsigned int pins[2]; |
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527 | 26 | unsigned int reg; |
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528 | | - u8 bit; |
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529 | | - u8 value; |
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530 | | -}; |
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531 | | - |
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532 | | -struct aspeed_pinctrl_data { |
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533 | | - struct regmap *maps[ASPEED_NR_PINMUX_IPS]; |
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534 | | - |
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535 | | - const struct pinctrl_pin_desc *pins; |
---|
536 | | - const unsigned int npins; |
---|
537 | | - |
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538 | | - const struct aspeed_pin_group *groups; |
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539 | | - const unsigned int ngroups; |
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540 | | - |
---|
541 | | - const struct aspeed_pin_function *functions; |
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542 | | - const unsigned int nfunctions; |
---|
543 | | - |
---|
544 | | - const struct aspeed_pin_config *configs; |
---|
545 | | - const unsigned int nconfigs; |
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| 27 | + u32 mask; |
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546 | 28 | }; |
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547 | 29 | |
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548 | 30 | #define ASPEED_PINCTRL_PIN(name_) \ |
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.. | .. |
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552 | 34 | .drv_data = (void *) &(PIN_SYM(name_)) \ |
---|
553 | 35 | } |
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554 | 36 | |
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555 | | -struct aspeed_pin_group { |
---|
556 | | - const char *name; |
---|
557 | | - const unsigned int *pins; |
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| 37 | +#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \ |
---|
| 38 | + .param = param_, \ |
---|
| 39 | + .pins = {pin0_, pin1_}, \ |
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| 40 | + .reg = reg_, \ |
---|
| 41 | + .mask = BIT_MASK(bit_) \ |
---|
| 42 | +} |
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| 43 | + |
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| 44 | +#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \ |
---|
| 45 | + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \ |
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| 46 | + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) |
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| 47 | + |
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| 48 | +#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \ |
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| 49 | + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \ |
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| 50 | + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) |
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| 51 | +/* |
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| 52 | + * Aspeed pin configuration description. |
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| 53 | + * |
---|
| 54 | + * @param: pinconf configuration parameter |
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| 55 | + * @arg: The supported argument for @param, or -1 if any value is supported |
---|
| 56 | + * @val: The register value to write to configure @arg for @param |
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| 57 | + * @mask: The bitfield mask for @val |
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| 58 | + * |
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| 59 | + * The map is to be used in conjunction with the configuration array supplied |
---|
| 60 | + * by the driver implementation. |
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| 61 | + */ |
---|
| 62 | +struct aspeed_pin_config_map { |
---|
| 63 | + enum pin_config_param param; |
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| 64 | + s32 arg; |
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| 65 | + u32 val; |
---|
| 66 | + u32 mask; |
---|
| 67 | +}; |
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| 68 | + |
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| 69 | +struct aspeed_pinctrl_data { |
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| 70 | + struct regmap *scu; |
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| 71 | + |
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| 72 | + const struct pinctrl_pin_desc *pins; |
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558 | 73 | const unsigned int npins; |
---|
| 74 | + |
---|
| 75 | + const struct aspeed_pin_config *configs; |
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| 76 | + const unsigned int nconfigs; |
---|
| 77 | + |
---|
| 78 | + struct aspeed_pinmux_data pinmux; |
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| 79 | + |
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| 80 | + const struct aspeed_pin_config_map *confmaps; |
---|
| 81 | + const unsigned int nconfmaps; |
---|
559 | 82 | }; |
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560 | 83 | |
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561 | | -#define ASPEED_PINCTRL_GROUP(name_) { \ |
---|
562 | | - .name = #name_, \ |
---|
563 | | - .pins = &(PIN_GROUP_SYM(name_))[0], \ |
---|
564 | | - .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \ |
---|
565 | | -} |
---|
566 | | - |
---|
567 | | -struct aspeed_pin_function { |
---|
568 | | - const char *name; |
---|
569 | | - const char *const *groups; |
---|
570 | | - unsigned int ngroups; |
---|
571 | | -}; |
---|
572 | | - |
---|
573 | | -#define ASPEED_PINCTRL_FUNC(name_, ...) { \ |
---|
574 | | - .name = #name_, \ |
---|
575 | | - .groups = &FUNC_GROUP_SYM(name_)[0], \ |
---|
576 | | - .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \ |
---|
577 | | -} |
---|
578 | | - |
---|
| 84 | +/* Aspeed pinctrl helpers */ |
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579 | 85 | int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev); |
---|
580 | 86 | const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
---|
581 | 87 | unsigned int group); |
---|