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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/pinctrl/aspeed/pinctrl-aspeed.h
....@@ -1,10 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (C) 2016 IBM Corp.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
84  */
95 
106 #ifndef PINCTRL_ASPEED
....@@ -16,504 +12,7 @@
1612 #include <linux/pinctrl/pinconf-generic.h>
1713 #include <linux/regmap.h>
1814 
19
-/*
20
- * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
21
- * functions. The SoC function enabled on a pin is determined on a priority
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- * basis where a given pin can provide a number of different signal types.
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- *
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- * The signal active on a pin is described by both a priority level and
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- * compound logical expressions involving multiple operators, registers and
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- * bits. Some difficulty arises as the pin's function bit masks for each
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- * priority level are frequently not the same (i.e. cannot just flip a bit to
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- * change from a high to low priority signal), or even in the same register.
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- * Further, not all signals can be unmuxed, as some expressions depend on
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- * values in the hardware strapping register (which is treated as read-only).
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- *
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- * SoC Multi-function Pin Expression Examples
33
- * ------------------------------------------
34
- *
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- * Here are some sample mux configurations from the AST2400 and AST2500
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- * datasheets to illustrate the corner cases, roughly in order of least to most
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- * corner. The signal priorities are in decending order from P0 (highest).
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- *
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- * D6 is a pin with a single function (beside GPIO); a high priority signal
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- * that participates in one function:
41
- *
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- * Ball | Default | P0 Signal | P0 Expression               | P1 Signal | P1 Expression | Other
43
- * -----+---------+-----------+-----------------------------+-----------+---------------+----------
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- *  D6    GPIOA0    MAC1LINK    SCU80[0]=1                                                GPIOA0
45
- * -----+---------+-----------+-----------------------------+-----------+---------------+----------
46
- *
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- * C5 is a multi-signal pin (high and low priority signals). Here we touch
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- * different registers for the different functions that enable each signal:
49
- *
50
- * -----+---------+-----------+-----------------------------+-----------+---------------+----------
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- *  C5    GPIOA4    SCL9        SCU90[22]=1                   TIMER5      SCU80[4]=1      GPIOA4
52
- * -----+---------+-----------+-----------------------------+-----------+---------------+----------
53
- *
54
- * E19 is a single-signal pin with two functions that influence the active
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- * signal. In this case both bits have the same meaning - enable a dedicated
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- * LPC reset pin. However it's not always the case that the bits in the
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- * OR-relationship have the same meaning.
58
- *
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- * -----+---------+-----------+-----------------------------+-----------+---------------+----------
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- *  E19   GPIOB4    LPCRST#     SCU80[12]=1 | Strap[14]=1                                 GPIOB4
61
- * -----+---------+-----------+-----------------------------+-----------+---------------+----------
62
- *
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- * For example, pin B19 has a low-priority signal that's enabled by two
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- * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
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- * bit in the STRAP register. The ACPI bit configures signals on pins in
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- * addition to B19. Both of the low priority functions as well as the high
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- * priority function must be disabled for GPIOF1 to be used.
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- *
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- * Ball | Default | P0 Signal | P0 Expression                           | P1 Signal | P1 Expression                          | Other
70
- * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
71
- *  B19   GPIOF1    NDCD4       SCU80[25]=1                               SIOPBI#     SCUA4[12]=1 | Strap[19]=0                GPIOF1
72
- * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
73
- *
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- * For pin E18, the SoC ANDs the expected state of three bits to determine the
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- * pin's active signal:
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- *
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- * * SCU3C[3]: Enable external SOC reset function
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- * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
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- * * SCU90[31]: Select SPI interface CS# output
80
- *
81
- * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
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- *  E18   GPIOB7    EXTRST#     SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0    SPICS1#     SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1   GPIOB7
83
- * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
84
- *
85
- * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
86
- * selecting the signals on pin E18)
87
- *
88
- * Pin T5 is a multi-signal pin with a more complex configuration:
89
- *
90
- * Ball | Default | P0 Signal | P0 Expression                | P1 Signal | P1 Expression | Other
91
- * -----+---------+-----------+------------------------------+-----------+---------------+----------
92
- *  T5    GPIOL1    VPIDE       SCU90[5:4]!=0 & SCU84[17]=1    NDCD1       SCU84[17]=1     GPIOL1
93
- * -----+---------+-----------+------------------------------+-----------+---------------+----------
94
- *
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- * The high priority signal configuration is best thought of in terms of its
96
- * exploded form, with reference to the SCU90[5:4] bits:
97
- *
98
- * * SCU90[5:4]=00: disable
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- * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
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- * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
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- * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
102
- *
103
- * Re-writing:
104
- *
105
- * -----+---------+-----------+------------------------------+-----------+---------------+----------
106
- *  T5    GPIOL1    VPIDE      (SCU90[5:4]=1 & SCU84[17]=1)    NDCD1       SCU84[17]=1     GPIOL1
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- *                             | (SCU90[5:4]=2 & SCU84[17]=1)
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- *                             | (SCU90[5:4]=3 & SCU84[17]=1)
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- * -----+---------+-----------+------------------------------+-----------+---------------+----------
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- *
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- * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
112
- * function pin", where the signal itself is determined by whether SCU94[5:4]
113
- * is disabled or in one of the 18, 24 or 30bit video modes.
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- *
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- * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
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- * W1 and U5:
117
- *
118
- * -----+---------+-----------+------------------------------+-----------+---------------+----------
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- *  W1    GPIOL6    VPIB0       SCU90[5:4]=3 & SCU84[22]=1     TXD1        SCU84[22]=1     GPIOL6
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- *  U5    GPIOL7    VPIB1       SCU90[5:4]=3 & SCU84[23]=1     RXD1        SCU84[23]=1     GPIOL7
121
- * -----+---------+-----------+------------------------------+-----------+---------------+----------
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- *
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- * The examples of T5 and W1 are particularly fertile, as they also demonstrate
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- * that despite operating as part of the video input bus each signal needs to
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- * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
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- * register bit. This is a little crazy if the bus doesn't have optional
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- * signals, but is used to decent effect with some of the UARTs where not all
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- * signals are required. However, this isn't done consistently - UART1 is
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- * enabled on a per-pin basis, and by contrast, all signals for UART6 are
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- * enabled by a single bit.
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- *
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- * Further, the high and low priority signals listed in the table above share
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- * a configuration bit. The VPI signals should operate in concert in a single
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- * function, but the UART signals should retain the ability to be configured
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- * independently. This pushes the implementation down the path of tagging a
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- * signal's expressions with the function they participate in, rather than
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- * defining masks affecting multiple signals per function. The latter approach
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- * fails in this instance where applying the configuration for the UART pin of
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- * interest will stomp on the state of other UART signals when disabling the
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- * VPI functions on the current pin.
141
- *
142
- * Ball |  Default   | P0 Signal | P0 Expression             | P1 Signal | P1 Expression | Other
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- * -----+------------+-----------+---------------------------+-----------+---------------+------------
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- *  A12   RGMII1TXCK   GPIOT0      SCUA0[0]=1                  RMII1TXEN   Strap[6]=0      RGMII1TXCK
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- *  B12   RGMII1TXCTL  GPIOT1      SCUA0[1]=1                  –           Strap[6]=0      RGMII1TXCTL
146
- * -----+------------+-----------+---------------------------+-----------+---------------+------------
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- *
148
- * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
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- * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
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- * should be treated like any other signal type with full function expression
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- * requirements, and not assumed to be the default case. Separately, GPIOT0 and
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- * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
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- * pins in the function's group to disable the higher-priority signals such
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- * that the signal for the function of interest is correctly enabled.
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- *
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- * Finally, three priority levels aren't always enough; the AST2500 brings with
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- * it 18 pins of five priority levels, however the 18 pins only use three of
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- * the five priority levels.
159
- *
160
- * Ultimately the requirement to control pins in the examples above drive the
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- * design:
162
- *
163
- * * Pins provide signals according to functions activated in the mux
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- *   configuration
165
- *
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- * * Pins provide up to five signal types in a priority order
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- *
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- * * For priorities levels defined on a pin, each priority provides one signal
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- *
170
- * * Enabling lower priority signals requires higher priority signals be
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- *   disabled
172
- *
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- * * A function represents a set of signals; functions are distinct if their
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- *   sets of signals are not equal
175
- *
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- * * Signals participate in one or more functions
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- *
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- * * A function is described by an expression of one or more signal
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- *   descriptors, which compare bit values in a register
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- *
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- * * A signal expression is the smallest set of signal descriptors whose
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- *   comparisons must evaluate 'true' for a signal to be enabled on a pin.
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- *
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- * * A function's signal is active on a pin if evaluating all signal
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- *   descriptors in the pin's signal expression for the function yields a 'true'
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- *   result
187
- *
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- * * A signal at a given priority on a given pin is active if any of the
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- *   functions in which the signal participates are active, and no higher
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- *   priority signal on the pin is active
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- *
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- * * GPIO is configured per-pin
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- *
194
- * And so:
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- *
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- * * To disable a signal, any function(s) activating the signal must be
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- *   disabled
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- *
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- * * Each pin must know the signal expressions of functions in which it
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- *   participates, for the purpose of enabling the Other function. This is done
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- *   by deactivating all functions that activate higher priority signals on the
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- *   pin.
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- *
204
- * As a concrete example:
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- *
206
- * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
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- *
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- * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
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- *
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- * * The NDCD1 signal participates in just its own NDCD1 function
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- *
212
- * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
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- *   prioritised
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- *
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- * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
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- *   and VPI30 functions all be disabled
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- *
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- * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
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- *   to provide GPIOL6
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- *
221
- * Considerations
222
- * --------------
223
- *
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- * If pinctrl allows us to allocate a pin we can configure a function without
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- * concern for the function of already allocated pins, if pin groups are
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- * created with respect to the SoC functions in which they participate. This is
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- * intuitive, but it did not feel obvious from the bit/pin relationships.
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- *
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- * Conversely, failing to allocate all pins in a group indicates some bits (as
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- * well as pins) required for the group's configuration will already be in use,
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- * likely in a way that's inconsistent with the requirements of the failed
232
- * group.
233
- */
234
-
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-#define ASPEED_IP_SCU		0
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-#define ASPEED_IP_GFX		1
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-#define ASPEED_IP_LPC		2
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-#define ASPEED_NR_PINMUX_IPS	3
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-
240
-/*
241
- * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
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- * references registers by the device/offset mnemonic. The register macros
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- * below are named the same way to ease transcription and verification (as
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- * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
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- * reference registers beyond those dedicated to pinmux, such as the system
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- * reset control and MAC clock configuration registers. The AST2500 goes a step
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- * further and references registers in the graphics IP block, but that isn't
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- * handled yet.
249
- */
250
-#define SCU2C           0x2C /* Misc. Control Register */
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-#define SCU3C           0x3C /* System Reset Control/Status Register */
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-#define SCU48           0x48 /* MAC Interface Clock Delay Setting */
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-#define HW_STRAP1       0x70 /* AST2400 strapping is 33 bits, is split */
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-#define HW_REVISION_ID  0x7C /* Silicon revision ID register */
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-#define SCU80           0x80 /* Multi-function Pin Control #1 */
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-#define SCU84           0x84 /* Multi-function Pin Control #2 */
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-#define SCU88           0x88 /* Multi-function Pin Control #3 */
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-#define SCU8C           0x8C /* Multi-function Pin Control #4 */
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-#define SCU90           0x90 /* Multi-function Pin Control #5 */
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-#define SCU94           0x94 /* Multi-function Pin Control #6 */
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-#define SCUA0           0xA0 /* Multi-function Pin Control #7 */
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-#define SCUA4           0xA4 /* Multi-function Pin Control #8 */
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-#define SCUA8           0xA8 /* Multi-function Pin Control #9 */
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-#define SCUAC           0xAC /* Multi-function Pin Control #10 */
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-#define HW_STRAP2       0xD0 /* Strapping */
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-
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- /**
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-  * A signal descriptor, which describes the register, bits and the
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-  * enable/disable values that should be compared or written.
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-  *
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-  * @ip: The IP block identifier, used as an index into the regmap array in
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-  *      struct aspeed_pinctrl_data
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-  * @reg: The register offset with respect to the base address of the IP block
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-  * @mask: The mask to apply to the register. The lowest set bit of the mask is
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-  *        used to derive the shift value.
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-  * @enable: The value that enables the function. Value should be in the LSBs,
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-  *          not at the position of the mask.
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-  * @disable: The value that disables the function. Value should be in the
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-  *           LSBs, not at the position of the mask.
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-  */
281
-struct aspeed_sig_desc {
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-	unsigned int ip;
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-	unsigned int reg;
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-	u32 mask;
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-	u32 enable;
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-	u32 disable;
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-};
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-
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-/**
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- * Describes a signal expression. The expression is evaluated by ANDing the
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- * evaluation of the descriptors.
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- *
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- * @signal: The signal name for the priority level on the pin. If the signal
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- *          type is GPIO, then the signal name must begin with the string
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- *          "GPIO", e.g. GPIOA0, GPIOT4 etc.
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- * @function: The name of the function the signal participates in for the
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- *            associated expression
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- * @ndescs: The number of signal descriptors in the expression
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- * @descs: Pointer to an array of signal descriptors that comprise the
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- *         function expression
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- */
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-struct aspeed_sig_expr {
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-	const char *signal;
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-	const char *function;
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-	int ndescs;
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-	const struct aspeed_sig_desc *descs;
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-};
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-
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-/**
310
- * A struct capturing the list of expressions enabling signals at each priority
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- * for a given pin. The signal configuration for a priority level is evaluated
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- * by ORing the evaluation of the signal expressions in the respective
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- * priority's list.
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- *
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- * @name: A name for the pin
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- * @prios: A pointer to an array of expression list pointers
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- *
318
- */
319
-struct aspeed_pin_desc {
320
-	const char *name;
321
-	const struct aspeed_sig_expr ***prios;
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-};
323
-
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-/* Macro hell */
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-
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-#define SIG_DESC_IP_BIT(ip, reg, idx, val) \
327
-	{ ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
328
-
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-/**
330
- * Short-hand macro for describing an SCU descriptor enabled by the state of
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- * one bit. The disable value is derived.
332
- *
333
- * @reg: The signal's associated register, offset from base
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- * @idx: The signal's bit index in the register
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- * @val: The value (0 or 1) that enables the function
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- */
337
-#define SIG_DESC_BIT(reg, idx, val) \
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-	SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
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-
340
-#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
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-
342
-/**
343
- * A further short-hand macro expanding to an SCU descriptor enabled by a set
344
- * bit.
345
- *
346
- * @reg: The register, offset from base
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- * @idx: The bit index in the register
348
- */
349
-#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
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-
351
-#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
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-#define SIG_DESC_LIST_DECL(sig, func, ...) \
353
-	static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
354
-		{ __VA_ARGS__ }
355
-
356
-#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
357
-#define SIG_EXPR_DECL_(sig, func) \
358
-	static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
359
-	{ \
360
-		.signal = #sig, \
361
-		.function = #func, \
362
-		.ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
363
-		.descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
364
-	}
365
-
366
-/**
367
- * Declare a signal expression.
368
- *
369
- * @sig: A macro symbol name for the signal (is subjected to stringification
370
- *        and token pasting)
371
- * @func: The function in which the signal is participating
372
- * @...: Signal descriptors that define the signal expression
373
- *
374
- * For example, the following declares the ROMD8 signal for the ROM16 function:
375
- *
376
- *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
377
- *
378
- * And with multiple signal descriptors:
379
- *
380
- *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
381
- *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
382
- */
383
-#define SIG_EXPR_DECL(sig, func, ...) \
384
-	SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
385
-	SIG_EXPR_DECL_(sig, func)
386
-
387
-/**
388
- * Declare a pointer to a signal expression
389
- *
390
- * @sig: The macro symbol name for the signal (subjected to token pasting)
391
- * @func: The macro symbol name for the function (subjected to token pasting)
392
- */
393
-#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
394
-
395
-#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
396
-
397
-/**
398
- * Declare a signal expression list for reference in a struct aspeed_pin_prio.
399
- *
400
- * @sig: A macro symbol name for the signal (is subjected to token pasting)
401
- * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
402
- *
403
- * For example, the 16-bit ROM bus can be enabled by one of two possible signal
404
- * expressions:
405
- *
406
- *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
407
- *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
408
- *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
409
- *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
410
- *              SIG_EXPR_PTR(ROMD8, ROM16S));
411
- */
412
-#define SIG_EXPR_LIST_DECL(sig, ...) \
413
-	static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
414
-		{ __VA_ARGS__, NULL }
415
-
416
-/**
417
- * A short-hand macro for declaring a function expression and an expression
418
- * list with a single function.
419
- *
420
- * @func: A macro symbol name for the function (is subjected to token pasting)
421
- * @...: Function descriptors that define the function expression
422
- *
423
- * For example, signal NCTS6 participates in its own function with one group:
424
- *
425
- *     SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
426
- */
427
-#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
428
-	SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
429
-	SIG_EXPR_DECL_(sig, func); \
430
-	SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
431
-
432
-#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
433
-	SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
434
-
435
-#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
436
-
437
-#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
438
-#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
439
-#define PIN_SYM(pin) pin_ ## pin
440
-
441
-#define MS_PIN_DECL_(pin, ...) \
442
-	static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
443
-		{ __VA_ARGS__, NULL }; \
444
-	static const struct aspeed_pin_desc PIN_SYM(pin) = \
445
-		{ #pin, PIN_EXPRS_PTR(pin) }
446
-
447
-/**
448
- * Declare a multi-signal pin
449
- *
450
- * @pin: The pin number
451
- * @other: Macro name for "other" functionality (subjected to stringification)
452
- * @high: Macro name for the highest priority signal functions
453
- * @low: Macro name for the low signal functions
454
- *
455
- * For example:
456
- *
457
- *     #define A8 56
458
- *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
459
- *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
460
- *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
461
- *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
462
- *              SIG_EXPR_PTR(ROMD8, ROM16S));
463
- *     SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
464
- *     MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
465
- */
466
-#define MS_PIN_DECL(pin, other, high, low) \
467
-	SIG_EXPR_LIST_DECL_SINGLE(other, other); \
468
-	MS_PIN_DECL_(pin, \
469
-			SIG_EXPR_LIST_PTR(high), \
470
-			SIG_EXPR_LIST_PTR(low), \
471
-			SIG_EXPR_LIST_PTR(other))
472
-
473
-#define PIN_GROUP_SYM(func) pins_ ## func
474
-#define FUNC_GROUP_SYM(func) groups_ ## func
475
-#define FUNC_GROUP_DECL(func, ...) \
476
-	static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
477
-	static const char *FUNC_GROUP_SYM(func)[] = { #func }
478
-
479
-/**
480
- * Declare a single signal pin
481
- *
482
- * @pin: The pin number
483
- * @other: Macro name for "other" functionality (subjected to stringification)
484
- * @sig: Macro name for the signal (subjected to stringification)
485
- *
486
- * For example:
487
- *
488
- *     #define E3 80
489
- *     SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
490
- *     SS_PIN_DECL(E3, GPIOK0, SCL5);
491
- */
492
-#define SS_PIN_DECL(pin, other, sig) \
493
-	SIG_EXPR_LIST_DECL_SINGLE(other, other); \
494
-	MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
495
-
496
-/**
497
- * Single signal, single function pin declaration
498
- *
499
- * @pin: The pin number
500
- * @other: Macro name for "other" functionality (subjected to stringification)
501
- * @sig: Macro name for the signal (subjected to stringification)
502
- * @...: Signal descriptors that define the function expression
503
- *
504
- * For example:
505
- *
506
- *    SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
507
- */
508
-#define SSSF_PIN_DECL(pin, other, sig, ...) \
509
-	SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
510
-	SIG_EXPR_LIST_DECL_SINGLE(other, other); \
511
-	MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
512
-	FUNC_GROUP_DECL(sig, pin)
513
-
514
-#define GPIO_PIN_DECL(pin, gpio) \
515
-	SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
516
-	MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
15
+#include "pinmux-aspeed.h"
51716 
51817 /**
51918  * @param The pinconf parameter type
....@@ -525,24 +24,7 @@
52524 	enum pin_config_param param;
52625 	unsigned int pins[2];
52726 	unsigned int reg;
528
-	u8 bit;
529
-	u8 value;
530
-};
531
-
532
-struct aspeed_pinctrl_data {
533
-	struct regmap *maps[ASPEED_NR_PINMUX_IPS];
534
-
535
-	const struct pinctrl_pin_desc *pins;
536
-	const unsigned int npins;
537
-
538
-	const struct aspeed_pin_group *groups;
539
-	const unsigned int ngroups;
540
-
541
-	const struct aspeed_pin_function *functions;
542
-	const unsigned int nfunctions;
543
-
544
-	const struct aspeed_pin_config *configs;
545
-	const unsigned int nconfigs;
27
+	u32 mask;
54628 };
54729 
54830 #define ASPEED_PINCTRL_PIN(name_) \
....@@ -552,30 +34,54 @@
55234 		.drv_data = (void *) &(PIN_SYM(name_)) \
55335 	}
55436 
555
-struct aspeed_pin_group {
556
-	const char *name;
557
-	const unsigned int *pins;
37
+#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \
38
+	.param = param_, \
39
+	.pins = {pin0_, pin1_}, \
40
+	.reg = reg_, \
41
+	.mask = BIT_MASK(bit_) \
42
+}
43
+
44
+#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
45
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
46
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   pin_, pin_, reg_, bit_)
47
+
48
+#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
49
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
50
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
51
+/*
52
+ * Aspeed pin configuration description.
53
+ *
54
+ * @param: pinconf configuration parameter
55
+ * @arg: The supported argument for @param, or -1 if any value is supported
56
+ * @val: The register value to write to configure @arg for @param
57
+ * @mask: The bitfield mask for @val
58
+ *
59
+ * The map is to be used in conjunction with the configuration array supplied
60
+ * by the driver implementation.
61
+ */
62
+struct aspeed_pin_config_map {
63
+	enum pin_config_param param;
64
+	s32 arg;
65
+	u32 val;
66
+	u32 mask;
67
+};
68
+
69
+struct aspeed_pinctrl_data {
70
+	struct regmap *scu;
71
+
72
+	const struct pinctrl_pin_desc *pins;
55873 	const unsigned int npins;
74
+
75
+	const struct aspeed_pin_config *configs;
76
+	const unsigned int nconfigs;
77
+
78
+	struct aspeed_pinmux_data pinmux;
79
+
80
+	const struct aspeed_pin_config_map *confmaps;
81
+	const unsigned int nconfmaps;
55982 };
56083 
561
-#define ASPEED_PINCTRL_GROUP(name_) { \
562
-	.name = #name_, \
563
-	.pins = &(PIN_GROUP_SYM(name_))[0], \
564
-	.npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
565
-}
566
-
567
-struct aspeed_pin_function {
568
-	const char *name;
569
-	const char *const *groups;
570
-	unsigned int ngroups;
571
-};
572
-
573
-#define ASPEED_PINCTRL_FUNC(name_, ...) { \
574
-	.name = #name_, \
575
-	.groups = &FUNC_GROUP_SYM(name_)[0], \
576
-	.ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
577
-}
578
-
84
+/* Aspeed pinctrl helpers */
57985 int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
58086 const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
58187 		unsigned int group);