forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/phy/rockchip/phy-rockchip-naneng-usb2.c
....@@ -109,7 +109,6 @@
109109  * @ls_det_en: linestate detection enable register.
110110  * @ls_det_st: linestate detection state register.
111111  * @ls_det_clr: linestate detection clear register.
112
- * @phy_chg_mode: set phy in charge detection mode.
113112  * @phy_sus: phy suspend register.
114113  * @utmi_bvalid: utmi vbus bvalid status register.
115114  * @utmi_iddig: otg port id pin status register.
....@@ -141,7 +140,6 @@
141140 	struct usb2phy_reg	ls_det_en;
142141 	struct usb2phy_reg	ls_det_st;
143142 	struct usb2phy_reg	ls_det_clr;
144
-	struct usb2phy_reg	phy_chg_mode;
145143 	struct usb2phy_reg	phy_sus;
146144 	struct usb2phy_reg	utmi_bvalid;
147145 	struct usb2phy_reg	utmi_iddig;
....@@ -221,7 +219,6 @@
221219  * @dev: pointer to our struct device.
222220  * @grf: General Register Files regmap.
223221  * @base: the base address of APB interface.
224
- * @apb_reset: apb reset signal for phy.
225222  * @reset: power reset signal for phy.
226223  * @clks: array of input clocks.
227224  * @num_clks: number of input clocks.
....@@ -240,7 +237,6 @@
240237 	struct device		*dev;
241238 	struct regmap		*grf;
242239 	void __iomem		*base;
243
-	struct reset_control	*apb_reset;
244240 	struct reset_control	*reset;
245241 	struct clk_bulk_data	*clks;
246242 	int			num_clks;
....@@ -358,7 +354,7 @@
358354 	/* optional override of the clockname */
359355 	of_property_read_string(node, "clock-output-names", &init.name);
360356 
361
-	if (refclk) {
357
+	if (!IS_ERR(refclk)) {
362358 		clk_name = __clk_get_name(refclk);
363359 		init.parent_names = &clk_name;
364360 		init.num_parents = 1;
....@@ -663,7 +659,8 @@
663659 	return ret;
664660 }
665661 
666
-static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode)
662
+static int rockchip_usb2phy_set_mode(struct phy *phy,
663
+				     enum phy_mode mode, int submode)
667664 {
668665 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
669666 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
....@@ -800,45 +797,12 @@
800797 				struct rockchip_usb2phy_port *rport)
801798 {
802799 	bool chg_valid, phy_connect;
803
-	const struct usb2phy_reg *phy_sus_reg;
804
-	unsigned int phy_sus_cfg, mask;
805
-	int result, cnt, ret;
800
+	int result;
801
+	int cnt;
806802 
807803 	mutex_lock(&rport->mutex);
808804 
809
-	/*
810
-	 * We are violating what the phy specification says about
811
-	 * the charge detection process. Ideally we need to hold
812
-	 * the phy in the reset state during the charge detection
813
-	 * process, but that's causing trouble synchronizing between
814
-	 * the phy and usb controller because CLK60_30 is disabled
815
-	 * while phy in reset.
816
-	 *
817
-	 * We have discussed this with the phy IP Provider, and
818
-	 * it was suggested to keep the CLK60_30 while do charging
819
-	 * detection.
820
-	 *
821
-	 * Set the phy in charge mode (keep the CLK60_30):
822
-	 * Enable the DP/DM pulldown resistor;
823
-	 * Set the opmode to non-driving mode;
824
-	 * Set the phy controlled by GRF utmi interface, and set
825
-	 * the utmi in normal mode to keep the CLK60_30.
826
-	 */
827
-	phy_sus_reg = &rport->port_cfg->phy_sus;
828
-	ret = regmap_read(rphy->grf, phy_sus_reg->offset, &phy_sus_cfg);
829
-	if (ret) {
830
-		dev_err(&rport->phy->dev,
831
-			"Fail to read phy_sus reg offset 0x%x, ret %d\n",
832
-			phy_sus_reg->offset, ret);
833
-		goto unlock;
834
-	}
835
-
836
-	ret = property_enable(rphy->grf, &rport->port_cfg->phy_chg_mode, true);
837
-	if (ret) {
838
-		dev_err(&rport->phy->dev,
839
-			"Fail to set phy_chg_mode reg, ret %d\n", ret);
840
-		goto unlock;
841
-	}
805
+	reset_control_assert(rphy->reset);
842806 
843807 	/* CHG_RST is set to 1'b0 to start charge detection */
844808 	property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true);
....@@ -878,21 +842,15 @@
878842 	dev_info(&rport->phy->dev, "charger = %s\n",
879843 		 chg_to_string(rphy->chg_type));
880844 
845
+	usleep_range(1000, 1100);
846
+	reset_control_deassert(rphy->reset);
847
+	/* waiting for the utmi_clk to become stable */
848
+	usleep_range(2500, 3000);
849
+
881850 	/* disable the chg detection module */
882851 	property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true);
883852 	property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false);
884853 
885
-	mask = GENMASK(phy_sus_reg->bitend, phy_sus_reg->bitstart);
886
-	/* Restore the phy suspend configuration */
887
-	ret = regmap_write(rphy->grf, phy_sus_reg->offset,
888
-			   ((phy_sus_cfg << phy_sus_reg->bitstart) |
889
-			    (mask << BIT_WRITEABLE_SHIFT)));
890
-	if (ret)
891
-		dev_err(&rport->phy->dev,
892
-			"Fail to set phy_sus reg offset 0x%x, ret %d\n",
893
-			phy_sus_reg->offset, ret);
894
-
895
-unlock:
896854 	mutex_unlock(&rport->mutex);
897855 }
898856 
....@@ -1120,7 +1078,7 @@
11201078 		extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
11211079 		extcon_sync(rphy->edev, EXTCON_USB);
11221080 		extcon_sync(rphy->edev, EXTCON_USB_HOST);
1123
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST);
1081
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
11241082 		property_enable(rphy->grf, &rport->port_cfg->idpullup,
11251083 				false);
11261084 		property_enable(rphy->grf, &rport->port_cfg->iddig_output,
....@@ -1129,7 +1087,7 @@
11291087 				true);
11301088 		break;
11311089 	case USB_DR_MODE_PERIPHERAL:
1132
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE);
1090
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
11331091 		property_enable(rphy->grf, &rport->port_cfg->idpullup,
11341092 				true);
11351093 		property_enable(rphy->grf, &rport->port_cfg->iddig_output,
....@@ -1138,7 +1096,7 @@
11381096 				true);
11391097 		break;
11401098 	case USB_DR_MODE_OTG:
1141
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG);
1099
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
11421100 		property_enable(rphy->grf, &rport->port_cfg->iddig_output,
11431101 				false);
11441102 		property_enable(rphy->grf, &rport->port_cfg->iddig_en,
....@@ -1309,7 +1267,7 @@
13091267 			extcon_set_state(rphy->edev, EXTCON_USB, false);
13101268 			extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
13111269 		}
1312
-		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST);
1270
+		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
13131271 		/*
13141272 		 * Here set iddig to 0 by disable idpullup, the otg_suspendm
13151273 		 * will be set to 1 to enable the disconnect detection module,
....@@ -1509,10 +1467,6 @@
15091467 	if (IS_ERR(rphy->reset))
15101468 		return PTR_ERR(rphy->reset);
15111469 
1512
-	rphy->apb_reset = devm_reset_control_get(dev, "u2phy-apb");
1513
-	if (IS_ERR(rphy->apb_reset))
1514
-		return PTR_ERR(rphy->apb_reset);
1515
-
15161470 	rphy->vup_gpio = devm_gpiod_get_optional(dev, "vup", GPIOD_OUT_LOW);
15171471 	if (IS_ERR(rphy->vup_gpio)) {
15181472 		ret = PTR_ERR(rphy->vup_gpio);
....@@ -1520,11 +1474,9 @@
15201474 		return ret;
15211475 	}
15221476 
1523
-	reset_control_assert(rphy->apb_reset);
15241477 	reset_control_assert(rphy->reset);
15251478 	udelay(1);
15261479 	reset_control_deassert(rphy->reset);
1527
-	reset_control_deassert(rphy->apb_reset);
15281480 
15291481 	match = of_match_device(dev->driver->of_match_table, dev);
15301482 	if (!match || !match->data) {
....@@ -1914,7 +1866,6 @@
19141866 				.ls_det_en = { 0x10300, 0, 0, 0, 1 },
19151867 				.ls_det_st = { 0x10304, 0, 0, 0, 1 },
19161868 				.ls_det_clr = { 0x10308, 0, 0, 0, 1 },
1917
-				.phy_chg_mode = { 0x10230, 8, 0, 0x052, 0x1d7 },
19181869 				.phy_sus = { 0x10230, 8, 0, 0x052, 0x1d5 },
19191870 				.utmi_bvalid = { 0x10248, 9, 9, 0, 1 },
19201871 				.utmi_iddig = { 0x10248, 6, 6, 0, 1 },