forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c
....@@ -14,12 +14,10 @@
1414 #include <linux/module.h>
1515 #include <linux/of_device.h>
1616 #include <linux/platform_device.h>
17
-#include <linux/regmap.h>
1817 #include <linux/reset.h>
1918 #include <linux/phy/phy.h>
2019 #include <linux/pm_runtime.h>
2120 #include <linux/mfd/syscon.h>
22
-#include <linux/rockchip/cpu.h>
2321 
2422 #define PSEC_PER_SEC	1000000000000LL
2523 
....@@ -84,27 +82,12 @@
8482 #define DATA_LANE_0_SKEW_PHASE_MASK		GENMASK(2, 0)
8583 #define DATA_LANE_0_SKEW_PHASE(x)		UPDATE(x, 2, 0)
8684 /* Analog Register Part: reg08 */
87
-#define PRE_EMPHASIS_ENABLE_MASK		BIT(7)
88
-#define PRE_EMPHASIS_ENABLE			BIT(7)
89
-#define PRE_EMPHASIS_DISABLE			0
90
-#define PLL_POST_DIV_ENABLE_MASK		BIT(5)
91
-#define PLL_POST_DIV_ENABLE			BIT(5)
92
-#define PLL_POST_DIV_DISABLE			0
93
-#define DATA_LANE_VOD_RANGE_SET_MASK		GENMASK(3, 0)
94
-#define DATA_LANE_VOD_RANGE_SET(x)		UPDATE(x, 3, 0)
9585 #define SAMPLE_CLOCK_DIRECTION_MASK		BIT(4)
9686 #define SAMPLE_CLOCK_DIRECTION_REVERSE		BIT(4)
9787 #define SAMPLE_CLOCK_DIRECTION_FORWARD		0
9888 #define LOWFRE_EN_MASK				BIT(5)
9989 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1		0
10090 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2		1
101
-/* Analog Register Part: reg0b */
102
-#define CLOCK_LANE_VOD_RANGE_SET_MASK		GENMASK(3, 0)
103
-#define CLOCK_LANE_VOD_RANGE_SET(x)		UPDATE(x, 3, 0)
104
-#define VOD_MIN_RANGE				0x1
105
-#define VOD_MID_RANGE				0x3
106
-#define VOD_BIG_RANGE				0x7
107
-#define VOD_MAX_RANGE				0xf
10891 /* Analog Register Part: reg1e */
10992 #define PLL_MODE_SEL_MASK			GENMASK(6, 5)
11093 #define PLL_MODE_SEL_LVDS_MODE			0
....@@ -124,22 +107,20 @@
124107 #define T_LPX_CNT_MASK				GENMASK(5, 0)
125108 #define T_LPX_CNT(x)				UPDATE(x, 5, 0)
126109 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
127
-#define T_HS_ZERO_CNT_HI_MASK			BIT(7)
128
-#define T_HS_ZERO_CNT_HI(x)			UPDATE(x, 7, 7)
129110 #define T_HS_PREPARE_CNT_MASK			GENMASK(6, 0)
130111 #define T_HS_PREPARE_CNT(x)			UPDATE(x, 6, 0)
131112 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
132
-#define T_HS_ZERO_CNT_LO_MASK			GENMASK(5, 0)
133
-#define T_HS_ZERO_CNT_LO(x)			UPDATE(x, 5, 0)
113
+#define T_HS_ZERO_CNT_MASK			GENMASK(5, 0)
114
+#define T_HS_ZERO_CNT(x)			UPDATE(x, 5, 0)
134115 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
135116 #define T_HS_TRAIL_CNT_MASK			GENMASK(6, 0)
136117 #define T_HS_TRAIL_CNT(x)			UPDATE(x, 6, 0)
137118 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
138
-#define T_HS_EXIT_CNT_LO_MASK			GENMASK(4, 0)
139
-#define T_HS_EXIT_CNT_LO(x)			UPDATE(x, 4, 0)
119
+#define T_HS_EXIT_CNT_MASK			GENMASK(4, 0)
120
+#define T_HS_EXIT_CNT(x)			UPDATE(x, 4, 0)
140121 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
141
-#define T_CLK_POST_CNT_LO_MASK			GENMASK(3, 0)
142
-#define T_CLK_POST_CNT_LO(x)			UPDATE(x, 3, 0)
122
+#define T_CLK_POST_CNT_MASK			GENMASK(3, 0)
123
+#define T_CLK_POST_CNT(x)			UPDATE(x, 3, 0)
143124 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
144125 #define LPDT_TX_PPI_SYNC_MASK			BIT(2)
145126 #define LPDT_TX_PPI_SYNC_ENABLE			BIT(2)
....@@ -153,13 +134,9 @@
153134 #define T_CLK_PRE_CNT_MASK			GENMASK(3, 0)
154135 #define T_CLK_PRE_CNT(x)			UPDATE(x, 3, 0)
155136 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
156
-#define T_CLK_POST_HI_MASK			GENMASK(7, 6)
157
-#define T_CLK_POST_HI(x)			UPDATE(x, 7, 6)
158137 #define T_TA_GO_CNT_MASK			GENMASK(5, 0)
159138 #define T_TA_GO_CNT(x)				UPDATE(x, 5, 0)
160139 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
161
-#define T_HS_EXIT_CNT_HI_MASK			BIT(6)
162
-#define T_HS_EXIT_CNT_HI(x)			UPDATE(x, 6, 6)
163140 #define T_TA_SURE_CNT_MASK			GENMASK(5, 0)
164141 #define T_TA_SURE_CNT(x)			UPDATE(x, 5, 0)
165142 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
....@@ -197,19 +174,6 @@
197174 #define DSI_PHY_STATUS		0xb0
198175 #define PHY_LOCK		BIT(0)
199176 
200
-enum soc_type {
201
-	PX30,
202
-	PX30S,
203
-	RK3128,
204
-	RK3368,
205
-	RK3568,
206
-};
207
-
208
-enum phy_max_rate {
209
-	MAX_1GHZ,
210
-	MAX_2_5GHZ,
211
-};
212
-
213177 struct mipi_dphy_timing {
214178 	unsigned int clkmiss;
215179 	unsigned int clkpost;
....@@ -235,26 +199,14 @@
235199 	unsigned int wakeup;
236200 };
237201 
238
-struct inno_mipi_dphy_timing {
239
-	unsigned int max_lane_mbps;
240
-	u8 lpx;
241
-	u8 hs_prepare;
242
-	u8 clk_lane_hs_zero;
243
-	u8 data_lane_hs_zero;
244
-	u8 hs_trail;
245
-};
246
-
247202 struct inno_video_phy {
248203 	struct device *dev;
249204 	struct clk *ref_clk;
250205 	struct clk *pclk_phy;
251206 	struct clk *pclk_host;
252
-	struct regmap *regmap;
207
+	void __iomem *phy_base;
253208 	void __iomem *host_base;
254209 	struct reset_control *rst;
255
-	enum phy_mode mode;
256
-	unsigned int lanes;
257
-	const struct inno_video_phy_plat_data *pdata;
258210 
259211 	struct {
260212 		struct clk_hw hw;
....@@ -262,13 +214,6 @@
262214 		u16 fbdiv;
263215 		unsigned long rate;
264216 	} pll;
265
-};
266
-
267
-struct inno_video_phy_plat_data {
268
-	enum soc_type soc_type;
269
-	const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
270
-	const unsigned int num_timings;
271
-	enum phy_max_rate max_rate;
272217 };
273218 
274219 enum {
....@@ -282,44 +227,6 @@
282227 	REGISTER_PART_LVDS,
283228 };
284229 
285
-static const
286
-struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = {
287
-	{ 110, 0x0, 0x20, 0x16, 0x02, 0x22},
288
-	{ 150, 0x0, 0x06, 0x16, 0x03, 0x45},
289
-	{ 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
290
-	{ 250, 0x0, 0x05, 0x17, 0x05, 0x16},
291
-	{ 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
292
-	{ 400, 0x0, 0x64, 0x19, 0x07, 0x33},
293
-	{ 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
294
-	{ 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
295
-	{ 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
296
-	{ 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
297
-	{1000, 0x0, 0x09, 0x20, 0x09, 0x27},
298
-};
299
-
300
-static const
301
-struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = {
302
-	{ 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
303
-	{ 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
304
-	{ 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
305
-	{ 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
306
-	{ 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
307
-	{ 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
308
-	{ 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
309
-	{ 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
310
-	{ 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
311
-	{ 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
312
-	{1000, 0x05, 0x08, 0x20, 0x09, 0x30},
313
-	{1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
314
-	{1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
315
-	{1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
316
-	{1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
317
-	{2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
318
-	{2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
319
-	{2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
320
-	{2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
321
-};
322
-
323230 static inline struct inno_video_phy *hw_to_inno(struct clk_hw *hw)
324231 {
325232 	return container_of(hw, struct inno_video_phy, pll.hw);
....@@ -329,8 +236,12 @@
329236 			    u8 first, u8 second, u8 mask, u8 val)
330237 {
331238 	u32 reg = PHY_REG(first, second) << 2;
239
+	unsigned int tmp, orig;
332240 
333
-	regmap_update_bits(inno->regmap, reg, mask, val);
241
+	orig = readl(inno->phy_base + reg);
242
+	tmp = orig & ~mask;
243
+	tmp |= val & mask;
244
+	writel(tmp, inno->phy_base + reg);
334245 }
335246 
336247 static void host_update_bits(struct inno_video_phy *inno,
....@@ -372,49 +283,37 @@
372283 	timing->wakeup = 1000000000;
373284 }
374285 
375
-static const struct inno_mipi_dphy_timing *
376
-inno_mipi_dphy_get_timing(struct inno_video_phy *inno)
286
+static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
377287 {
378
-	const struct inno_mipi_dphy_timing *timings;
379
-	unsigned int num_timings;
380
-	unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
288
+	struct mipi_dphy_timing gotp;
289
+	const struct {
290
+		unsigned long rate;
291
+		u8 hs_prepare;
292
+		u8 clk_lane_hs_zero;
293
+		u8 data_lane_hs_zero;
294
+		u8 hs_trail;
295
+	} timings[] = {
296
+		{ 110000000, 0x20, 0x16, 0x02, 0x22},
297
+		{ 150000000, 0x06, 0x16, 0x03, 0x45},
298
+		{ 200000000, 0x18, 0x17, 0x04, 0x0b},
299
+		{ 250000000, 0x05, 0x17, 0x05, 0x16},
300
+		{ 300000000, 0x51, 0x18, 0x06, 0x2c},
301
+		{ 400000000, 0x64, 0x19, 0x07, 0x33},
302
+		{ 500000000, 0x20, 0x1b, 0x07, 0x4e},
303
+		{ 600000000, 0x6a, 0x1d, 0x08, 0x3a},
304
+		{ 700000000, 0x3e, 0x1e, 0x08, 0x6a},
305
+		{ 800000000, 0x21, 0x1f, 0x09, 0x29},
306
+		{1000000000, 0x09, 0x20, 0x09, 0x27},
307
+	};
308
+	u32 t_txbyteclkhs, t_txclkesc, ui;
309
+	u32 txbyteclkhs, txclkesc, esc_clk_div;
310
+	u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
311
+	u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
381312 	unsigned int i;
382313 
383
-	timings = inno->pdata->inno_mipi_dphy_timing_table;
384
-	num_timings = inno->pdata->num_timings;
385
-
386
-	for (i = 0; i < num_timings; i++)
387
-		if (lane_mbps <= timings[i].max_lane_mbps)
388
-			break;
389
-
390
-	if (i == num_timings)
391
-		--i;
392
-
393
-	return &timings[i];
394
-
395
-}
396
-
397
-static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy *inno)
398
-{
399
-
400
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
401
-			REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
402
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
403
-			REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
404
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
405
-			REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
406
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
407
-			PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
408
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
409
-			CLOCK_LANE_VOD_RANGE_SET_MASK,
410
-			CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
411
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
412
-			 REG_LDOPD_MASK | REG_PLLPD_MASK,
413
-			 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
414
-}
415
-
416
-static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy *inno)
417
-{
314
+	/* Select MIPI mode */
315
+	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
316
+			MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
418317 	/* Configure PLL */
419318 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
420319 			REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
....@@ -426,10 +325,6 @@
426325 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
427326 			REG_LDOPD_MASK | REG_PLLPD_MASK,
428327 			REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
429
-}
430
-
431
-static void inno_mipi_dphy_reset(struct inno_video_phy *inno)
432
-{
433328 	/* Reset analog */
434329 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
435330 			REG_SYNCRST_MASK, REG_SYNCRST_RESET);
....@@ -442,21 +337,10 @@
442337 	udelay(1);
443338 	phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
444339 			REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
445
-}
446
-
447
-static void inno_mipi_dphy_timing_init(struct inno_video_phy *inno)
448
-{
449
-	struct mipi_dphy_timing gotp;
450
-	u32 t_txbyteclkhs, t_txclkesc, ui, sys_clk;
451
-	u32 txbyteclkhs, txclkesc, esc_clk_div;
452
-	u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
453
-	u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
454
-	const struct inno_mipi_dphy_timing *timing;
455
-	unsigned int i;
456340 
457341 	txbyteclkhs = inno->pll.rate / 8;
458342 	t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
459
-	sys_clk = clk_get_rate(inno->pclk_phy);
343
+
460344 	esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
461345 	txclkesc = txbyteclkhs / esc_clk_div;
462346 	t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
....@@ -482,9 +366,14 @@
482366 	 */
483367 	clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
484368 
485
-	wakeup = DIV_ROUND_CLOSEST_ULL(gotp.wakeup * sys_clk, PSEC_PER_SEC);
486
-	if (wakeup > 0x3ff)
487
-		wakeup = 0x3ff;
369
+	/*
370
+	 * The value of counter for HS Tlpx Time
371
+	 * Tlpx = Tpin_txbyteclkhs * (2 + value)
372
+	 */
373
+	lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
374
+	if (lpx >= 2)
375
+		lpx -= 2;
376
+
488377 	/*
489378 	 * The value of counter for HS Tta-go
490379 	 * Tta-go for turnaround
....@@ -504,23 +393,18 @@
504393 	 */
505394 	ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
506395 
507
-	timing = inno_mipi_dphy_get_timing(inno);
396
+	for (i = 0; i < ARRAY_SIZE(timings); i++)
397
+		if (inno->pll.rate <= timings[i].rate)
398
+			break;
508399 
509
-	/*
510
-	 * The value of counter for HS Tlpx Time
511
-	 * Tlpx = Tpin_txbyteclkhs * (2 + value)
512
-	 */
513
-	if (inno->pdata->max_rate == MAX_1GHZ) {
514
-		lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
515
-		if (lpx >= 2)
516
-			lpx -= 2;
517
-	} else
518
-		lpx = timing->lpx;
400
+	if (i == ARRAY_SIZE(timings))
401
+		--i;
519402 
520
-	hs_prepare = timing->hs_prepare;
521
-	hs_trail = timing->hs_trail;
522
-	clk_lane_hs_zero = timing->clk_lane_hs_zero;
523
-	data_lane_hs_zero = timing->data_lane_hs_zero;
403
+	hs_prepare = timings[i].hs_prepare;
404
+	hs_trail = timings[i].hs_trail;
405
+	clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
406
+	data_lane_hs_zero = timings[i].data_lane_hs_zero;
407
+	wakeup = 0x3ff;
524408 
525409 	for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
526410 		if (i == REGISTER_PART_CLOCK_LANE)
....@@ -532,29 +416,14 @@
532416 				T_LPX_CNT(lpx));
533417 		phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
534418 				T_HS_PREPARE_CNT(hs_prepare));
535
-
536
-		if (inno->pdata->max_rate == MAX_2_5GHZ)
537
-			phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
538
-					T_HS_ZERO_CNT_HI(hs_zero >> 6));
539
-
540
-		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
541
-				T_HS_ZERO_CNT_LO(hs_zero));
419
+		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
420
+				T_HS_ZERO_CNT(hs_zero));
542421 		phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
543422 				T_HS_TRAIL_CNT(hs_trail));
544
-
545
-		if (inno->pdata->max_rate == MAX_2_5GHZ)
546
-			phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
547
-					T_HS_EXIT_CNT_HI(hs_exit >> 5));
548
-
549
-		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
550
-				T_HS_EXIT_CNT_LO(hs_exit));
551
-
552
-		if (inno->pdata->max_rate == MAX_2_5GHZ)
553
-			phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
554
-					T_CLK_POST_HI(clk_post >> 4));
555
-
556
-		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
557
-				T_CLK_POST_CNT_LO(clk_post));
423
+		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
424
+				T_HS_EXIT_CNT(hs_exit));
425
+		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
426
+				T_CLK_POST_CNT(clk_post));
558427 		phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
559428 				T_CLK_PRE_CNT(clk_pre));
560429 		phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
....@@ -569,53 +438,10 @@
569438 				T_TA_WAIT_CNT(ta_wait));
570439 	}
571440 
572
-}
573
-
574
-static void inno_mipi_dphy_lane_enable(struct inno_video_phy *inno)
575
-{
576
-	u8 val = LANE_EN_CK;
577
-
578
-	switch (inno->lanes) {
579
-	case 1:
580
-		val |= LANE_EN_0;
581
-		break;
582
-	case 2:
583
-		val |= LANE_EN_1 | LANE_EN_0;
584
-		break;
585
-	case 3:
586
-		val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
587
-		break;
588
-	case 4:
589
-	default:
590
-		val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
591
-		break;
592
-	}
593
-
594
-	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
595
-}
596
-
597
-
598
-static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
599
-{
600
-	/* Select MIPI mode */
601
-	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
602
-			MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
603
-
604
-	/* set pin_txclkesc_0 pin_txbyteclk invert disable */
605
-	if (inno->pdata->soc_type == PX30S)
606
-		phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,
607
-				INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE);
608
-
609
-	if (inno->pdata->max_rate == MAX_2_5GHZ)
610
-		inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
611
-	else
612
-		inno_mipi_dphy_max_1GHz_pll_enable(inno);
613
-
614
-	inno_mipi_dphy_reset(inno);
615
-
616
-	inno_mipi_dphy_timing_init(inno);
617
-
618
-	inno_mipi_dphy_lane_enable(inno);
441
+	/* Enable all lanes on analog part */
442
+	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
443
+			LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
444
+			LANE_EN_1 | LANE_EN_0);
619445 }
620446 
621447 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
....@@ -630,16 +456,6 @@
630456 			SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
631457 			SAMPLE_CLOCK_DIRECTION_REVERSE |
632458 			PLL_OUTPUT_FREQUENCY_DIV_BY_1);
633
-
634
-	/* Reset LVDS digital logic */
635
-	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
636
-			LVDS_DIGITAL_INTERNAL_RESET_MASK,
637
-			LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
638
-	udelay(1);
639
-	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
640
-			LVDS_DIGITAL_INTERNAL_RESET_MASK,
641
-			LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
642
-
643459 	/* Select LVDS mode */
644460 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
645461 			MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
....@@ -664,6 +480,14 @@
664480 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
665481 			PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
666482 
483
+	/* Reset LVDS digital logic */
484
+	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
485
+			LVDS_DIGITAL_INTERNAL_RESET_MASK,
486
+			LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
487
+	udelay(1);
488
+	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
489
+			LVDS_DIGITAL_INTERNAL_RESET_MASK,
490
+			LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
667491 	/* Enable LVDS digital logic */
668492 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
669493 			LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
....@@ -677,6 +501,9 @@
677501 
678502 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
679503 {
504
+	/* Select TTL mode */
505
+	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
506
+			MODE_ENABLE_MASK, TTL_MODE_ENABLE);
680507 	/* Reset digital logic */
681508 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
682509 			LVDS_DIGITAL_INTERNAL_RESET_MASK,
....@@ -685,10 +512,6 @@
685512 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
686513 			LVDS_DIGITAL_INTERNAL_RESET_MASK,
687514 			LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
688
-
689
-	/* Select TTL mode */
690
-	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
691
-			MODE_ENABLE_MASK, TTL_MODE_ENABLE);
692515 	/* Enable digital logic */
693516 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
694517 			LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
....@@ -705,6 +528,7 @@
705528 static int inno_video_phy_power_on(struct phy *phy)
706529 {
707530 	struct inno_video_phy *inno = phy_get_drvdata(phy);
531
+	enum phy_mode mode = phy_get_mode(phy);
708532 
709533 	clk_prepare_enable(inno->pclk_host);
710534 	clk_prepare_enable(inno->pclk_phy);
....@@ -717,18 +541,16 @@
717541 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
718542 			POWER_WORK_MASK, POWER_WORK_ENABLE);
719543 
720
-	switch (inno->mode) {
721
-	case PHY_MODE_VIDEO_MIPI:
544
+	switch (mode) {
545
+	case PHY_MODE_MIPI_DPHY:
722546 		inno_video_phy_mipi_mode_enable(inno);
723547 		break;
724
-	case PHY_MODE_VIDEO_LVDS:
548
+	case PHY_MODE_LVDS:
725549 		inno_video_phy_lvds_mode_enable(inno);
726550 		break;
727
-	case PHY_MODE_VIDEO_TTL:
551
+	default:
728552 		inno_video_phy_ttl_mode_enable(inno);
729553 		break;
730
-	default:
731
-		return -EINVAL;
732554 	}
733555 
734556 	return 0;
....@@ -764,18 +586,6 @@
764586 
765587 static int inno_video_phy_set_mode(struct phy *phy, enum phy_mode mode)
766588 {
767
-	struct inno_video_phy *inno = phy_get_drvdata(phy);
768
-
769
-	switch (mode) {
770
-	case PHY_MODE_VIDEO_MIPI:
771
-	case PHY_MODE_VIDEO_LVDS:
772
-	case PHY_MODE_VIDEO_TTL:
773
-		inno->mode = mode;
774
-		break;
775
-	default:
776
-		return -EINVAL;
777
-	}
778
-
779589 	return 0;
780590 }
781591 
....@@ -941,48 +751,6 @@
941751 	of_clk_del_provider(dev->of_node);
942752 }
943753 
944
-static const struct regmap_config inno_video_phy_regmap_config = {
945
-	.reg_bits = 32,
946
-	.val_bits = 32,
947
-	.reg_stride = 4,
948
-	.max_register = 0x3ac,
949
-};
950
-
951
-static const struct inno_video_phy_plat_data px30_video_phy_plat_data = {
952
-	.soc_type = PX30,
953
-	.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
954
-	.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
955
-	.max_rate = MAX_1GHZ,
956
-};
957
-
958
-static const struct inno_video_phy_plat_data px30s_video_phy_plat_data = {
959
-	.soc_type = PX30S,
960
-	.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
961
-	.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
962
-	.max_rate = MAX_2_5GHZ,
963
-};
964
-
965
-static const struct inno_video_phy_plat_data rk3128_video_phy_plat_data = {
966
-	.soc_type = RK3128,
967
-	.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
968
-	.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
969
-	.max_rate = MAX_1GHZ,
970
-};
971
-
972
-static const struct inno_video_phy_plat_data rk3368_video_phy_plat_data = {
973
-	.soc_type = RK3368,
974
-	.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
975
-	.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
976
-	.max_rate = MAX_1GHZ,
977
-};
978
-
979
-static const struct inno_video_phy_plat_data rk3568_video_phy_plat_data = {
980
-	.soc_type = RK3568,
981
-	.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
982
-	.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
983
-	.max_rate = MAX_2_5GHZ,
984
-};
985
-
986754 static int inno_video_phy_probe(struct platform_device *pdev)
987755 {
988756 	struct device *dev = &pdev->dev;
....@@ -990,7 +758,6 @@
990758 	struct phy_provider *phy_provider;
991759 	struct phy *phy;
992760 	struct resource *res;
993
-	void __iomem *regs;
994761 	int ret;
995762 
996763 	inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
....@@ -998,10 +765,6 @@
998765 		return -ENOMEM;
999766 
1000767 	inno->dev = dev;
1001
-	inno->pdata = of_device_get_match_data(inno->dev);
1002
-	if (soc_is_px30s())
1003
-		inno->pdata = &px30s_video_phy_plat_data;
1004
-
1005768 	platform_set_drvdata(pdev, inno);
1006769 
1007770 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
....@@ -1010,17 +773,9 @@
1010773 		return -EINVAL;
1011774 	}
1012775 
1013
-	regs = devm_ioremap_resource(dev, res);
1014
-	if (IS_ERR(regs))
1015
-		return PTR_ERR(regs);
1016
-
1017
-	inno->regmap = devm_regmap_init_mmio(dev, regs,
1018
-					     &inno_video_phy_regmap_config);
1019
-	if (IS_ERR(inno->regmap)) {
1020
-		ret = PTR_ERR(inno->regmap);
1021
-		dev_err(dev, "failed to init regmap: %d\n", ret);
1022
-		return ret;
1023
-	}
776
+	inno->phy_base = devm_ioremap(dev, res->start, resource_size(res));
777
+	if (!inno->phy_base)
778
+		return -ENOMEM;
1024779 
1025780 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1026781 	if (!res) {
....@@ -1067,9 +822,6 @@
1067822 		return ret;
1068823 	}
1069824 
1070
-	if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes))
1071
-		inno->lanes = 4;
1072
-
1073825 	phy_set_drvdata(phy, inno);
1074826 
1075827 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
....@@ -1099,22 +851,10 @@
1099851 }
1100852 
1101853 static const struct of_device_id inno_video_phy_of_match[] = {
1102
-	{
1103
-		.compatible = "rockchip,px30-video-phy",
1104
-		.data = &px30_video_phy_plat_data,
1105
-	}, {
1106
-		.compatible = "rockchip,px30s-video-phy",
1107
-		.data = &px30s_video_phy_plat_data,
1108
-	}, {
1109
-		.compatible = "rockchip,rk3128-video-phy",
1110
-		.data = &rk3128_video_phy_plat_data,
1111
-	}, {
1112
-		.compatible = "rockchip,rk3368-video-phy",
1113
-		.data = &rk3368_video_phy_plat_data,
1114
-	}, {
1115
-		.compatible = "rockchip,rk3568-video-phy",
1116
-		.data = &rk3568_video_phy_plat_data,
1117
-	},
854
+	{ .compatible = "rockchip,px30-video-phy", },
855
+	{ .compatible = "rockchip,rk3128-video-phy", },
856
+	{ .compatible = "rockchip,rk3368-video-phy", },
857
+	{ .compatible = "rockchip,rk3568-video-phy", },
1118858 	{}
1119859 };
1120860 MODULE_DEVICE_TABLE(of, inno_video_phy_of_match);