hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/phy/rockchip/phy-rockchip-inno-combphy.c
....@@ -14,6 +14,7 @@
1414 #include <linux/module.h>
1515 #include <linux/of_device.h>
1616 #include <linux/phy/phy.h>
17
+#include <linux/phy/pcie.h>
1718 #include <linux/regmap.h>
1819 #include <linux/reset.h>
1920 #include <dt-bindings/phy/phy.h>
....@@ -545,7 +546,7 @@
545546 return 0;
546547 }
547548
548
-static int rockchip_combphy_set_mode(struct phy *phy, enum phy_mode mode)
549
+static int rockchip_combphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
549550 {
550551 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
551552 u32 reg;
....@@ -555,9 +556,9 @@
555556
556557 reg = readl(priv->mmio + 0x21a8);
557558
558
- if (PHY_MODE_PCIE_EP == mode)
559
+ if (PHY_MODE_PCIE_EP == submode)
559560 reg |= (0x1 << 2);
560
- else if (PHY_MODE_PCIE_RC == mode)
561
+ else if (PHY_MODE_PCIE_RC == submode)
561562 reg &= ~(0x1 << 2);
562563 else
563564 return -EINVAL;