add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/phy/qualcomm/Kconfig
..
..
@@ -1,3 +1,4 @@
1
+# SPDX-License-Identifier: GPL-2.0-only
1
2
 #
2
3
 # Phy drivers for Qualcomm and Atheros platforms
3
4
 #
..
..
@@ -17,12 +18,27 @@
17
18
 	depends on OF
18
19
 	select GENERIC_PHY
19
20
 
21
+config PHY_QCOM_IPQ4019_USB
22
+	tristate "Qualcomm IPQ4019 USB PHY driver"
23
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
24
+	select GENERIC_PHY
25
+	help
26
+	  Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
27
+
20
28
 config PHY_QCOM_IPQ806X_SATA
21
29
 	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
22
30
 	depends on ARCH_QCOM
23
31
 	depends on HAS_IOMEM
24
32
 	depends on OF
25
33
 	select GENERIC_PHY
34
+
35
+config PHY_QCOM_PCIE2
36
+	tristate "Qualcomm PCIe Gen2 PHY Driver"
37
+	depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
38
+	select GENERIC_PHY
39
+	help
40
+	  Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
41
+	  based PCIe controller.
26
42
 
27
43
 config PHY_QCOM_QMP
28
44
 	tristate "Qualcomm QMP PHY Driver"
..
..
@@ -43,13 +59,6 @@
43
59
 	  PHY which is usually paired with either the ChipIdea or Synopsys DWC3
44
60
 	  USB IPs on MSM SOCs.
45
61
 
46
-config PHY_QCOM_UFS
47
-	tristate "Qualcomm UFS PHY driver"
48
-	depends on OF && ARCH_QCOM
49
-	select GENERIC_PHY
50
-	help
51
-	  Support for UFS PHY on QCOM chipsets.
52
-
53
62
 config PHY_QCOM_USB_HS
54
63
 	tristate "Qualcomm USB HS PHY module"
55
64
 	depends on USB_ULPI_BUS
..
..
@@ -59,9 +68,49 @@
59
68
 	  Support for the USB high-speed ULPI compliant phy on Qualcomm
60
69
 	  chipsets.
61
70
 
71
+config PHY_QCOM_USB_SNPS_FEMTO_V2
72
+	tristate "Qualcomm SNPS FEMTO USB HS PHY V2 module"
73
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
74
+	select GENERIC_PHY
75
+	help
76
+	  Enable support for the USB high-speed SNPS Femto phy on Qualcomm
77
+	  chipsets.  This PHY has differences in the register map compared
78
+	  to the V1 variants.  The PHY is paired with a Synopsys DWC3 USB
79
+	  controller on Qualcomm SOCs.
80
+
62
81
 config PHY_QCOM_USB_HSIC
63
82
 	tristate "Qualcomm USB HSIC ULPI PHY module"
64
83
 	depends on USB_ULPI_BUS
65
84
 	select GENERIC_PHY
66
85
 	help
67
86
 	  Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
87
+
88
+config PHY_QCOM_USB_HS_28NM
89
+	tristate "Qualcomm 28nm High-Speed PHY"
90
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
91
+	depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
92
+	select GENERIC_PHY
93
+	help
94
+	  Enable this to support the Qualcomm Synopsys DesignWare Core 28nm
95
+	  High-Speed PHY driver. This driver supports the Hi-Speed PHY which
96
+	  is usually paired with either the ChipIdea or Synopsys DWC3 USB
97
+	  IPs on MSM SOCs.
98
+
99
+config PHY_QCOM_USB_SS
100
+	tristate "Qualcomm USB Super-Speed PHY driver"
101
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
102
+	depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
103
+	select GENERIC_PHY
104
+	help
105
+	  Enable this to support the Super-Speed USB transceiver on various
106
+	  Qualcomm chipsets.
107
+
108
+config PHY_QCOM_IPQ806X_USB
109
+	tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
110
+	depends on HAS_IOMEM
111
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
112
+	select GENERIC_PHY
113
+	help
114
+	  This option enables support for the Synopsis PHYs present inside the
115
+	  Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
116
+	  both HS and SS PHY controllers.