add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/phy/marvell/phy-pxa-28nm-usb2.c
..
..
@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * Copyright (C) 2015 Linaro, Ltd.
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  * Rob Herring <robh@kernel.org>
..
..
@@ -5,16 +6,6 @@
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  * Based on vendor driver:
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  * Copyright (C) 2013 Marvell Inc.
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  * Author: Chao Xie <xiechao.mail@gmail.com>
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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9
  */
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10
 
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11
 #include <linux/delay.h>
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..
@@ -22,6 +13,7 @@
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13
 #include <linux/of.h>
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14
 #include <linux/of_device.h>
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15
 #include <linux/io.h>
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+#include <linux/iopoll.h>
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 #include <linux/err.h>
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 #include <linux/clk.h>
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 #include <linux/module.h>
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..
@@ -147,15 +139,12 @@
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 	struct clk		*clk;
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 };
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141
 
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-static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
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+static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
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 {
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-	timeout += jiffies;
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-	while (time_is_after_eq_jiffies(timeout)) {
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-		if ((readl(reg) & mask) == mask)
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-			return true;
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-		msleep(1);
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-	}
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-	return false;
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+	u32 val;
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+
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+	return readl_poll_timeout(reg, val, ((val & mask) == mask),
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+				   1000, 1000 * ms);
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148
 }
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149
 
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 static int mv_usb2_phy_28nm_init(struct phy *phy)
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@@ -217,24 +206,23 @@
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 	 */
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207
 
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 	/* Make sure PHY Calibration is ready */
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-	if (!wait_for_reg(base + PHY_28NM_CAL_REG,
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-	    PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
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-	    HZ / 10)) {
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+	ret = wait_for_reg(base + PHY_28NM_CAL_REG,
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+			   PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
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+			   100);
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+	if (ret) {
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 		dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");
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-		ret = -ETIMEDOUT;
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214
 		goto err_clk;
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215
 	}
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-	if (!wait_for_reg(base + PHY_28NM_RX_REG1,
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-	    PHY_28NM_RX_SQCAL_DONE, HZ / 10)) {
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+	ret = wait_for_reg(base + PHY_28NM_RX_REG1,
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+			   PHY_28NM_RX_SQCAL_DONE, 100);
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+	if (ret) {
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 		dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");
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-		ret = -ETIMEDOUT;
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220
 		goto err_clk;
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221
 	}
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 	/* Make sure PHY PLL is ready */
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-	if (!wait_for_reg(base + PHY_28NM_PLL_REG0,
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-	    PHY_28NM_PLL_READY, HZ / 10)) {
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+	ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);
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+	if (ret) {
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 		dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");
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-		ret = -ETIMEDOUT;
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 		goto err_clk;
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 	}
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