add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/phy/marvell/phy-pxa-28nm-hsic.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2015 Linaro, Ltd.
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  * Rob Herring <robh@kernel.org>
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@@ -5,22 +6,13 @@
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  * Based on vendor driver:
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  * Copyright (C) 2013 Marvell Inc.
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  * Author: Chao Xie <xiechao.mail@gmail.com>
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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  */
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10
 
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 #include <linux/delay.h>
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 #include <linux/slab.h>
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 #include <linux/of.h>
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 #include <linux/io.h>
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+#include <linux/iopoll.h>
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 #include <linux/err.h>
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 #include <linux/clk.h>
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 #include <linux/module.h>
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@@ -53,15 +45,12 @@
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 	struct clk		*clk;
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 };
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47
 
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-static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
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+static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
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 {
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-	timeout += jiffies;
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-	while (time_is_after_eq_jiffies(timeout)) {
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-		if ((readl(reg) & mask) == mask)
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-			return true;
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-		msleep(1);
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-	}
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-	return false;
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+	u32 val;
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+
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+	return readl_poll_timeout(reg, val, ((val & mask) == mask),
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+				  1000, 1000 * ms);
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 }
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55
 
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 static int mv_hsic_phy_init(struct phy *phy)
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@@ -69,6 +58,7 @@
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 	struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
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 	struct platform_device *pdev = mv_phy->pdev;
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 	void __iomem *base = mv_phy->base;
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+	int ret;
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62
 
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 	clk_prepare_enable(mv_phy->clk);
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64
 
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@@ -84,14 +74,14 @@
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 		base + PHY_28NM_HSIC_PLL_CTRL2);
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 	/* Make sure PHY PLL is locked */
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-	if (!wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
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-	    PHY_28NM_HSIC_H2S_PLL_LOCK, HZ / 10)) {
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+	ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
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+			   PHY_28NM_HSIC_H2S_PLL_LOCK, 100);
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+	if (ret) {
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 		dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS.");
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 		clk_disable_unprepare(mv_phy->clk);
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-		return -ETIMEDOUT;
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 	}
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-	return 0;
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+	return ret;
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 }
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86
 
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 static int mv_hsic_phy_power_on(struct phy *phy)
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@@ -100,6 +90,7 @@
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 	struct platform_device *pdev = mv_phy->pdev;
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 	void __iomem *base = mv_phy->base;
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 	u32 reg;
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+	int ret;
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 	reg = readl(base + PHY_28NM_HSIC_CTRL);
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 	/* Avoid SE0 state when resume for some device will take it as reset */
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@@ -117,20 +108,20 @@
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 	 */
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 	/* Make sure PHY Calibration is ready */
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-	if (!wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
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-	    PHY_28NM_HSIC_H2S_IMPCAL_DONE, HZ / 10)) {
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+	ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
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+			   PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100);
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+	if (ret) {
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 		dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS.");
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-		return -ETIMEDOUT;
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+		return ret;
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 	}
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 	/* Waiting for HSIC connect int*/
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-	if (!wait_for_reg(base + PHY_28NM_HSIC_INT,
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-	    PHY_28NM_HSIC_CONNECT_INT, HZ / 5)) {
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+	ret = wait_for_reg(base + PHY_28NM_HSIC_INT,
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+			   PHY_28NM_HSIC_CONNECT_INT, 200);
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+	if (ret)
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 		dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout.");
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-		return -ETIMEDOUT;
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-	}
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-	return 0;
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+	return ret;
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 }
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 static int mv_hsic_phy_power_off(struct phy *phy)