.. | .. |
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5 | 5 | * Antoine Tenart <antoine.tenart@free-electrons.com> |
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6 | 6 | */ |
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7 | 7 | |
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| 8 | +#include <linux/arm-smccc.h> |
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| 9 | +#include <linux/clk.h> |
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8 | 10 | #include <linux/io.h> |
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9 | 11 | #include <linux/iopoll.h> |
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10 | 12 | #include <linux/mfd/syscon.h> |
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11 | 13 | #include <linux/module.h> |
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| 14 | +#include <linux/phy.h> |
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12 | 15 | #include <linux/phy/phy.h> |
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13 | 16 | #include <linux/platform_device.h> |
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14 | 17 | #include <linux/regmap.h> |
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.. | .. |
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21 | 24 | #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11) |
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22 | 25 | #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12) |
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23 | 26 | #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14) |
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| 27 | +#define MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE BIT(15) |
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24 | 28 | #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000) |
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25 | 29 | #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3) |
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26 | 30 | #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4) |
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.. | .. |
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76 | 80 | #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000) |
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77 | 81 | #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5) |
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78 | 82 | #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10) |
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79 | | -#define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000) |
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80 | | -#define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2) |
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| 83 | +#define MVEBU_COMPHY_DTL_CTRL(n) (0x984 + (n) * 0x1000) |
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| 84 | +#define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2) |
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81 | 85 | #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000) |
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82 | 86 | #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7) |
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83 | 87 | #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000) |
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.. | .. |
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110 | 114 | #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4) |
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111 | 115 | #define MVEBU_COMPHY_PIPE_SELECTOR 0x1144 |
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112 | 116 | #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4) |
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| 117 | +#define MVEBU_COMPHY_SD1_CTRL1 0x1148 |
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| 118 | +#define MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN BIT(26) |
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| 119 | +#define MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN BIT(27) |
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113 | 120 | |
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114 | 121 | #define MVEBU_COMPHY_LANES 6 |
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115 | 122 | #define MVEBU_COMPHY_PORTS 3 |
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116 | 123 | |
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117 | | -struct mvebu_comhy_conf { |
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| 124 | +#define COMPHY_SIP_POWER_ON 0x82000001 |
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| 125 | +#define COMPHY_SIP_POWER_OFF 0x82000002 |
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| 126 | + |
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| 127 | +/* |
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| 128 | + * A lane is described by the following bitfields: |
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| 129 | + * [ 1- 0]: COMPHY polarity invertion |
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| 130 | + * [ 2- 7]: COMPHY speed |
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| 131 | + * [ 5-11]: COMPHY port index |
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| 132 | + * [12-16]: COMPHY mode |
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| 133 | + * [17]: Clock source |
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| 134 | + * [18-20]: PCIe width (x1, x2, x4) |
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| 135 | + */ |
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| 136 | +#define COMPHY_FW_POL_OFFSET 0 |
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| 137 | +#define COMPHY_FW_POL_MASK GENMASK(1, 0) |
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| 138 | +#define COMPHY_FW_SPEED_OFFSET 2 |
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| 139 | +#define COMPHY_FW_SPEED_MASK GENMASK(7, 2) |
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| 140 | +#define COMPHY_FW_SPEED_MAX COMPHY_FW_SPEED_MASK |
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| 141 | +#define COMPHY_FW_SPEED_1250 0 |
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| 142 | +#define COMPHY_FW_SPEED_3125 2 |
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| 143 | +#define COMPHY_FW_SPEED_5000 3 |
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| 144 | +#define COMPHY_FW_SPEED_103125 6 |
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| 145 | +#define COMPHY_FW_PORT_OFFSET 8 |
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| 146 | +#define COMPHY_FW_PORT_MASK GENMASK(11, 8) |
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| 147 | +#define COMPHY_FW_MODE_OFFSET 12 |
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| 148 | +#define COMPHY_FW_MODE_MASK GENMASK(16, 12) |
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| 149 | +#define COMPHY_FW_WIDTH_OFFSET 18 |
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| 150 | +#define COMPHY_FW_WIDTH_MASK GENMASK(20, 18) |
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| 151 | + |
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| 152 | +#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol, width) \ |
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| 153 | + ((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \ |
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| 154 | + (((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \ |
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| 155 | + (((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \ |
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| 156 | + (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK) | \ |
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| 157 | + (((width) << COMPHY_FW_WIDTH_OFFSET) & COMPHY_FW_WIDTH_MASK)) |
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| 158 | + |
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| 159 | +#define COMPHY_FW_PARAM(mode, port) \ |
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| 160 | + COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_MAX, 0, 0) |
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| 161 | + |
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| 162 | +#define COMPHY_FW_PARAM_ETH(mode, port, speed) \ |
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| 163 | + COMPHY_FW_PARAM_FULL(mode, port, speed, 0, 0) |
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| 164 | + |
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| 165 | +#define COMPHY_FW_PARAM_PCIE(mode, port, width) \ |
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| 166 | + COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_5000, 0, width) |
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| 167 | + |
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| 168 | +#define COMPHY_FW_MODE_SATA 0x1 |
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| 169 | +#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */ |
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| 170 | +#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */ |
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| 171 | +#define COMPHY_FW_MODE_USB3H 0x4 |
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| 172 | +#define COMPHY_FW_MODE_USB3D 0x5 |
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| 173 | +#define COMPHY_FW_MODE_PCIE 0x6 |
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| 174 | +#define COMPHY_FW_MODE_RXAUI 0x7 |
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| 175 | +#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */ |
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| 176 | + |
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| 177 | +struct mvebu_comphy_conf { |
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118 | 178 | enum phy_mode mode; |
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| 179 | + int submode; |
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119 | 180 | unsigned lane; |
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120 | 181 | unsigned port; |
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121 | 182 | u32 mux; |
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| 183 | + u32 fw_mode; |
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122 | 184 | }; |
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123 | 185 | |
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124 | | -#define MVEBU_COMPHY_CONF(_lane, _port, _mode, _mux) \ |
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| 186 | +#define ETH_CONF(_lane, _port, _submode, _mux, _fw) \ |
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| 187 | + { \ |
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| 188 | + .lane = _lane, \ |
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| 189 | + .port = _port, \ |
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| 190 | + .mode = PHY_MODE_ETHERNET, \ |
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| 191 | + .submode = _submode, \ |
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| 192 | + .mux = _mux, \ |
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| 193 | + .fw_mode = _fw, \ |
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| 194 | + } |
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| 195 | + |
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| 196 | +#define GEN_CONF(_lane, _port, _mode, _fw) \ |
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125 | 197 | { \ |
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126 | 198 | .lane = _lane, \ |
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127 | 199 | .port = _port, \ |
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128 | 200 | .mode = _mode, \ |
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129 | | - .mux = _mux, \ |
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| 201 | + .submode = PHY_INTERFACE_MODE_NA, \ |
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| 202 | + .mux = -1, \ |
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| 203 | + .fw_mode = _fw, \ |
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130 | 204 | } |
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131 | 205 | |
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132 | | -static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = { |
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| 206 | +static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { |
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133 | 207 | /* lane 0 */ |
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134 | | - MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1), |
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135 | | - MVEBU_COMPHY_CONF(0, 1, PHY_MODE_2500SGMII, 0x1), |
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| 208 | + GEN_CONF(0, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), |
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| 209 | + ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), |
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| 210 | + ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII), |
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| 211 | + GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), |
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136 | 212 | /* lane 1 */ |
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137 | | - MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1), |
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138 | | - MVEBU_COMPHY_CONF(1, 2, PHY_MODE_2500SGMII, 0x1), |
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| 213 | + GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), |
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| 214 | + GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D), |
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| 215 | + GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), |
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| 216 | + GEN_CONF(1, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), |
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| 217 | + ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), |
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| 218 | + ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII), |
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139 | 219 | /* lane 2 */ |
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140 | | - MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1), |
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141 | | - MVEBU_COMPHY_CONF(2, 0, PHY_MODE_2500SGMII, 0x1), |
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142 | | - MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1), |
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| 220 | + ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), |
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| 221 | + ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII), |
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| 222 | + ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI), |
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| 223 | + ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI), |
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| 224 | + GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), |
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| 225 | + GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), |
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| 226 | + GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), |
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143 | 227 | /* lane 3 */ |
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144 | | - MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2), |
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145 | | - MVEBU_COMPHY_CONF(3, 1, PHY_MODE_2500SGMII, 0x2), |
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| 228 | + GEN_CONF(3, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), |
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| 229 | + ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII), |
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| 230 | + ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII), |
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| 231 | + ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI), |
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| 232 | + GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), |
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| 233 | + GEN_CONF(3, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), |
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146 | 234 | /* lane 4 */ |
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147 | | - MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2), |
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148 | | - MVEBU_COMPHY_CONF(4, 0, PHY_MODE_2500SGMII, 0x2), |
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149 | | - MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2), |
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150 | | - MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1), |
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| 235 | + ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII), |
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| 236 | + ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII), |
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| 237 | + ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI), |
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| 238 | + ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI), |
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| 239 | + GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D), |
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| 240 | + GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), |
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| 241 | + GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), |
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| 242 | + ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), |
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| 243 | + ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII), |
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| 244 | + ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI), |
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151 | 245 | /* lane 5 */ |
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152 | | - MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1), |
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153 | | - MVEBU_COMPHY_CONF(5, 2, PHY_MODE_2500SGMII, 0x1), |
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| 246 | + ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI), |
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| 247 | + GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), |
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| 248 | + ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), |
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| 249 | + ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII), |
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| 250 | + GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), |
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154 | 251 | }; |
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155 | 252 | |
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156 | 253 | struct mvebu_comphy_priv { |
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157 | 254 | void __iomem *base; |
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158 | 255 | struct regmap *regmap; |
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159 | 256 | struct device *dev; |
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| 257 | + struct clk *mg_domain_clk; |
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| 258 | + struct clk *mg_core_clk; |
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| 259 | + struct clk *axi_clk; |
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| 260 | + unsigned long cp_phys; |
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160 | 261 | }; |
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161 | 262 | |
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162 | 263 | struct mvebu_comphy_lane { |
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163 | 264 | struct mvebu_comphy_priv *priv; |
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164 | 265 | unsigned id; |
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165 | 266 | enum phy_mode mode; |
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| 267 | + int submode; |
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166 | 268 | int port; |
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167 | 269 | }; |
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168 | 270 | |
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169 | | -static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) |
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| 271 | +static int mvebu_comphy_smc(unsigned long function, unsigned long phys, |
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| 272 | + unsigned long lane, unsigned long mode) |
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| 273 | +{ |
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| 274 | + struct arm_smccc_res res; |
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| 275 | + s32 ret; |
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| 276 | + |
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| 277 | + arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); |
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| 278 | + ret = res.a0; |
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| 279 | + |
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| 280 | + switch (ret) { |
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| 281 | + case SMCCC_RET_SUCCESS: |
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| 282 | + return 0; |
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| 283 | + case SMCCC_RET_NOT_SUPPORTED: |
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| 284 | + return -EOPNOTSUPP; |
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| 285 | + default: |
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| 286 | + return -EINVAL; |
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| 287 | + } |
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| 288 | +} |
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| 289 | + |
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| 290 | +static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, |
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| 291 | + enum phy_mode mode, int submode) |
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170 | 292 | { |
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171 | 293 | int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes); |
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| 294 | + /* Ignore PCIe submode: it represents the width */ |
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| 295 | + bool ignore_submode = (mode == PHY_MODE_PCIE); |
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| 296 | + const struct mvebu_comphy_conf *conf; |
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172 | 297 | |
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173 | 298 | /* Unused PHY mux value is 0x0 */ |
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174 | 299 | if (mode == PHY_MODE_INVALID) |
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175 | 300 | return 0; |
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176 | 301 | |
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177 | 302 | for (i = 0; i < n; i++) { |
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178 | | - if (mvebu_comphy_cp110_modes[i].lane == lane && |
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179 | | - mvebu_comphy_cp110_modes[i].port == port && |
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180 | | - mvebu_comphy_cp110_modes[i].mode == mode) |
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| 303 | + conf = &mvebu_comphy_cp110_modes[i]; |
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| 304 | + if (conf->lane == lane && |
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| 305 | + conf->port == port && |
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| 306 | + conf->mode == mode && |
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| 307 | + (conf->submode == submode || ignore_submode)) |
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181 | 308 | break; |
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182 | 309 | } |
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183 | 310 | |
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184 | 311 | if (i == n) |
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185 | 312 | return -EINVAL; |
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186 | 313 | |
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187 | | - return mvebu_comphy_cp110_modes[i].mux; |
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| 314 | + if (fw_mode) |
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| 315 | + return conf->fw_mode; |
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| 316 | + else |
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| 317 | + return conf->mux; |
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188 | 318 | } |
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189 | 319 | |
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190 | | -static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, |
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191 | | - enum phy_mode mode) |
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| 320 | +static inline int mvebu_comphy_get_mux(int lane, int port, |
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| 321 | + enum phy_mode mode, int submode) |
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| 322 | +{ |
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| 323 | + return mvebu_comphy_get_mode(false, lane, port, mode, submode); |
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| 324 | +} |
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| 325 | + |
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| 326 | +static inline int mvebu_comphy_get_fw_mode(int lane, int port, |
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| 327 | + enum phy_mode mode, int submode) |
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| 328 | +{ |
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| 329 | + return mvebu_comphy_get_mode(true, lane, port, mode, submode); |
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| 330 | +} |
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| 331 | + |
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| 332 | +static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane) |
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192 | 333 | { |
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193 | 334 | struct mvebu_comphy_priv *priv = lane->priv; |
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194 | 335 | u32 val; |
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.. | .. |
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205 | 346 | MVEBU_COMPHY_SERDES_CFG0_PU_TX | |
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206 | 347 | MVEBU_COMPHY_SERDES_CFG0_HALF_BUS | |
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207 | 348 | MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) | |
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208 | | - MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf)); |
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209 | | - if (mode == PHY_MODE_10GKR) |
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| 349 | + MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf) | |
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| 350 | + MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE); |
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| 351 | + |
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| 352 | + switch (lane->submode) { |
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| 353 | + case PHY_INTERFACE_MODE_10GBASER: |
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210 | 354 | val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | |
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211 | 355 | MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); |
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212 | | - else if (mode == PHY_MODE_2500SGMII) |
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| 356 | + break; |
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| 357 | + case PHY_INTERFACE_MODE_RXAUI: |
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| 358 | + val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xb) | |
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| 359 | + MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xb) | |
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| 360 | + MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE; |
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| 361 | + break; |
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| 362 | + case PHY_INTERFACE_MODE_2500BASEX: |
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213 | 363 | val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) | |
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214 | 364 | MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) | |
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215 | 365 | MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; |
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216 | | - else if (mode == PHY_MODE_SGMII) |
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| 366 | + break; |
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| 367 | + case PHY_INTERFACE_MODE_SGMII: |
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217 | 368 | val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | |
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218 | 369 | MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) | |
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219 | 370 | MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; |
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| 371 | + break; |
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| 372 | + default: |
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| 373 | + dev_err(priv->dev, |
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| 374 | + "unsupported comphy submode (%d) on lane %d\n", |
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| 375 | + lane->submode, |
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| 376 | + lane->id); |
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| 377 | + return -ENOTSUPP; |
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| 378 | + } |
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| 379 | + |
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220 | 380 | writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); |
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| 381 | + |
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| 382 | + if (lane->submode == PHY_INTERFACE_MODE_RXAUI) { |
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| 383 | + regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val); |
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| 384 | + |
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| 385 | + switch (lane->id) { |
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| 386 | + case 2: |
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| 387 | + case 3: |
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| 388 | + val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN; |
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| 389 | + break; |
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| 390 | + case 4: |
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| 391 | + case 5: |
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| 392 | + val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN; |
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| 393 | + break; |
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| 394 | + default: |
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| 395 | + dev_err(priv->dev, |
---|
| 396 | + "RXAUI is not supported on comphy lane %d\n", |
---|
| 397 | + lane->id); |
---|
| 398 | + return -EINVAL; |
---|
| 399 | + } |
---|
| 400 | + |
---|
| 401 | + regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val); |
---|
| 402 | + } |
---|
221 | 403 | |
---|
222 | 404 | /* reset */ |
---|
223 | 405 | val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); |
---|
.. | .. |
---|
243 | 425 | /* refclk selection */ |
---|
244 | 426 | val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); |
---|
245 | 427 | val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; |
---|
246 | | - if (mode == PHY_MODE_10GKR) |
---|
| 428 | + if (lane->submode == PHY_INTERFACE_MODE_10GBASER) |
---|
247 | 429 | val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; |
---|
248 | 430 | writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); |
---|
249 | 431 | |
---|
.. | .. |
---|
259 | 441 | val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); |
---|
260 | 442 | val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1); |
---|
261 | 443 | writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); |
---|
| 444 | + |
---|
| 445 | + return 0; |
---|
262 | 446 | } |
---|
263 | 447 | |
---|
264 | | -static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, |
---|
265 | | - enum phy_mode mode) |
---|
| 448 | +static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane) |
---|
266 | 449 | { |
---|
267 | 450 | struct mvebu_comphy_priv *priv = lane->priv; |
---|
268 | 451 | u32 val; |
---|
.. | .. |
---|
303 | 486 | return 0; |
---|
304 | 487 | } |
---|
305 | 488 | |
---|
306 | | -static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode) |
---|
| 489 | +static int mvebu_comphy_set_mode_sgmii(struct phy *phy) |
---|
307 | 490 | { |
---|
308 | 491 | struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
309 | 492 | struct mvebu_comphy_priv *priv = lane->priv; |
---|
310 | 493 | u32 val; |
---|
| 494 | + int err; |
---|
311 | 495 | |
---|
312 | | - mvebu_comphy_ethernet_init_reset(lane, mode); |
---|
| 496 | + err = mvebu_comphy_ethernet_init_reset(lane); |
---|
| 497 | + if (err) |
---|
| 498 | + return err; |
---|
313 | 499 | |
---|
314 | 500 | val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); |
---|
315 | 501 | val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; |
---|
316 | 502 | val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL; |
---|
317 | 503 | writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); |
---|
318 | 504 | |
---|
319 | | - val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); |
---|
320 | | - val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; |
---|
321 | | - writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); |
---|
| 505 | + val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); |
---|
| 506 | + val &= ~MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN; |
---|
| 507 | + writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); |
---|
322 | 508 | |
---|
323 | 509 | regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); |
---|
324 | 510 | val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; |
---|
.. | .. |
---|
330 | 516 | val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); |
---|
331 | 517 | writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); |
---|
332 | 518 | |
---|
333 | | - return mvebu_comphy_init_plls(lane, PHY_MODE_SGMII); |
---|
| 519 | + return mvebu_comphy_init_plls(lane); |
---|
334 | 520 | } |
---|
335 | 521 | |
---|
336 | | -static int mvebu_comphy_set_mode_10gkr(struct phy *phy) |
---|
| 522 | +static int mvebu_comphy_set_mode_rxaui(struct phy *phy) |
---|
337 | 523 | { |
---|
338 | 524 | struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
339 | 525 | struct mvebu_comphy_priv *priv = lane->priv; |
---|
340 | 526 | u32 val; |
---|
| 527 | + int err; |
---|
341 | 528 | |
---|
342 | | - mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_10GKR); |
---|
| 529 | + err = mvebu_comphy_ethernet_init_reset(lane); |
---|
| 530 | + if (err) |
---|
| 531 | + return err; |
---|
343 | 532 | |
---|
344 | 533 | val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); |
---|
345 | 534 | val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | |
---|
346 | 535 | MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; |
---|
347 | 536 | writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); |
---|
348 | 537 | |
---|
349 | | - val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); |
---|
350 | | - val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; |
---|
351 | | - writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); |
---|
| 538 | + val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); |
---|
| 539 | + val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN; |
---|
| 540 | + writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); |
---|
| 541 | + |
---|
| 542 | + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); |
---|
| 543 | + val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN; |
---|
| 544 | + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); |
---|
| 545 | + |
---|
| 546 | + val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); |
---|
| 547 | + val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; |
---|
| 548 | + writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); |
---|
| 549 | + |
---|
| 550 | + val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); |
---|
| 551 | + val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); |
---|
| 552 | + val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xd); |
---|
| 553 | + writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); |
---|
| 554 | + |
---|
| 555 | + val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); |
---|
| 556 | + val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | |
---|
| 557 | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7)); |
---|
| 558 | + val |= MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x1) | |
---|
| 559 | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x1) | |
---|
| 560 | + MVEBU_COMPHY_GEN1_S1_RX_DFE_EN; |
---|
| 561 | + writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); |
---|
| 562 | + |
---|
| 563 | + val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); |
---|
| 564 | + val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); |
---|
| 565 | + writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); |
---|
| 566 | + |
---|
| 567 | + val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); |
---|
| 568 | + val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); |
---|
| 569 | + val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); |
---|
| 570 | + writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); |
---|
| 571 | + |
---|
| 572 | + return mvebu_comphy_init_plls(lane); |
---|
| 573 | +} |
---|
| 574 | + |
---|
| 575 | +static int mvebu_comphy_set_mode_10gbaser(struct phy *phy) |
---|
| 576 | +{ |
---|
| 577 | + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
| 578 | + struct mvebu_comphy_priv *priv = lane->priv; |
---|
| 579 | + u32 val; |
---|
| 580 | + int err; |
---|
| 581 | + |
---|
| 582 | + err = mvebu_comphy_ethernet_init_reset(lane); |
---|
| 583 | + if (err) |
---|
| 584 | + return err; |
---|
| 585 | + |
---|
| 586 | + val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); |
---|
| 587 | + val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | |
---|
| 588 | + MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; |
---|
| 589 | + writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); |
---|
| 590 | + |
---|
| 591 | + val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); |
---|
| 592 | + val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN; |
---|
| 593 | + writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); |
---|
352 | 594 | |
---|
353 | 595 | /* Speed divider */ |
---|
354 | 596 | val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); |
---|
.. | .. |
---|
469 | 711 | val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a); |
---|
470 | 712 | writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); |
---|
471 | 713 | |
---|
472 | | - return mvebu_comphy_init_plls(lane, PHY_MODE_10GKR); |
---|
| 714 | + return mvebu_comphy_init_plls(lane); |
---|
473 | 715 | } |
---|
474 | 716 | |
---|
475 | | -static int mvebu_comphy_power_on(struct phy *phy) |
---|
| 717 | +static int mvebu_comphy_power_on_legacy(struct phy *phy) |
---|
476 | 718 | { |
---|
477 | 719 | struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
478 | 720 | struct mvebu_comphy_priv *priv = lane->priv; |
---|
479 | 721 | int ret, mux; |
---|
480 | 722 | u32 val; |
---|
481 | 723 | |
---|
482 | | - mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode); |
---|
| 724 | + mux = mvebu_comphy_get_mux(lane->id, lane->port, |
---|
| 725 | + lane->mode, lane->submode); |
---|
483 | 726 | if (mux < 0) |
---|
484 | 727 | return -ENOTSUPP; |
---|
485 | 728 | |
---|
.. | .. |
---|
492 | 735 | val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); |
---|
493 | 736 | regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); |
---|
494 | 737 | |
---|
495 | | - switch (lane->mode) { |
---|
496 | | - case PHY_MODE_SGMII: |
---|
497 | | - case PHY_MODE_2500SGMII: |
---|
498 | | - ret = mvebu_comphy_set_mode_sgmii(phy, lane->mode); |
---|
| 738 | + switch (lane->submode) { |
---|
| 739 | + case PHY_INTERFACE_MODE_SGMII: |
---|
| 740 | + case PHY_INTERFACE_MODE_2500BASEX: |
---|
| 741 | + ret = mvebu_comphy_set_mode_sgmii(phy); |
---|
499 | 742 | break; |
---|
500 | | - case PHY_MODE_10GKR: |
---|
501 | | - ret = mvebu_comphy_set_mode_10gkr(phy); |
---|
| 743 | + case PHY_INTERFACE_MODE_RXAUI: |
---|
| 744 | + ret = mvebu_comphy_set_mode_rxaui(phy); |
---|
| 745 | + break; |
---|
| 746 | + case PHY_INTERFACE_MODE_10GBASER: |
---|
| 747 | + ret = mvebu_comphy_set_mode_10gbaser(phy); |
---|
502 | 748 | break; |
---|
503 | 749 | default: |
---|
504 | 750 | return -ENOTSUPP; |
---|
.. | .. |
---|
512 | 758 | return ret; |
---|
513 | 759 | } |
---|
514 | 760 | |
---|
515 | | -static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode) |
---|
| 761 | +static int mvebu_comphy_power_on(struct phy *phy) |
---|
| 762 | +{ |
---|
| 763 | + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
| 764 | + struct mvebu_comphy_priv *priv = lane->priv; |
---|
| 765 | + int fw_mode, fw_speed; |
---|
| 766 | + u32 fw_param = 0; |
---|
| 767 | + int ret; |
---|
| 768 | + |
---|
| 769 | + fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, |
---|
| 770 | + lane->mode, lane->submode); |
---|
| 771 | + if (fw_mode < 0) |
---|
| 772 | + goto try_legacy; |
---|
| 773 | + |
---|
| 774 | + /* Try SMC flow first */ |
---|
| 775 | + switch (lane->mode) { |
---|
| 776 | + case PHY_MODE_ETHERNET: |
---|
| 777 | + switch (lane->submode) { |
---|
| 778 | + case PHY_INTERFACE_MODE_RXAUI: |
---|
| 779 | + dev_dbg(priv->dev, "set lane %d to RXAUI mode\n", |
---|
| 780 | + lane->id); |
---|
| 781 | + fw_speed = 0; |
---|
| 782 | + break; |
---|
| 783 | + case PHY_INTERFACE_MODE_SGMII: |
---|
| 784 | + dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n", |
---|
| 785 | + lane->id); |
---|
| 786 | + fw_speed = COMPHY_FW_SPEED_1250; |
---|
| 787 | + break; |
---|
| 788 | + case PHY_INTERFACE_MODE_2500BASEX: |
---|
| 789 | + dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n", |
---|
| 790 | + lane->id); |
---|
| 791 | + fw_speed = COMPHY_FW_SPEED_3125; |
---|
| 792 | + break; |
---|
| 793 | + case PHY_INTERFACE_MODE_10GBASER: |
---|
| 794 | + dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n", |
---|
| 795 | + lane->id); |
---|
| 796 | + fw_speed = COMPHY_FW_SPEED_103125; |
---|
| 797 | + break; |
---|
| 798 | + default: |
---|
| 799 | + dev_err(priv->dev, "unsupported Ethernet mode (%d)\n", |
---|
| 800 | + lane->submode); |
---|
| 801 | + return -ENOTSUPP; |
---|
| 802 | + } |
---|
| 803 | + fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed); |
---|
| 804 | + break; |
---|
| 805 | + case PHY_MODE_USB_HOST_SS: |
---|
| 806 | + case PHY_MODE_USB_DEVICE_SS: |
---|
| 807 | + dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id); |
---|
| 808 | + fw_param = COMPHY_FW_PARAM(fw_mode, lane->port); |
---|
| 809 | + break; |
---|
| 810 | + case PHY_MODE_SATA: |
---|
| 811 | + dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id); |
---|
| 812 | + fw_param = COMPHY_FW_PARAM(fw_mode, lane->port); |
---|
| 813 | + break; |
---|
| 814 | + case PHY_MODE_PCIE: |
---|
| 815 | + dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id, |
---|
| 816 | + lane->submode); |
---|
| 817 | + fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port, |
---|
| 818 | + lane->submode); |
---|
| 819 | + break; |
---|
| 820 | + default: |
---|
| 821 | + dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode); |
---|
| 822 | + return -ENOTSUPP; |
---|
| 823 | + } |
---|
| 824 | + |
---|
| 825 | + ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id, |
---|
| 826 | + fw_param); |
---|
| 827 | + if (!ret) |
---|
| 828 | + return ret; |
---|
| 829 | + |
---|
| 830 | + if (ret == -EOPNOTSUPP) |
---|
| 831 | + dev_err(priv->dev, |
---|
| 832 | + "unsupported SMC call, try updating your firmware\n"); |
---|
| 833 | + |
---|
| 834 | + dev_warn(priv->dev, |
---|
| 835 | + "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n", |
---|
| 836 | + lane->id, lane->mode, ret); |
---|
| 837 | + |
---|
| 838 | +try_legacy: |
---|
| 839 | + /* Fallback to Linux's implementation */ |
---|
| 840 | + return mvebu_comphy_power_on_legacy(phy); |
---|
| 841 | +} |
---|
| 842 | + |
---|
| 843 | +static int mvebu_comphy_set_mode(struct phy *phy, |
---|
| 844 | + enum phy_mode mode, int submode) |
---|
516 | 845 | { |
---|
517 | 846 | struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
518 | 847 | |
---|
519 | | - if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0) |
---|
| 848 | + if (submode == PHY_INTERFACE_MODE_1000BASEX) |
---|
| 849 | + submode = PHY_INTERFACE_MODE_SGMII; |
---|
| 850 | + |
---|
| 851 | + if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0) |
---|
520 | 852 | return -EINVAL; |
---|
521 | 853 | |
---|
522 | 854 | lane->mode = mode; |
---|
| 855 | + lane->submode = submode; |
---|
| 856 | + |
---|
| 857 | + /* PCIe submode represents the width */ |
---|
| 858 | + if (mode == PHY_MODE_PCIE && !lane->submode) |
---|
| 859 | + lane->submode = 1; |
---|
| 860 | + |
---|
523 | 861 | return 0; |
---|
524 | 862 | } |
---|
525 | 863 | |
---|
526 | | -static int mvebu_comphy_power_off(struct phy *phy) |
---|
| 864 | +static int mvebu_comphy_power_off_legacy(struct phy *phy) |
---|
527 | 865 | { |
---|
528 | 866 | struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
529 | 867 | struct mvebu_comphy_priv *priv = lane->priv; |
---|
.. | .. |
---|
544 | 882 | regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); |
---|
545 | 883 | |
---|
546 | 884 | return 0; |
---|
| 885 | +} |
---|
| 886 | + |
---|
| 887 | +static int mvebu_comphy_power_off(struct phy *phy) |
---|
| 888 | +{ |
---|
| 889 | + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); |
---|
| 890 | + struct mvebu_comphy_priv *priv = lane->priv; |
---|
| 891 | + int ret; |
---|
| 892 | + |
---|
| 893 | + ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys, |
---|
| 894 | + lane->id, 0); |
---|
| 895 | + if (!ret) |
---|
| 896 | + return ret; |
---|
| 897 | + |
---|
| 898 | + /* Fallback to Linux's implementation */ |
---|
| 899 | + return mvebu_comphy_power_off_legacy(phy); |
---|
547 | 900 | } |
---|
548 | 901 | |
---|
549 | 902 | static const struct phy_ops mvebu_comphy_ops = { |
---|
.. | .. |
---|
567 | 920 | return phy; |
---|
568 | 921 | |
---|
569 | 922 | lane = phy_get_drvdata(phy); |
---|
570 | | - if (lane->port >= 0) |
---|
571 | | - return ERR_PTR(-EBUSY); |
---|
572 | 923 | lane->port = args->args[0]; |
---|
573 | 924 | |
---|
574 | 925 | return phy; |
---|
| 926 | +} |
---|
| 927 | + |
---|
| 928 | +static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv) |
---|
| 929 | +{ |
---|
| 930 | + int ret; |
---|
| 931 | + |
---|
| 932 | + priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk"); |
---|
| 933 | + if (IS_ERR(priv->mg_domain_clk)) |
---|
| 934 | + return PTR_ERR(priv->mg_domain_clk); |
---|
| 935 | + |
---|
| 936 | + ret = clk_prepare_enable(priv->mg_domain_clk); |
---|
| 937 | + if (ret < 0) |
---|
| 938 | + return ret; |
---|
| 939 | + |
---|
| 940 | + priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk"); |
---|
| 941 | + if (IS_ERR(priv->mg_core_clk)) { |
---|
| 942 | + ret = PTR_ERR(priv->mg_core_clk); |
---|
| 943 | + goto dis_mg_domain_clk; |
---|
| 944 | + } |
---|
| 945 | + |
---|
| 946 | + ret = clk_prepare_enable(priv->mg_core_clk); |
---|
| 947 | + if (ret < 0) |
---|
| 948 | + goto dis_mg_domain_clk; |
---|
| 949 | + |
---|
| 950 | + priv->axi_clk = devm_clk_get(priv->dev, "axi_clk"); |
---|
| 951 | + if (IS_ERR(priv->axi_clk)) { |
---|
| 952 | + ret = PTR_ERR(priv->axi_clk); |
---|
| 953 | + goto dis_mg_core_clk; |
---|
| 954 | + } |
---|
| 955 | + |
---|
| 956 | + ret = clk_prepare_enable(priv->axi_clk); |
---|
| 957 | + if (ret < 0) |
---|
| 958 | + goto dis_mg_core_clk; |
---|
| 959 | + |
---|
| 960 | + return 0; |
---|
| 961 | + |
---|
| 962 | +dis_mg_core_clk: |
---|
| 963 | + clk_disable_unprepare(priv->mg_core_clk); |
---|
| 964 | + |
---|
| 965 | +dis_mg_domain_clk: |
---|
| 966 | + clk_disable_unprepare(priv->mg_domain_clk); |
---|
| 967 | + |
---|
| 968 | + priv->mg_domain_clk = NULL; |
---|
| 969 | + priv->mg_core_clk = NULL; |
---|
| 970 | + priv->axi_clk = NULL; |
---|
| 971 | + |
---|
| 972 | + return ret; |
---|
| 973 | +}; |
---|
| 974 | + |
---|
| 975 | +static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv *priv) |
---|
| 976 | +{ |
---|
| 977 | + if (priv->axi_clk) |
---|
| 978 | + clk_disable_unprepare(priv->axi_clk); |
---|
| 979 | + |
---|
| 980 | + if (priv->mg_core_clk) |
---|
| 981 | + clk_disable_unprepare(priv->mg_core_clk); |
---|
| 982 | + |
---|
| 983 | + if (priv->mg_domain_clk) |
---|
| 984 | + clk_disable_unprepare(priv->mg_domain_clk); |
---|
575 | 985 | } |
---|
576 | 986 | |
---|
577 | 987 | static int mvebu_comphy_probe(struct platform_device *pdev) |
---|
.. | .. |
---|
580 | 990 | struct phy_provider *provider; |
---|
581 | 991 | struct device_node *child; |
---|
582 | 992 | struct resource *res; |
---|
| 993 | + int ret; |
---|
583 | 994 | |
---|
584 | 995 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
---|
585 | 996 | if (!priv) |
---|
.. | .. |
---|
596 | 1007 | if (IS_ERR(priv->base)) |
---|
597 | 1008 | return PTR_ERR(priv->base); |
---|
598 | 1009 | |
---|
| 1010 | + /* |
---|
| 1011 | + * Ignore error if clocks have not been initialized properly for DT |
---|
| 1012 | + * compatibility reasons. |
---|
| 1013 | + */ |
---|
| 1014 | + ret = mvebu_comphy_init_clks(priv); |
---|
| 1015 | + if (ret) { |
---|
| 1016 | + if (ret == -EPROBE_DEFER) |
---|
| 1017 | + return ret; |
---|
| 1018 | + dev_warn(&pdev->dev, "cannot initialize clocks\n"); |
---|
| 1019 | + } |
---|
| 1020 | + |
---|
| 1021 | + /* |
---|
| 1022 | + * Hack to retrieve a physical offset relative to this CP that will be |
---|
| 1023 | + * given to the firmware |
---|
| 1024 | + */ |
---|
| 1025 | + priv->cp_phys = res->start; |
---|
| 1026 | + |
---|
599 | 1027 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
---|
600 | 1028 | struct mvebu_comphy_lane *lane; |
---|
601 | 1029 | struct phy *phy; |
---|
602 | | - int ret; |
---|
603 | 1030 | u32 val; |
---|
604 | 1031 | |
---|
605 | 1032 | ret = of_property_read_u32(child, "reg", &val); |
---|
.. | .. |
---|
615 | 1042 | } |
---|
616 | 1043 | |
---|
617 | 1044 | lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); |
---|
618 | | - if (!lane) |
---|
619 | | - return -ENOMEM; |
---|
| 1045 | + if (!lane) { |
---|
| 1046 | + of_node_put(child); |
---|
| 1047 | + ret = -ENOMEM; |
---|
| 1048 | + goto disable_clks; |
---|
| 1049 | + } |
---|
620 | 1050 | |
---|
621 | 1051 | phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops); |
---|
622 | | - if (IS_ERR(phy)) |
---|
623 | | - return PTR_ERR(phy); |
---|
| 1052 | + if (IS_ERR(phy)) { |
---|
| 1053 | + of_node_put(child); |
---|
| 1054 | + ret = PTR_ERR(phy); |
---|
| 1055 | + goto disable_clks; |
---|
| 1056 | + } |
---|
624 | 1057 | |
---|
625 | 1058 | lane->priv = priv; |
---|
626 | 1059 | lane->mode = PHY_MODE_INVALID; |
---|
| 1060 | + lane->submode = PHY_INTERFACE_MODE_NA; |
---|
627 | 1061 | lane->id = val; |
---|
628 | 1062 | lane->port = -1; |
---|
629 | 1063 | phy_set_drvdata(phy, lane); |
---|
630 | 1064 | |
---|
631 | 1065 | /* |
---|
632 | | - * Once all modes are supported in this driver we should call |
---|
| 1066 | + * All modes are supported in this driver so we could call |
---|
633 | 1067 | * mvebu_comphy_power_off(phy) here to avoid relying on the |
---|
634 | | - * bootloader/firmware configuration. |
---|
| 1068 | + * bootloader/firmware configuration, but for compatibility |
---|
| 1069 | + * reasons we cannot de-configure the COMPHY without being sure |
---|
| 1070 | + * that the firmware is up-to-date and fully-featured. |
---|
635 | 1071 | */ |
---|
636 | 1072 | } |
---|
637 | 1073 | |
---|
638 | 1074 | dev_set_drvdata(&pdev->dev, priv); |
---|
639 | 1075 | provider = devm_of_phy_provider_register(&pdev->dev, |
---|
640 | 1076 | mvebu_comphy_xlate); |
---|
| 1077 | + |
---|
641 | 1078 | return PTR_ERR_OR_ZERO(provider); |
---|
| 1079 | + |
---|
| 1080 | +disable_clks: |
---|
| 1081 | + mvebu_comphy_disable_unprepare_clks(priv); |
---|
| 1082 | + |
---|
| 1083 | + return ret; |
---|
642 | 1084 | } |
---|
643 | 1085 | |
---|
644 | 1086 | static const struct of_device_id mvebu_comphy_of_match_table[] = { |
---|