.. | .. |
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32 | 32 | |
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33 | 33 | /* register 0x01 */ |
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34 | 34 | #define REF_FREF_SEL_25 BIT(0) |
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35 | | -#define PHY_MODE_SATA (0x0 << 5) |
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| 35 | +#define PHY_BERLIN_MODE_SATA (0x0 << 5) |
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36 | 36 | |
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37 | 37 | /* register 0x02 */ |
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38 | 38 | #define USE_MAX_PLL_RATE BIT(12) |
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.. | .. |
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102 | 102 | |
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103 | 103 | /* set PHY mode and ref freq to 25 MHz */ |
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104 | 104 | phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, |
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105 | | - 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA); |
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| 105 | + 0x00ff, |
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| 106 | + REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA); |
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106 | 107 | |
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107 | 108 | /* set PHY up to 6 Gbps */ |
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108 | 109 | phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, |
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.. | .. |
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231 | 232 | struct phy_berlin_desc *phy_desc; |
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232 | 233 | |
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233 | 234 | if (of_property_read_u32(child, "reg", &phy_id)) { |
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234 | | - dev_err(dev, "missing reg property in node %s\n", |
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235 | | - child->name); |
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| 235 | + dev_err(dev, "missing reg property in node %pOFn\n", |
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| 236 | + child); |
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236 | 237 | ret = -EINVAL; |
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237 | 238 | goto put_child; |
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238 | 239 | } |
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239 | 240 | |
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240 | 241 | if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) { |
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241 | | - dev_err(dev, "invalid reg in node %s\n", child->name); |
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| 242 | + dev_err(dev, "invalid reg in node %pOFn\n", child); |
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242 | 243 | ret = -EINVAL; |
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243 | 244 | goto put_child; |
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244 | 245 | } |
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