hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/parisc/gsc.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23 * Interrupt management for most GSC and related devices.
34 *
....@@ -6,11 +7,6 @@
67 * (c) Copyright 1999 Matthew Wilcox
78 * (c) Copyright 2000 Helge Deller
89 * (c) Copyright 2001 Matthew Wilcox for Hewlett-Packard
9
- *
10
- * This program is free software; you can redistribute it and/or modify
11
- * it under the terms of the GNU General Public License as published by
12
- * the Free Software Foundation; either version 2 of the License, or
13
- * (at your option) any later version.
1410 */
1511
1612 #include <linux/bitops.h>
....@@ -139,10 +135,41 @@
139135 */
140136 }
141137
138
+#ifdef CONFIG_SMP
139
+static int gsc_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
140
+ bool force)
141
+{
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+ struct gsc_asic *gsc_dev = irq_data_get_irq_chip_data(d);
143
+ struct cpumask tmask;
144
+ int cpu_irq;
145
+
146
+ if (!cpumask_and(&tmask, dest, cpu_online_mask))
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+ return -EINVAL;
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+
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+ cpu_irq = cpu_check_affinity(d, &tmask);
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+ if (cpu_irq < 0)
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+ return cpu_irq;
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+
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+ gsc_dev->gsc_irq.txn_addr = txn_affinity_addr(d->irq, cpu_irq);
154
+ gsc_dev->eim = ((u32) gsc_dev->gsc_irq.txn_addr) | gsc_dev->gsc_irq.txn_data;
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+
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+ /* switch IRQ's for devices below LASI/WAX to other CPU */
157
+ gsc_writel(gsc_dev->eim, gsc_dev->hpa + OFFSET_IAR);
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+
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+ irq_data_update_effective_affinity(d, &tmask);
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+
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+ return IRQ_SET_MASK_OK;
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+}
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+#endif
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+
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+
142166 static struct irq_chip gsc_asic_interrupt_type = {
143167 .name = "GSC-ASIC",
144168 .irq_unmask = gsc_asic_unmask_irq,
145169 .irq_mask = gsc_asic_mask_irq,
170
+#ifdef CONFIG_SMP
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+ .irq_set_affinity = gsc_set_affinity_irq,
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+#endif
146173 };
147174
148175 int gsc_assign_irq(struct irq_chip *type, void *data)