forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/ntb/hw/intel/ntb_hw_gen1.c
....@@ -60,6 +60,7 @@
6060 #include "ntb_hw_intel.h"
6161 #include "ntb_hw_gen1.h"
6262 #include "ntb_hw_gen3.h"
63
+#include "ntb_hw_gen4.h"
6364 
6465 #define NTB_NAME	"ntb_hw_intel"
6566 #define NTB_DESC	"Intel(R) PCI-E Non-Transparent Bridge Driver"
....@@ -180,7 +181,7 @@
180181 	return ndev->reg->mw_bar[idx];
181182 }
182183 
183
-static inline int ndev_db_addr(struct intel_ntb_dev *ndev,
184
+void ndev_db_addr(struct intel_ntb_dev *ndev,
184185 			       phys_addr_t *db_addr, resource_size_t *db_size,
185186 			       phys_addr_t reg_addr, unsigned long reg)
186187 {
....@@ -196,8 +197,6 @@
196197 		*db_size = ndev->reg->db_size;
197198 		dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size);
198199 	}
199
-
200
-	return 0;
201200 }
202201 
203202 u64 ndev_db_read(struct intel_ntb_dev *ndev,
....@@ -764,6 +763,8 @@
764763 		return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
765764 	else if (pdev_is_gen3(ndev->ntb.pdev))
766765 		return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
766
+	else if (pdev_is_gen4(ndev->ntb.pdev))
767
+		return ndev_ntb4_debugfs_read(filp, ubuf, count, offp);
767768 
768769 	return -ENXIO;
769770 }
....@@ -1111,13 +1112,28 @@
11111112 				  ndev->self_reg->db_mask);
11121113 }
11131114 
1114
-int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
1115
-			   resource_size_t *db_size)
1115
+static int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
1116
+			   resource_size_t *db_size, u64 *db_data, int db_bit)
11161117 {
1118
+	u64 db_bits;
11171119 	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
11181120 
1119
-	return ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr,
1121
+	if (unlikely(db_bit >= BITS_PER_LONG_LONG))
1122
+		return -EINVAL;
1123
+
1124
+	db_bits = BIT_ULL(db_bit);
1125
+
1126
+	if (unlikely(db_bits & ~ntb_ndev(ntb)->db_valid_mask))
1127
+		return -EINVAL;
1128
+
1129
+	ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr,
11201130 			    ndev->peer_reg->db_bell);
1131
+
1132
+	if (db_data)
1133
+		*db_data = db_bits;
1134
+
1135
+
1136
+	return 0;
11211137 }
11221138 
11231139 static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
....@@ -1189,7 +1205,7 @@
11891205 			       ndev->peer_reg->spad);
11901206 }
11911207 
1192
-static u64 xeon_db_ioread(void __iomem *mmio)
1208
+static u64 xeon_db_ioread(const void __iomem *mmio)
11931209 {
11941210 	return (u64)ioread16(mmio);
11951211 }
....@@ -1770,10 +1786,6 @@
17701786 			goto err_dma_mask;
17711787 		dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
17721788 	}
1773
-	rc = dma_coerce_mask_and_coherent(&ndev->ntb.dev,
1774
-					  dma_get_mask(&pdev->dev));
1775
-	if (rc)
1776
-		goto err_dma_mask;
17771789 
17781790 	ndev->self_mmio = pci_iomap(pdev, 0, 0);
17791791 	if (!ndev->self_mmio) {
....@@ -1845,16 +1857,15 @@
18451857 	int rc, node;
18461858 
18471859 	node = dev_to_node(&pdev->dev);
1860
+	ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1861
+	if (!ndev) {
1862
+		rc = -ENOMEM;
1863
+		goto err_ndev;
1864
+	}
1865
+
1866
+	ndev_init_struct(ndev, pdev);
18481867 
18491868 	if (pdev_is_gen1(pdev)) {
1850
-		ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1851
-		if (!ndev) {
1852
-			rc = -ENOMEM;
1853
-			goto err_ndev;
1854
-		}
1855
-
1856
-		ndev_init_struct(ndev, pdev);
1857
-
18581869 		rc = intel_ntb_init_pci(ndev, pdev);
18591870 		if (rc)
18601871 			goto err_init_pci;
....@@ -1862,17 +1873,8 @@
18621873 		rc = xeon_init_dev(ndev);
18631874 		if (rc)
18641875 			goto err_init_dev;
1865
-
18661876 	} else if (pdev_is_gen3(pdev)) {
1867
-		ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1868
-		if (!ndev) {
1869
-			rc = -ENOMEM;
1870
-			goto err_ndev;
1871
-		}
1872
-
1873
-		ndev_init_struct(ndev, pdev);
18741877 		ndev->ntb.ops = &intel_ntb3_ops;
1875
-
18761878 		rc = intel_ntb_init_pci(ndev, pdev);
18771879 		if (rc)
18781880 			goto err_init_pci;
....@@ -1880,10 +1882,18 @@
18801882 		rc = gen3_init_dev(ndev);
18811883 		if (rc)
18821884 			goto err_init_dev;
1885
+	} else if (pdev_is_gen4(pdev)) {
1886
+		ndev->ntb.ops = &intel_ntb4_ops;
1887
+		rc = intel_ntb_init_pci(ndev, pdev);
1888
+		if (rc)
1889
+			goto err_init_pci;
18831890 
1891
+		rc = gen4_init_dev(ndev);
1892
+		if (rc)
1893
+			goto err_init_dev;
18841894 	} else {
18851895 		rc = -EINVAL;
1886
-		goto err_ndev;
1896
+		goto err_init_pci;
18871897 	}
18881898 
18891899 	ndev_reset_unsafe_flags(ndev);
....@@ -1902,7 +1912,7 @@
19021912 
19031913 err_register:
19041914 	ndev_deinit_debugfs(ndev);
1905
-	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
1915
+	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev))
19061916 		xeon_deinit_dev(ndev);
19071917 err_init_dev:
19081918 	intel_ntb_deinit_pci(ndev);
....@@ -1918,7 +1928,7 @@
19181928 
19191929 	ntb_unregister_device(&ndev->ntb);
19201930 	ndev_deinit_debugfs(ndev);
1921
-	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
1931
+	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev))
19221932 		xeon_deinit_dev(ndev);
19231933 	intel_ntb_deinit_pci(ndev);
19241934 	kfree(ndev);
....@@ -2023,6 +2033,7 @@
20232033 };
20242034 
20252035 static const struct pci_device_id intel_ntb_pci_tbl[] = {
2036
+	/* GEN1 */
20262037 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
20272038 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
20282039 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
....@@ -2038,7 +2049,12 @@
20382049 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
20392050 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
20402051 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_BDX)},
2052
+
2053
+	/* GEN3 */
20412054 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)},
2055
+
2056
+	/* GEN4 */
2057
+	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
20422058 	{0}
20432059 };
20442060 MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);