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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/siutils_priv.h
....@@ -1,15 +1,16 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Include file private to the SOC Interconnect support files.
43  *
5
- * Copyright (C) 1999-2019, Broadcom Corporation
6
- * 
4
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
5
+ *
6
+ * Copyright (C) 1999-2017, Broadcom Corporation
7
+ *
78  *      Unless you and Broadcom execute a separate written software license
89  * agreement governing use of this software, this software is licensed to you
910  * under the terms of the GNU General Public License version 2 (the "GPL"),
1011  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1112  * following added to such license:
12
- * 
13
+ *
1314  *      As a special exception, the copyright holders of this software give you
1415  * permission to link this software with independent modules, and to copy and
1516  * distribute the resulting executable under terms of your choice, provided that
....@@ -17,7 +18,7 @@
1718  * the license of that module.  An independent module is a module which is not
1819  * derived from this software.  The special exception does not apply to any
1920  * modifications of the software.
20
- * 
21
+ *
2122  *      Notwithstanding the above, under no circumstances may you combine this
2223  * software in any way with any other Broadcom software provided under a license
2324  * other than the GPL, without Broadcom's express prior written consent.
....@@ -25,13 +26,27 @@
2526  *
2627  * <<Broadcom-WL-IPTag/Open:>>
2728  *
28
- * $Id: siutils_priv.h 520760 2014-12-15 00:54:16Z $
29
+ * $Id: siutils_priv.h 698933 2017-05-11 06:05:10Z $
2930  */
3031 
3132 #ifndef	_siutils_priv_h_
3233 #define	_siutils_priv_h_
3334 
35
+#if defined(SI_ERROR_ENFORCE)
36
+#define	SI_ERROR(args)	printf args
37
+#else
3438 #define	SI_ERROR(args)
39
+#endif // endif
40
+
41
+#if defined(ENABLE_CORECAPTURE)
42
+
43
+#define	SI_PRINT(args)	osl_wificc_logDebug args
44
+
45
+#else
46
+
47
+#define	SI_PRINT(args)	printf args
48
+
49
+#endif /* ENABLE_CORECAPTURE */
3550 
3651 #define	SI_MSG(args)
3752 
....@@ -39,14 +54,13 @@
3954 #define	SI_VMSG(args)	printf args
4055 #else
4156 #define	SI_VMSG(args)
42
-#endif
57
+#endif // endif
4358 
4459 #define	IS_SIM(chippkg)	((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
4560 
4661 typedef uint32 (*si_intrsoff_t)(void *intr_arg);
4762 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
4863 typedef bool (*si_intrsenabled_t)(void *intr_arg);
49
-
5064 
5165 #define SI_GPIO_MAX		16
5266 
....@@ -58,65 +72,110 @@
5872 	struct gci_gpio_item	*next;
5973 } gci_gpio_item_t;
6074 
75
+#define AI_SLAVE_WRAPPER        0
76
+#define AI_MASTER_WRAPPER       1
77
+
78
+typedef struct axi_wrapper {
79
+	uint32  mfg;
80
+	uint32  cid;
81
+	uint32  rev;
82
+	uint32  wrapper_type;
83
+	uint32  wrapper_addr;
84
+	uint32  wrapper_size;
85
+} axi_wrapper_t;
86
+
87
+#define SI_MAX_AXI_WRAPPERS		32
88
+#define AI_REG_READ_TIMEOUT		300 /* in msec */
89
+
90
+/* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */
91
+/* register at 0x19C doesn't exist, so error is logged at the slave wrapper */
92
+#define BT_CC_SPROM_BADREG_LO   0x18000190
93
+#define BT_CC_SPROM_BADREG_SIZE 4
94
+#define BT_CC_SPROM_BADREG_HI   0
95
+#define BCM4350_BT_AXI_ID	6
96
+#define BCM4345_BT_AXI_ID	6
97
+#define BCM4349_BT_AXI_ID	5
98
+#define BCM4364_BT_AXI_ID	5
99
+
100
+/* for BT logging and memory dump, ignore failed access to BT memory */
101
+#define BCM4347_BT_ADDR_HI	0
102
+#define BCM4347_BT_ADDR_LO	0x19000000	/* BT address space */
103
+#define BCM4347_BT_SIZE		0x01000000	/* BT address space size */
104
+#define BCM4347_UNUSED_AXI_ID	0xffffffff
105
+#define BCM4347_CC_AXI_ID	0
106
+#define BCM4347_PCIE_AXI_ID	1
61107 
62108 typedef struct si_cores_info {
63
-	void	*regs[SI_MAXCORES];	/* other regs va */
109
+	volatile void	*regs[SI_MAXCORES];	/* other regs va */
64110 
65
-	uint	coreid[SI_MAXCORES];	/* id of each core */
66
-	uint32	coresba[SI_MAXCORES];	/* backplane address of each core */
67
-	void	*regs2[SI_MAXCORES];	/* va of each core second register set (usbh20) */
68
-	uint32	coresba2[SI_MAXCORES];	/* address of each core second register set (usbh20) */
69
-	uint32	coresba_size[SI_MAXCORES]; /* backplane address space size */
70
-	uint32	coresba2_size[SI_MAXCORES]; /* second address space size */
111
+	uint	coreid[SI_MAXCORES];	/**< id of each core */
112
+	uint32	coresba[SI_MAXCORES];	/**< backplane address of each core */
113
+	void	*regs2[SI_MAXCORES];	/**< va of each core second register set (usbh20) */
114
+	uint32	coresba2[SI_MAXCORES];	/**< address of each core second register set (usbh20) */
115
+	uint32	coresba_size[SI_MAXCORES]; /**< backplane address space size */
116
+	uint32	coresba2_size[SI_MAXCORES]; /**< second address space size */
71117 
72
-	void	*wrappers[SI_MAXCORES];	/* other cores wrapper va */
73
-	uint32	wrapba[SI_MAXCORES];	/* address of controlling wrapper */
118
+	void	*wrappers[SI_MAXCORES];	/**< other cores wrapper va */
119
+	uint32	wrapba[SI_MAXCORES];	/**< address of controlling wrapper */
74120 
75
-	void	*wrappers2[SI_MAXCORES];	/* other cores wrapper va */
76
-	uint32	wrapba2[SI_MAXCORES];	/* address of controlling wrapper */
121
+	void	*wrappers2[SI_MAXCORES];	/**< other cores wrapper va */
122
+	uint32	wrapba2[SI_MAXCORES];	/**< address of controlling wrapper */
77123 
78
-	uint32	cia[SI_MAXCORES];	/* erom cia entry for each core */
79
-	uint32	cib[SI_MAXCORES];	/* erom cia entry for each core */
124
+	void	*wrappers3[SI_MAXCORES];	/**< other cores wrapper va */
125
+	uint32	wrapba3[SI_MAXCORES];	/**< address of controlling wrapper */
126
+
127
+	uint32	cia[SI_MAXCORES];	/**< erom cia entry for each core */
128
+	uint32	cib[SI_MAXCORES];	/**< erom cia entry for each core */
129
+
130
+	uint32  csp2ba[SI_MAXCORES];		/**< Second slave port base addr 0 */
131
+	uint32  csp2ba_size[SI_MAXCORES];	/**< Second slave port addr space size */
80132 } si_cores_info_t;
81133 
82
-/* misc si info needed by some of the routines */
134
+/** misc si info needed by some of the routines */
83135 typedef struct si_info {
84
-	struct si_pub pub;		/* back plane public state (must be first field) */
136
+	struct si_pub pub;		/**< back plane public state (must be first field) */
85137 
86
-	void	*osh;			/* osl os handle */
87
-	void	*sdh;			/* bcmsdh handle */
138
+	void	*osh;			/**< osl os handle */
139
+	void	*sdh;			/**< bcmsdh handle */
88140 
89
-	uint	dev_coreid;		/* the core provides driver functions */
90
-	void	*intr_arg;		/* interrupt callback function arg */
91
-	si_intrsoff_t intrsoff_fn;	/* turns chip interrupts off */
92
-	si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
93
-	si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
141
+	uint	dev_coreid;		/**< the core provides driver functions */
142
+	void	*intr_arg;		/**< interrupt callback function arg */
143
+	si_intrsoff_t intrsoff_fn;	/**< turns chip interrupts off */
144
+	si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */
145
+	si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */
94146 
95
-	void *pch;			/* PCI/E core handle */
147
+	void *pch;			/**< PCI/E core handle */
96148 
97
-	bool	memseg;			/* flag to toggle MEM_SEG register */
149
+	bool	memseg;			/**< flag to toggle MEM_SEG register */
98150 
99151 	char *vars;
100152 	uint varsz;
101153 
102
-	void	*curmap;		/* current regs va */
154
+	volatile void	*curmap;		/* current regs va */
103155 
104
-	uint	curidx;			/* current core index */
105
-	uint	numcores;		/* # discovered cores */
156
+	uint	curidx;			/**< current core index */
157
+	uint	numcores;		/**< # discovered cores */
106158 
107
-	void	*curwrap;		/* current wrapper va */
159
+	void	*curwrap;		/**< current wrapper va */
108160 
109
-	uint32	oob_router;		/* oob router registers for axi */
161
+	uint32	oob_router;		/**< oob router registers for axi */
162
+	uint32	oob_router1;		/**< oob router registers for axi */
110163 
111
-	void *cores_info;
112
-	gci_gpio_item_t	*gci_gpio_head;	/* gci gpio interrupts head */
113
-	uint	chipnew;		/* new chip number */
114
-	uint second_bar0win;		/* Backplane region */
115
-	uint	num_br;		/* # discovered bridges */
116
-	uint32	br_wrapba[SI_MAXBR];	/* address of bridge controlling wrapper */
164
+	si_cores_info_t *cores_info;
165
+	gci_gpio_item_t	*gci_gpio_head;	/**< gci gpio interrupts head */
166
+	uint	chipnew;		/**< new chip number */
167
+	uint second_bar0win;		/**< Backplane region */
168
+	uint	num_br;		/**< # discovered bridges */
169
+	uint32	br_wrapba[SI_MAXBR];	/**< address of bridge controlling wrapper */
117170 	uint32	xtalfreq;
171
+	uint32	openloop_dco_code;	/**< OPEN loop calibration dco code */
172
+	uint8	spurmode;
173
+	bool	device_removed;
174
+	uint	axi_num_wrappers;
175
+	axi_wrapper_t   * axi_wrapper;
176
+	uint8	device_wake_opt; /* device_wake GPIO number */
177
+	uint8	lhl_ps_mode;
118178 } si_info_t;
119
-
120179 
121180 #define	SI_INFO(sih)	((si_info_t *)(uintptr)sih)
122181 
....@@ -125,7 +184,7 @@
125184 #define	GOODREGS(regs)	((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
126185 #define BADCOREADDR	0
127186 #define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
128
-#define	NOREV		-1		/* Invalid rev */
187
+#define	NOREV		-1		/**< Invalid rev */
129188 
130189 #define PCI(si)		((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
131190 			 ((si)->pub.buscoretype == PCI_CORE_ID))
....@@ -140,54 +199,46 @@
140199 
141200 #define PCMCIA(si)	((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
142201 
143
-/* Newer chips can access PCI/PCIE and CC core without requiring to change
144
- * PCI BAR0 WIN
145
- */
202
+/** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */
146203 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13)))
147204 
148
-#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
149
-#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
205
+#define CCREGS_FAST(si) \
206
+	(((si)->curmap == NULL) ? NULL : \
207
+	    ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
208
+#define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
150209 
151210 /*
152211  * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
153212  * after core switching to avoid invalid register accesss inside ISR.
154213  */
155214 #define INTR_OFF(si, intr_val) \
156
-	if ((si)->intrsoff_fn && (cores_info)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
215
+	if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
157216 		intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
158217 #define INTR_RESTORE(si, intr_val) \
159
-	if ((si)->intrsrestore_fn && (cores_info)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
218
+	if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
160219 		(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
161220 
162221 /* dynamic clock control defines */
163
-#define	LPOMINFREQ		25000		/* low power oscillator min */
164
-#define	LPOMAXFREQ		43000		/* low power oscillator max */
165
-#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
166
-#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
167
-#define	PCIMINFREQ		25000000	/* 25 MHz */
168
-#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */
222
+#define	LPOMINFREQ		25000		/**< low power oscillator min */
223
+#define	LPOMAXFREQ		43000		/**< low power oscillator max */
224
+#define	XTALMINFREQ		19800000	/**< 20 MHz - 1% */
225
+#define	XTALMAXFREQ		20200000	/**< 20 MHz + 1% */
226
+#define	PCIMINFREQ		25000000	/**< 25 MHz */
227
+#define	PCIMAXFREQ		34000000	/**< 33 MHz + fudge */
169228 
170
-#define	ILP_DIV_5MHZ		0		/* ILP = 5 MHz */
171
-#define	ILP_DIV_1MHZ		4		/* ILP = 1 MHz */
172
-
173
-/* Force fast clock for 4360b0 */
174
-#define PCI_FORCEHT(si)	\
175
-	(((PCIE_GEN1(si)) && (CHIPID(si->pub.chip) == BCM4311_CHIP_ID) && \
176
-	((CHIPREV(si->pub.chiprev) <= 1))) || \
177
-	((PCI(si) || PCIE_GEN1(si)) && (CHIPID(si->pub.chip) == BCM4321_CHIP_ID)) || \
178
-	(PCIE_GEN1(si) && (CHIPID(si->pub.chip) == BCM4716_CHIP_ID)) || \
179
-	(PCIE_GEN1(si) && (CHIPID(si->pub.chip) == BCM4748_CHIP_ID)))
229
+#define	ILP_DIV_5MHZ		0		/**< ILP = 5 MHz */
230
+#define	ILP_DIV_1MHZ		4		/**< ILP = 1 MHz */
180231 
181232 /* GPIO Based LED powersave defines */
182
-#define DEFAULT_GPIO_ONTIME	10		/* Default: 10% on */
183
-#define DEFAULT_GPIO_OFFTIME	90		/* Default: 10% on */
233
+#define DEFAULT_GPIO_ONTIME	10		/**< Default: 10% on */
234
+#define DEFAULT_GPIO_OFFTIME	90		/**< Default: 10% on */
184235 
185236 #ifndef DEFAULT_GPIOTIMERVAL
186237 #define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
187
-#endif
238
+#endif // endif
188239 
189240 /* Silicon Backplane externs */
190
-extern void sb_scan(si_t *sih, void *regs, uint devid);
241
+extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
191242 extern uint sb_coreid(si_t *sih);
192243 extern uint sb_intflag(si_t *sih);
193244 extern uint sb_flag(si_t *sih);
....@@ -195,9 +246,9 @@
195246 extern uint sb_corevendor(si_t *sih);
196247 extern uint sb_corerev(si_t *sih);
197248 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
198
-extern uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
249
+extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
199250 extern bool sb_iscoreup(si_t *sih);
200
-extern void *sb_setcoreidx(si_t *sih, uint coreidx);
251
+extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx);
201252 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
202253 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
203254 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
....@@ -216,7 +267,7 @@
216267 
217268 #if defined(BCMDBG_PHYDUMP)
218269 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
219
-#endif 
270
+#endif // endif
220271 
221272 /* Wake-on-wireless-LAN (WOWL) */
222273 extern bool sb_pci_pmecap(si_t *sih);
....@@ -230,7 +281,7 @@
230281 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
231282                        void *sdh, char **vars, uint *varsz);
232283 extern si_t *ai_kattach(osl_t *osh);
233
-extern void ai_scan(si_t *sih, void *regs, uint devid);
284
+extern void ai_scan(si_t *sih, void *regs, uint32 erombase, uint devid);
234285 
235286 extern uint ai_flag(si_t *sih);
236287 extern uint ai_flag_alt(si_t *sih);
....@@ -238,35 +289,50 @@
238289 extern uint ai_coreidx(si_t *sih);
239290 extern uint ai_corevendor(si_t *sih);
240291 extern uint ai_corerev(si_t *sih);
241
-extern uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
292
+extern uint ai_corerev_minor(si_t *sih);
293
+extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
242294 extern bool ai_iscoreup(si_t *sih);
243
-extern void *ai_setcoreidx(si_t *sih, uint coreidx);
244
-extern void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
295
+extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx);
296
+extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
297
+extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx);
245298 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
246299 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
247300 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
248301 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
302
+extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
249303 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
250304 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits,
251
-	uint32 resetbits, void *p, void *s);
252
-extern void ai_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
253
-extern void ai_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
254
-
305
+	uint32 resetbits, void *p, volatile void *s);
255306 extern void ai_core_disable(si_t *sih, uint32 bits);
256307 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits,
257308 	aidmp_t *pmacai, aidmp_t *smacai);
258309 extern int ai_numaddrspaces(si_t *sih);
259
-extern uint32 ai_addrspace(si_t *sih, uint asidx);
260
-extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
310
+extern uint32 ai_addrspace(si_t *sih, uint spidx, uint baidx);
311
+extern uint32 ai_addrspacesize(si_t *sih, uint spidx, uint baidx);
261312 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
262313 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
263
-extern void ai_enable_backplane_timeouts(si_t *sih);
264
-extern void ai_clear_backplane_to(si_t *sih);
314
+extern void ai_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid);
315
+extern uint32 ai_clear_backplane_to(si_t *sih);
316
+void ai_force_clocks(si_t *sih, uint clock_state);
317
+extern uint ai_num_slaveports(si_t *sih, uint coreidx);
318
+
319
+#ifdef BCM_BACKPLANE_TIMEOUT
320
+uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr);
321
+#endif /* BCM_BACKPLANE_TIMEOUT */
322
+
323
+#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
324
+extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap);
325
+#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
265326 
266327 #if defined(BCMDBG_PHYDUMP)
267328 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
268
-#endif 
329
+#endif // endif
269330 
331
+extern uint32 ai_wrapper_dump_buf_size(si_t *sih);
332
+extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p);
333
+extern bool ai_check_enable_backplane_log(si_t *sih);
334
+extern uint32 ai_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba,
335
+	uchar *p);
270336 
271337 #define ub_scan(a, b, c) do {} while (0)
272338 #define ub_flag(a) (0)