~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,16 +1,17 @@
1		-/* SPDX-License-Identifier: GPL-2.0 */
2	1	/*
3	2	* Misc utility routines for accessing chip-specific features
4	3	* of the SiliconBackplane-based Broadcom chips.
5	4	*
6		- * Copyright (C) 1999-2019, Broadcom Corporation
7		- *
	5	+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
	6	+ *
	7	+ * Copyright (C) 1999-2017, Broadcom Corporation
	8	+ *
8	9	* Unless you and Broadcom execute a separate written software license
9	10	* agreement governing use of this software, this software is licensed to you
10	11	* under the terms of the GNU General Public License version 2 (the "GPL"),
11	12	* available at http://www.broadcom.com/licenses/GPLv2.php, with the
12	13	* following added to such license:
13		- *
	14	+ *
14	15	* As a special exception, the copyright holders of this software give you
15	16	* permission to link this software with independent modules, and to copy and
16	17	* distribute the resulting executable under terms of your choice, provided that
..	..	@@ -18,7 +19,7 @@
18	19	* the license of that module. An independent module is a module which is not
19	20	* derived from this software. The special exception does not apply to any
20	21	* modifications of the software.
21		- *
	22	+ *
22	23	* Notwithstanding the above, under no circumstances may you combine this
23	24	* software in any way with any other Broadcom software provided under a license
24	25	* other than the GPL, without Broadcom's express prior written consent.
..	..	@@ -26,7 +27,7 @@
26	27	*
27	28	* <<Broadcom-WL-IPTag/Open:>>
28	29	*
29		- * $Id: siutils.c 722050 2019-08-21 02:24:57Z $
	30	+ * $Id: siutils.c 701025 2017-05-23 10:23:52Z $
30	31	*/
31	32
32	33	#include <bcm_cfg.h>
..	..	@@ -38,8 +39,12 @@
38	39	#include <bcmdevs.h>
39	40	#include <hndsoc.h>
40	41	#include <sbchipc.h>
	42	+#include <sbgci.h>
	43	+#ifndef BCMSDIO
	44	+#include <pcie_core.h>
	45	+#endif // endif
41	46	#ifdef BCMPCIEDEV
42		-#include <pciedev.h>
	47	+/
43	48	#endif /* BCMPCIEDEV */
44	49	#include <pcicfg.h>
45	50	#include <sbpcmcia.h>
..	..	@@ -54,10 +59,9 @@
54	59	#include <bcmsdpcm.h>
55	60	#endif /* BCMSDIO */
56	61	#include <hndpmu.h>
57		-
58		-#ifdef LOAD_DHD_WITH_FW_ALIVE
59		-#include <dhd_chip_info.h>
60		-#endif
	62	+#ifdef BCMSPI
	63	+#include <spid.h>
	64	+#endif /* BCMSPI */
61	65
62	66	#ifdef BCM_SDRBL
63	67	#include <hndcpu.h>
..	..	@@ -65,8 +69,28 @@
65	69	#ifdef HNDGCI
66	70	#include <hndgci.h>
67	71	#endif /* HNDGCI */
	72	+#ifdef WLGCIMBHLR
	73	+#include <hnd_gci.h>
	74	+#endif /* WLGCIMBHLR */
	75	+#ifdef BCMULP
	76	+#include <ulp.h>
	77	+#endif /* BCMULP */
	78	+#include <hndlhl.h>
	79	+
	80	+#include <lpflags.h>
68	81
69	82	#include "siutils_priv.h"
	83	+#ifdef SECI_UART
	84	+/* Defines the set of GPIOs to be used for SECI UART if not specified in NVRAM */
	85	+/* For further details on each ppin functionality please refer to PINMUX table in
	86	+ * Top level architecture of BCMXXXX Chip
	87	+ */
	88	+#define DEFAULT_SECI_UART_PINMUX 0x08090a0b
	89	+#define DEFAULT_SECI_UART_PINMUX_43430 0x0102
	90	+static bool force_seci_clk = 0;
	91	+#endif /* SECI_UART */
	92	+
	93	+#define XTAL_FREQ_26000KHZ 26000
70	94
71	95	/**
72	96	* A set of PMU registers is clocked in the ILP domain, which has an implication on register write
..	..	@@ -83,26 +107,35 @@
83	107	(regoff) == OFFSETOF(chipcregs_t, pmuwatchdog) \|\| \
84	108	(regoff) == OFFSETOF(chipcregs_t, res_req_timer))
85	109
	110	+#define GCI_FEM_CTRL_WAR 0x11111111
	111	+
	112	+#ifndef AXI_TO_VAL
	113	+#define AXI_TO_VAL 19
	114	+#endif /* AXI_TO_VAL */
	115	+
	116	+#ifndef AXI_TO_VAL_4347
	117	+/*
	118	+ * Increase BP timeout for fast clock and short PCIe timeouts
	119	+ * New timeout: 2 ** 25 cycles
	120	+ */
	121	+#define AXI_TO_VAL_4347 25
	122	+#endif /* AXI_TO_VAL_4347 */
	123	+
86	124	/* local prototypes */
87		-static si_info_t si_doattach(si_info_t sii, uint devid, osl_t osh, void regs,
	125	+static si_info_t si_doattach(si_info_t sii, uint devid, osl_t osh, volatile void regs,
88	126	uint bustype, void sdh, char vars, uint varsz);
89	127	static bool si_buscore_prep(si_info_t sii, uint bustype, uint devid, void sdh);
90	128	static bool si_buscore_setup(si_info_t sii, chipcregs_t cc, uint bustype, uint32 savewin,
91		- uint origidx, void regs);
92		-
	129	+ uint origidx, volatile void regs);
93	130
94	131	static bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff);
95		-
96		-#ifdef BCMLTECOEX
97		-static void si_config_gcigpio(si_t *sih, uint32 gci_pos, uint8 gcigpio,
98		- uint8 gpioctl_mask, uint8 gpioctl_val);
99		-#endif /* BCMLTECOEX */
100		-
101	132
102	133	/* global variable to indicate reservation/release of gpio's */
103	134	static uint32 si_gpioreservation = 0;
104	135
105	136	/* global flag to prevent shared resources from being initialized multiple times in si_attach() */
	137	+static bool si_onetimeinit = FALSE;
	138	+
106	139	#ifdef SR_DEBUG
107	140	static const uint32 si_power_island_test_array[] = {
108	141	0x0000, 0x0001, 0x0010, 0x0011,
..	..	@@ -113,6 +146,11 @@
113	146	#endif /* SR_DEBUG */
114	147
115	148	int do_4360_pcie2_war = 0;
	149	+
	150	+#ifdef BCMULP
	151	+/* Variable to store boot_type: warm_boot/cold_boot/etc. */
	152	+static int boot_type = 0;
	153	+#endif // endif
116	154
117	155	/* global kernel resource */
118	156	static si_info_t ksii;
..	..	@@ -130,19 +168,21 @@
130	168	* varsz - pointer to int to return the size of the vars
131	169	*/
132	170	si_t *
133		-si_attach(uint devid, osl_t osh, void regs,
	171	+si_attach(uint devid, osl_t osh, volatile void regs,
134	172	uint bustype, void sdh, char vars, uint varsz)
135	173	{
136	174	si_info_t *sii;
137	175	si_cores_info_t *cores_info;
138	176	/* alloc si_info_t */
139		- if ((sii = MALLOCZ(osh, sizeof (si_info_t))) == NULL) {
	177	+ /* freed after ucode download for firmware builds */
	178	+ if ((sii = MALLOCZ_NOPERSIST(osh, sizeof(si_info_t))) == NULL) {
140	179	SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
141	180	return (NULL);
142	181	}
143	182
144	183	/* alloc si_cores_info_t */
145		- if ((cores_info = (si_cores_info_t *)MALLOCZ(osh, sizeof (si_cores_info_t))) == NULL) {
	184	+ if ((cores_info = (si_cores_info_t *)MALLOCZ(osh,
	185	+ sizeof(si_cores_info_t))) == NULL) {
146	186	SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
147	187	MFREE(osh, sii, sizeof(si_info_t));
148	188	return (NULL);
..	..	@@ -160,10 +200,39 @@
160	200	return (si_t *)sii;
161	201	}
162	202
	203	+static uint32 wd_msticks; /*< watchdog timer ticks normalized to ms /
163	204
164		-static uint32 wd_msticks; /* watchdog timer ticks normalized to ms */
	205	+/** Returns the backplane address of the chipcommon core for a particular chip */
	206	+uint32
	207	+si_enum_base(uint devid)
	208	+{
	209	+ // NIC/DHD build
	210	+ switch (devid) {
	211	+ case BCM7271_CHIP_ID:
	212	+ case BCM7271_D11AC_ID:
	213	+ case BCM7271_D11AC2G_ID:
	214	+ case BCM7271_D11AC5G_ID:
	215	+ return 0xF1800000;
	216	+ }
165	217
166		-/** generic kernel variant of si_attach() */
	218	+ return SI_ENUM_BASE_DEFAULT;
	219	+}
	220	+
	221	+/** Returns the backplane address of the PCIE core for a particular chip */
	222	+uint32
	223	+si_pcie_enum_base(uint devid)
	224	+{
	225	+ switch (devid) {
	226	+ case CYW55560_WLAN_ID:
	227	+ case CYW89570_WLAN_ID:
	228	+ return SI_ENUM_PCIE2_BASE;
	229	+ }
	230	+
	231	+ /* Default - In future chips if devid is not matched */
	232	+ return SI_ENUM_PCIE2_BASE;
	233	+}
	234	+
	235	+/** generic kernel variant of si_attach(). Is not called for Linux WLAN NIC builds. */
167	236	si_t *
168	237	si_kattach(osl_t *osh)
169	238	{
..	..	@@ -172,12 +241,14 @@
172	241
173	242	if (!ksii_attached) {
174	243	void *regs = NULL;
175		- regs = REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
	244	+ const uint device_id = BCM4710_DEVICE_ID; // pick an arbitrary default device_id
	245	+
	246	+ regs = REG_MAP(si_enum_base(device_id), SI_CORE_SIZE); // map physical to virtual
176	247	cores_info = (si_cores_info_t *)&ksii_cores_info;
177	248	ksii.cores_info = cores_info;
178	249
179	250	ASSERT(osh);
180		- if (si_doattach(&ksii, BCM4710_DEVICE_ID, osh, regs,
	251	+ if (si_doattach(&ksii, device_id, osh, regs,
181	252	SI_BUS, NULL,
182	253	osh != SI_OSH ? &(ksii.vars) : NULL,
183	254	osh != SI_OSH ? &(ksii.varsz) : NULL) == NULL) {
..	..	@@ -189,30 +260,30 @@
189	260
190	261	/* save ticks normalized to ms for si_watchdog_ms() */
191	262	if (PMUCTL_ENAB(&ksii.pub)) {
192		- /* based on 32KHz ILP clock */
193		- wd_msticks = 32;
	263	+ /* based on 32KHz ILP clock */
	264	+ wd_msticks = 32;
194	265	} else {
195	266	wd_msticks = ALP_CLOCK / 1000;
196	267	}
197	268
198	269	ksii_attached = TRUE;
199	270	SI_MSG(("si_kattach done. ccrev = %d, wd_msticks = %d\n",
200		- ksii.pub.ccrev, wd_msticks));
	271	+ CCREV(ksii.pub.ccrev), wd_msticks));
201	272	}
202	273
203	274	return &ksii.pub;
204	275	}
205	276
206		-
207	277	static bool
208	278	si_buscore_prep(si_info_t sii, uint bustype, uint devid, void sdh)
209	279	{
	280	+ BCM_REFERENCE(sdh);
	281	+ BCM_REFERENCE(devid);
210	282	/* need to set memseg flag for CF card first before any sb registers access */
211	283	if (BUSTYPE(bustype) == PCMCIA_BUS)
212	284	sii->memseg = TRUE;
213	285
214		-
215		-#if defined(BCMSDIO)
	286	+#if defined(BCMSDIO) && !defined(BCMSDIOLITE)
216	287	if (BUSTYPE(bustype) == SDIO_BUS) {
217	288	int err;
218	289	uint8 clkset;
..	..	@@ -245,7 +316,25 @@
245	316	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
246	317	}
247	318
248		-#endif /* BCMSDIO && BCMDONGLEHOST */
	319	+#ifdef BCMSPI
	320	+ /* Avoid backplane accesses before wake-wlan (i.e. htavail) for spi.
	321	+ * F1 read accesses may return correct data but with data-not-available dstatus bit set.
	322	+ */
	323	+ if (BUSTYPE(bustype) == SPI_BUS) {
	324	+
	325	+ int err;
	326	+ uint32 regdata;
	327	+ /* wake up wlan function :WAKE_UP goes as HT_AVAIL request in hardware */
	328	+ regdata = bcmsdh_cfg_read_word(sdh, SDIO_FUNC_0, SPID_CONFIG, NULL);
	329	+ SI_MSG(("F0 REG0 rd = 0x%x\n", regdata));
	330	+ regdata \|= WAKE_UP;
	331	+
	332	+ bcmsdh_cfg_write_word(sdh, SDIO_FUNC_0, SPID_CONFIG, regdata, &err);
	333	+
	334	+ OSL_DELAY(100000);
	335	+ }
	336	+#endif /* BCMSPI */
	337	+#endif /* BCMSDIO && BCMDONGLEHOST && !BCMSDIOLITE */
249	338
250	339	return TRUE;
251	340	}
..	..	@@ -268,46 +357,31 @@
268	357	origidx = sii->curidx;
269	358	pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
270	359	pmu = si_setcoreidx(&sii->pub, pmucoreidx);
271		- pmuaddr = (uint32)(unsigned long)((uint8*)pmu + offset);
	360	+ pmuaddr = (uint32)(uintptr)((volatile uint8*)pmu + offset);
272	361	si_setcoreidx(sih, origidx);
273	362	} else
274		- pmuaddr = SI_ENUM_BASE + offset;
	363	+ pmuaddr = SI_ENUM_BASE(sih) + offset;
275	364
276	365	done:
277		- SI_MSG(("%s: addrRET: %x\n", __FUNCTION__, pmuaddr));
	366	+ printf("%s: addrRET: %x\n", __FUNCTION__, pmuaddr);
278	367	return pmuaddr;
279	368	}
280	369
281	370	static bool
282	371	si_buscore_setup(si_info_t sii, chipcregs_t cc, uint bustype, uint32 savewin,
283		- uint origidx, void regs)
	372	+ uint origidx, volatile void regs)
284	373	{
285	374	si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
286	375	bool pci, pcie, pcie_gen2 = FALSE;
287	376	uint i;
288	377	uint pciidx, pcieidx, pcirev, pcierev;
	378	+ struct si_pub *sih = &sii->pub;
289	379
290		-#ifdef LOAD_DHD_WITH_FW_ALIVE
291		- if(alive == FW_ALIVE_MAGIC) {
292		- switch(card_dev) {
293		- case BCM43430_CHIP_ID:
294		- if(card_rev == 2)
295		- memcpy(&sii->pub, &sii_pub_43436, sizeof(sii->pub));
296		- else
297		- memcpy(&sii->pub, &sii_pub_43430, sizeof(sii->pub));
298		- break;
299		-
300		- case BCM43012_CHIP_ID:
301		- memcpy(&sii->pub, &sii_pub_43012, sizeof(sii->pub));
302		- break;
303		- }
304		- return true;
305		- }
306		-#endif
307		-
	380	+#if defined(BCM_BACKPLANE_TIMEOUT) \|\| defined(AXI_TIMEOUTS)
308	381	/* first, enable backplane timeouts */
309		- if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
310		- ai_enable_backplane_timeouts(&sii->pub);
	382	+ si_slave_wrapper_add(&sii->pub);
	383	+#endif // endif
	384	+ sii->curidx = 0;
311	385
312	386	cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
313	387	ASSERT((uintptr)cc);
..	..	@@ -316,33 +390,50 @@
316	390	sii->pub.ccrev = (int)si_corerev(&sii->pub);
317	391
318	392	/* get chipcommon chipstatus */
319		- if (sii->pub.ccrev >= 11)
320		- sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
	393	+ if (CCREV(sii->pub.ccrev) >= 11) {
	394	+ /* TODO : We need a better approach to avoid this access in secure mode chips */
	395	+ if (sii->pub.chip != CYW55500_CHIP_ID &&
	396	+ sii->pub.chip != CYW55560_CHIP_ID) {
	397	+ sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
	398	+ }
	399	+ }
321	400
322		- /* get chipcommon capabilites */
323		- sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
324		- /* get chipcommon extended capabilities */
	401	+ if (!sih->chipidpresent) {
	402	+ /* get chipcommon capabilites */
	403	+ sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
	404	+ /* get chipcommon extended capabilities */
	405	+ if (CCREV(sii->pub.ccrev) >= 35)
	406	+ sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
325	407
326		- if (sii->pub.ccrev >= 35)
327		- sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
	408	+ /* get pmu rev and caps */
	409	+ if (sii->pub.cccaps & CC_CAP_PMU) {
	410	+ if (AOB_ENAB(&sii->pub)) {
	411	+ uint pmucoreidx;
	412	+ pmuregs_t *pmu;
	413	+ struct si_pub *sih = &sii->pub;
328	414
329		- /* get pmu rev and caps */
330		- if (sii->pub.cccaps & CC_CAP_PMU) {
331		- if (AOB_ENAB(&sii->pub)) {
332		- uint pmucoreidx;
333		- pmuregs_t *pmu;
334		- pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
335		- pmu = si_setcoreidx(&sii->pub, pmucoreidx);
336		- sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities);
337		- si_setcoreidx(&sii->pub, SI_CC_IDX);
338		- } else
339		- sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
	415	+ pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
	416	+ if (!GOODIDX(pmucoreidx)) {
	417	+ SI_ERROR(("si_buscore_setup: si_findcoreidx failed\n"));
	418	+ return FALSE;
	419	+ }
340	420
341		- sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
	421	+ pmu = si_setcoreidx(&sii->pub, pmucoreidx);
	422	+ sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities);
	423	+ si_setcoreidx(&sii->pub, SI_CC_IDX);
	424	+
	425	+ sii->pub.gcirev = si_corereg(sih, GCI_CORE_IDX(sih),
	426	+ GCI_OFFSETOF(sih, gci_corecaps0), 0, 0) &
	427	+ GCI_CAP0_REV_MASK;
	428	+ } else
	429	+ sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
	430	+
	431	+ sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
	432	+ }
342	433	}
343	434
344	435	SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
345		- sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
	436	+ CCREV(sii->pub.ccrev), sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
346	437	sii->pub.pmucaps));
347	438
348	439	/* figure out bus/orignal core idx */
..	..	@@ -362,28 +453,23 @@
362	453	crev = si_corerev(&sii->pub);
363	454
364	455	/* Display cores found */
365		- SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
366		- i, cid, crev, cores_info->coresba[i], cores_info->regs[i]));
	456	+ SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x size:%x regs 0x%p\n",
	457	+ i, cid, crev, sii->coresba[i], sii->coresba_size[i],
	458	+ OSL_OBFUSCATE_BUF(sii->regs[i])));
367	459
368	460	if (BUSTYPE(bustype) == SI_BUS) {
369	461	/* now look at the chipstatus register to figure the pacakge */
370	462	/* for SDIO but downloaded on PCIE dev */
	463	+#ifdef BCMPCIEDEV_ENABLED
371	464	if (cid == PCIE2_CORE_ID) {
372		- if (BCM43602_CHIP(sii->pub.chip) \|\|
373		- (CHIPID(sii->pub.chip) == BCM4365_CHIP_ID) \|\|
374		- (CHIPID(sii->pub.chip) == BCM4366_CHIP_ID) \|\|
375		- ((CHIPID(sii->pub.chip) == BCM4345_CHIP_ID \|\|
376		- CHIPID(sii->pub.chip) == BCM43454_CHIP_ID) &&
377		- CST4345_CHIPMODE_PCIE(sii->pub.chipst))) {
378	465	pcieidx = i;
379	466	pcierev = crev;
380	467	pcie = TRUE;
381	468	pcie_gen2 = TRUE;
382		- }
383	469	}
	470	+#endif // endif
384	471
385		- }
386		- else if (BUSTYPE(bustype) == PCI_BUS) {
	472	+ } else if (BUSTYPE(bustype) == PCI_BUS) {
387	473	if (cid == PCI_CORE_ID) {
388	474	pciidx = i;
389	475	pcirev = crev;
..	..	@@ -418,7 +504,6 @@
418	504	*origidx = i;
419	505	}
420	506
421		-
422	507	#if defined(PCIE_FULL_DONGLE)
423	508	if (pcie) {
424	509	if (pcie_gen2)
..	..	@@ -449,11 +534,6 @@
449	534	SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype,
450	535	sii->pub.buscorerev));
451	536
452		- if (BUSTYPE(sii->pub.bustype) == SI_BUS && (CHIPID(sii->pub.chip) == BCM4712_CHIP_ID) &&
453		- (sii->pub.chippkg != BCM4712LARGE_PKG_ID) && (CHIPREV(sii->pub.chiprev) <= 3))
454		- OR_REG(sii->osh, &cc->slow_clk_ctl, SCC_SS_XTAL);
455		-
456		-
457	537	#if defined(BCMSDIO)
458	538	/* Make sure any on-chip ARM is off (in case strapping is wrong), or downloaded code was
459	539	* already running.
..	..	@@ -471,9 +551,6 @@
471	551	return TRUE;
472	552	}
473	553
474		-
475		-
476		-
477	554	uint16
478	555	si_chipid(si_t *sih)
479	556	{
..	..	@@ -482,6 +559,7 @@
482	559	return (sii->chipnew) ? sii->chipnew : sih->chip;
483	560	}
484	561
	562	+/* CHIP_ID's being mapped here should not be used anywhere else in the code */
485	563	static void
486	564	si_chipid_fixup(si_t *sih)
487	565	{
..	..	@@ -493,49 +571,162 @@
493	571	sii->chipnew = sih->chip; /* save it */
494	572	sii->pub.chip = BCM43570_CHIP_ID; /* chip class */
495	573	break;
	574	+ case BCM43562_CHIP_ID:
496	575	case BCM4358_CHIP_ID:
497	576	case BCM43566_CHIP_ID:
498	577	sii->chipnew = sih->chip; /* save it */
499	578	sii->pub.chip = BCM43569_CHIP_ID; /* chip class */
500	579	break;
501	580	case BCM4356_CHIP_ID:
	581	+ case BCM4371_CHIP_ID:
502	582	sii->chipnew = sih->chip; /* save it */
503	583	sii->pub.chip = BCM4354_CHIP_ID; /* chip class */
504	584	break;
	585	+ case BCM4357_CHIP_ID:
	586	+ case BCM4361_CHIP_ID:
	587	+ sii->chipnew = sih->chip; /* save it */
	588	+ sii->pub.chip = BCM4347_CHIP_ID; /* chip class */
	589	+ break;
	590	+#ifdef CHIPS_CUSTOMER_HW6
	591	+ case BCM4377_CHIP_ID:
	592	+ sii->chipnew = sih->chip; /* save it */
	593	+ sii->pub.chip = BCM4369_CHIP_ID; /* chip class */
	594	+ break;
	595	+#endif /* CHIPS_CUSTOMER_HW6 */
505	596	default:
506	597	break;
507	598	}
508	599	}
509	600
	601	+#ifdef BCMULP
	602	+static void
	603	+si_check_boot_type(si_t sih, osl_t osh)
	604	+{
	605	+ if (sih->pmurev >= 30) {
	606	+ boot_type = PMU_REG_NEW(sih, swscratch, 0, 0);
	607	+ } else {
	608	+ boot_type = CHIPC_REG(sih, flashdata, 0, 0);
	609	+ }
	610	+
	611	+ SI_ERROR(("%s: boot_type: 0x%08x\n", __func__, boot_type));
	612	+}
	613	+#endif /* BCMULP */
	614	+
	615	+#ifdef BCM_BACKPLANE_TIMEOUT
	616	+uint32
	617	+si_clear_backplane_to_fast(void sih, void addr)
	618	+{
	619	+ si_t *_sih = DISCARD_QUAL(sih, si_t);
	620	+
	621	+ if (CHIPTYPE(_sih->socitype) == SOCI_AI) {
	622	+ return ai_clear_backplane_to_fast(_sih, addr);
	623	+ }
	624	+
	625	+ return 0;
	626	+}
	627	+
	628	+const si_axi_error_info_t *
	629	+si_get_axi_errlog_info(si_t *sih)
	630	+{
	631	+ if (CHIPTYPE(sih->socitype) == SOCI_AI) {
	632	+ return (const si_axi_error_info_t *)sih->err_info;
	633	+ }
	634	+
	635	+ return NULL;
	636	+}
	637	+
	638	+void
	639	+si_reset_axi_errlog_info(si_t *sih)
	640	+{
	641	+ if (sih->err_info) {
	642	+ sih->err_info->count = 0;
	643	+ }
	644	+}
	645	+#endif /* BCM_BACKPLANE_TIMEOUT */
	646	+
	647	+#ifdef BCMSDIO
	648	+void *
	649	+si_get_sdio_addrbase(void *sdh)
	650	+{
	651	+ uint8 devctl;
	652	+ int err = 0;
	653	+ uint32 addr = 0;
	654	+
	655	+ devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
	656	+ if (err)
	657	+ return NULL;
	658	+
	659	+ bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
	660	+ SBSDIO_DEVICE_CTL, devctl \| SBSDIO_DEVCTL_ADDR_RESET, &err);
	661	+ if (err)
	662	+ goto exit;
	663	+
	664	+ addr \|= (bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, NULL) << 8) \|
	665	+ (bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, NULL) << 16) \|
	666	+ (bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, NULL) << 24);
	667	+
	668	+ SI_MSG(("%s: sdiod core address is 0x%x\n", __FUNCTION__, addr));
	669	+exit:
	670	+ if (err) {
	671	+ SI_ERROR(("%s: Get SDIO core base address failed, err=%d", __FUNCTION__, err));
	672	+ addr = 0;
	673	+ }
	674	+ bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
	675	+
	676	+ return (void *)((uintptr)addr);
	677	+}
	678	+#endif /* BCMSDIO */
	679	+
510	680	/**
511		- * Allocate an si handle. This function may be called multiple times.
	681	+ * Allocate an si handle. This function may be called multiple times. This function is called by
	682	+ * both si_attach() and si_kattach().
512	683	*
513	684	* vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
514	685	* function set 'vars' to NULL.
515	686	*/
516	687	static si_info_t *
517		-si_doattach(si_info_t sii, uint devid, osl_t osh, void *regs,
	688	+si_doattach(si_info_t sii, uint devid, osl_t osh, volatile void *regs,
518	689	uint bustype, void sdh, char vars, uint varsz)
519	690	{
520	691	struct si_pub *sih = &sii->pub;
521		- uint32 w, savewin;
	692	+ uint32 w = 0;
	693	+ uint32 savewin;
522	694	chipcregs_t *cc;
523	695	char *pvars = NULL;
524	696	uint origidx;
525		-#if !defined(_CFEZ_) \|\| defined(CFG_WL)
526		-#endif
	697	+#ifdef NVSRCX
	698	+ char *sromvars;
	699	+#endif // endif
	700	+ uint32 erombase;
	701	+#ifdef BCMSDIO
	702	+ uint8 cardcap;
	703	+ sdpcmd_regs_t *sdioc;
	704	+#endif // endif
527	705
528	706	ASSERT(GOODREGS(regs));
529	707
530	708	savewin = 0;
531	709
532	710	sih->buscoreidx = BADIDX;
	711	+ sii->device_removed = FALSE;
533	712
534	713	sii->curmap = regs;
535	714	sii->sdh = sdh;
536	715	sii->osh = osh;
537	716	sii->second_bar0win = ~0x0;
	717	+ sih->enum_base = si_enum_base(devid);
538	718
	719	+#if defined(BCM_BACKPLANE_TIMEOUT)
	720	+ sih->err_info = MALLOCZ(osh, sizeof(si_axi_error_info_t));
	721	+ if (sih->err_info == NULL) {
	722	+ SI_ERROR(("%s: %zu bytes MALLOC FAILED",
	723	+ __FUNCTION__, sizeof(si_axi_error_info_t)));
	724	+ }
	725	+#endif /* BCM_BACKPLANE_TIMEOUT */
	726	+
	727	+#if defined(BCM_BACKPLANE_TIMEOUT)
	728	+ osl_set_bpt_cb(osh, (void )si_clear_backplane_to_fast, (void )sih);
	729	+#endif // endif
539	730
540	731	/* check to see if we are a si core mimic'ing a pci core */
541	732	if ((bustype == PCI_BUS) &&
..	..	@@ -548,29 +739,42 @@
548	739	/* find Chipcommon address */
549	740	if (bustype == PCI_BUS) {
550	741	savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
551		- if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
552		- savewin = SI_ENUM_BASE;
553		- OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
	742	+ if (!GOODCOREADDR(savewin, SI_ENUM_BASE(sih)))
	743	+ savewin = SI_ENUM_BASE(sih);
	744	+ OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE(sih));
554	745	if (!regs)
555	746	return NULL;
556	747	cc = (chipcregs_t *)regs;
	748	+ erombase = R_REG(osh, &cc->eromptr);
557	749	#ifdef BCMSDIO
558	750	} else if ((bustype == SDIO_BUS) \|\| (bustype == SPI_BUS)) {
559	751	cc = (chipcregs_t *)sii->curmap;
560		-#endif
	752	+ cardcap = bcmsdh_cfg_read(sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, NULL);
	753	+ if (cardcap & SDIOD_CCCR_BRCM_CARDCAP_CHIPID_PRESENT) {
	754	+ sih->chipidpresent = TRUE;
	755	+ sdioc = si_get_sdio_addrbase(sdh);
	756	+ w = R_REG(osh, &sdioc->chipid);
	757	+ erombase = R_REG(osh, &sdioc->eromptr);
	758	+ } else {
	759	+ erombase = R_REG(osh, &cc->eromptr);
	760	+ }
	761	+ if (cardcap & SDIOD_CCCR_BRCM_CARDCAP_SECURE_MODE) {
	762	+ sih->secureboot = TRUE;
	763	+ }
	764	+#endif // endif
561	765	} else {
562		- cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
	766	+ cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE(sih), SI_CORE_SIZE);
	767	+ erombase = R_REG(osh, &cc->eromptr);
563	768	}
564	769
565	770	sih->bustype = bustype;
566	771	#ifdef BCMBUSTYPE
567		- /* Fix the -Werror=tautological-compare compiling error */
568	772	if (bustype != BUSTYPE(bustype)) {
569	773	SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n",
570	774	bustype, BUSTYPE(bustype)));
571	775	return NULL;
572	776	}
573		-#endif
	777	+#endif // endif
574	778
575	779	/* bus/core/clk setup for register access */
576	780	if (!si_buscore_prep(sii, bustype, devid, sdh)) {
..	..	@@ -587,7 +791,8 @@
587	791	SI_ERROR(("%s: chipcommon register space is null \n", __FUNCTION__));
588	792	return NULL;
589	793	}
590		- w = R_REG(osh, &cc->chipid);
	794	+ if (!w)
	795	+ w = R_REG(osh, &cc->chipid);
591	796	if ((w & 0xfffff) == 148277) w -= 65532;
592	797	sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
593	798	/* Might as wll fill in chip id rev & pkg */
..	..	@@ -597,24 +802,50 @@
597	802
598	803	si_chipid_fixup(sih);
599	804
600		- if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && CHIPREV(sih->chiprev == 0) &&
601		- (sih->chippkg != BCM4329_289PIN_PKG_ID)) {
602		- sih->chippkg = BCM4329_182PIN_PKG_ID;
	805	+ if (CHIPID(sih->chip) == BCM43465_CHIP_ID) {
	806	+ sih->chip = BCM4366_CHIP_ID;
	807	+ } else if (CHIPID(sih->chip) == BCM43525_CHIP_ID) {
	808	+ sih->chip = BCM4365_CHIP_ID;
603	809	}
	810	+
604	811	sih->issim = IS_SIM(sih->chippkg);
	812	+
	813	+#ifdef CHIPS_CUSTOMER_HW6
	814	+ if (MULTIBP_CAP(sih))
	815	+ {
	816	+ sih->_multibp_enable = TRUE;
	817	+ }
	818	+#endif // endif
605	819
606	820	/* scan for cores */
607	821	if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) {
608	822	SI_MSG(("Found chip type SB (0x%08x)\n", w));
609	823	sb_scan(&sii->pub, regs, devid);
610	824	} else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) \|\|
611		- (CHIPTYPE(sii->pub.socitype) == SOCI_NAI)) {
	825	+ (CHIPTYPE(sii->pub.socitype) == SOCI_NAI) \|\|
	826	+ (CHIPTYPE(sii->pub.socitype) == SOCI_DVTBUS)) {
	827	+
612	828	if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
613	829	SI_MSG(("Found chip type AI (0x%08x)\n", w));
614		- else
	830	+ else if (CHIPTYPE(sii->pub.socitype) == SOCI_NAI)
615	831	SI_MSG(("Found chip type NAI (0x%08x)\n", w));
	832	+ else
	833	+ SI_MSG(("Found chip type DVT (0x%08x)\n", w));
616	834	/* pass chipc address instead of original core base */
617		- ai_scan(&sii->pub, (void *)(uintptr)cc, devid);
	835	+
	836	+ if (sii->osh) {
	837	+ sii->axi_wrapper = (axi_wrapper_t *)MALLOCZ(sii->osh,
	838	+ (sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS));
	839	+
	840	+ if (sii->axi_wrapper == NULL) {
	841	+ SI_ERROR(("%s: %zu bytes MALLOC Failed", __FUNCTION__,
	842	+ (sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS)));
	843	+ }
	844	+ } else {
	845	+ sii->axi_wrapper = NULL;
	846	+ }
	847	+
	848	+ ai_scan(&sii->pub, (void *)(uintptr)cc, erombase, devid);
618	849	} else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
619	850	SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip));
620	851	/* pass chipc address instead of original core base */
..	..	@@ -634,17 +865,19 @@
634	865	SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
635	866	goto exit;
636	867	}
	868	+#ifdef BCMULP
	869	+ if (BCMULP_ENAB()) {
	870	+ si_check_boot_type(sih, osh);
	871	+ if (ulp_module_init(osh, sih) != BCME_OK) {
	872	+ ULP_ERR(("%s: err in ulp_module_init\n", __FUNCTION__));
	873	+ goto exit;
	874	+ }
	875	+ }
	876	+#endif /* BCMULP */
637	877
638	878	#if !defined(_CFEZ_) \|\| defined(CFG_WL)
639		- if (CHIPID(sih->chip) == BCM4322_CHIP_ID && (((sih->chipst & CST4322_SPROM_OTP_SEL_MASK)
640		- >> CST4322_SPROM_OTP_SEL_SHIFT) == (CST4322_OTP_PRESENT \|
641		- CST4322_SPROM_PRESENT))) {
642		- SI_ERROR(("%s: Invalid setting: both SPROM and OTP strapped.\n", __FUNCTION__));
643		- return NULL;
644		- }
645		-
646	879	/* assume current core is CC */
647		- if ((sii->pub.ccrev == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID \|\|
	880	+ if ((CCREV(sii->pub.ccrev) == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID \|\|
648	881	CHIPID(sih->chip) == BCM43235_CHIP_ID \|\|
649	882	CHIPID(sih->chip) == BCM43234_CHIP_ID \|\|
650	883	CHIPID(sih->chip) == BCM43238_CHIP_ID) &&
..	..	@@ -661,10 +894,54 @@
661	894	OSL_DELAY(10);
662	895	}
663	896
	897	+ /* Set the clkdiv2 divisor bits (2:0) to 0x4 if srom is present */
	898	+ if (bustype == SI_BUS) {
	899	+ uint32 clkdiv2, sromprsnt, capabilities, srom_supported;
	900	+ capabilities = R_REG(osh, &cc->capabilities);
	901	+ srom_supported = capabilities & SROM_SUPPORTED;
	902	+ if (srom_supported)
	903	+ {
	904	+ sromprsnt = R_REG(osh, &cc->sromcontrol);
	905	+ sromprsnt = sromprsnt & SROM_PRSNT_MASK;
	906	+ if (sromprsnt) {
	907	+ /* SROM clock come from backplane clock/div2. Must <= 1Mhz */
	908	+ clkdiv2 = (R_REG(osh, &cc->clkdiv2) & ~CLKD2_SROM);
	909	+ clkdiv2 \|= CLKD2_SROMDIV_192;
	910	+ W_REG(osh, &cc->clkdiv2, clkdiv2);
	911	+ }
	912	+ }
	913	+ }
	914	+
664	915	if (bustype == PCI_BUS) {
665	916
	917	+#ifdef BCMQT
	918	+ /* Set OTPClkDiv to smaller value otherwise OTP always reads 0xFFFF.
	919	+ * For real-chip we shouldn't set OTPClkDiv to 2 because 20/2 = 10 > 9Mhz
	920	+ */
	921	+ {
	922	+ uint otpclkdiv = 0;
	923	+
	924	+ if ((CHIPID(sih->chip) == BCM43131_CHIP_ID) \|\|
	925	+ (CHIPID(sih->chip) == BCM43217_CHIP_ID)) {
	926	+ otpclkdiv = 4;
	927	+ }
	928	+
	929	+ if (otpclkdiv != 0) {
	930	+ uint clkdiv, savecore;
	931	+ savecore = si_coreidx(sih);
	932	+ si_setcore(sih, CC_CORE_ID, 0);
	933	+
	934	+ clkdiv = R_REG(osh, &cc->clkdiv);
	935	+ clkdiv = (clkdiv & ~CLKD_OTP) \| (otpclkdiv << CLKD_OTP_SHIFT);
	936	+ W_REG(osh, &cc->clkdiv, clkdiv);
	937	+
	938	+ SI_ERROR(("%s: set clkdiv to 0x%x for QT\n", __FUNCTION__, clkdiv));
	939	+ si_setcoreidx(sih, savecore);
	940	+ }
	941	+ }
	942	+#endif /* BCMQT */
666	943	}
667		-#endif
	944	+#endif // endif
668	945	#ifdef BCM_SDRBL
669	946	/* 4360 rom bootloader in PCIE case, if the SDR is enabled, But preotection is
670	947	* not turned on, then we want to hold arm in reset.
..	..	@@ -689,35 +966,34 @@
689	966	pvars = NULL;
690	967	BCM_REFERENCE(pvars);
691	968
	969	+ {
	970	+ sii->lhl_ps_mode = LHL_PS_MODE_0;
	971	+ }
692	972
	973	+ if (!si_onetimeinit) {
693	974
694		- if (sii->pub.ccrev >= 20) {
	975	+ if (CCREV(sii->pub.ccrev) >= 20) {
695	976	uint32 gpiopullup = 0, gpiopulldown = 0;
696	977	cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
697	978	ASSERT(cc != NULL);
698		-
699		- /* 4314/43142 has pin muxing, don't clear gpio bits */
700		- if ((CHIPID(sih->chip) == BCM4314_CHIP_ID) \|\|
701		- (CHIPID(sih->chip) == BCM43142_CHIP_ID)) {
702		- gpiopullup \|= 0x402e0;
703		- gpiopulldown \|= 0x20500;
704		- }
705		-
706		-
707		- W_REG(osh, &cc->gpiopullup, gpiopullup);
708		- W_REG(osh, &cc->gpiopulldown, gpiopulldown);
	979	+ BCM_REFERENCE(gpiopullup);
	980	+ BCM_REFERENCE(gpiopulldown);
709	981	si_setcoreidx(sih, origidx);
710	982	}
711	983
	984	+ }
712	985
713	986	/* clear any previous epidiag-induced target abort */
714	987	ASSERT(!si_taclear(sih, FALSE));
715	988
	989	+#if defined(BCMPMU_STATS) && !defined(BCMPMU_STATS_DISABLED)
	990	+ si_pmustatstimer_init(sih);
	991	+#endif /* BCMPMU_STATS */
716	992
717	993	#ifdef BOOTLOADER_CONSOLE_OUTPUT
718	994	/* Enable console prints */
719	995	si_muxenab(sii, 3);
720		-#endif
	996	+#endif // endif
721	997
722	998	return (sii);
723	999
..	..	@@ -734,7 +1010,6 @@
734	1010	si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
735	1011	uint idx;
736	1012
737		-
738	1013	if (BUSTYPE(sih->bustype) == SI_BUS)
739	1014	for (idx = 0; idx < SI_MAXCORES; idx++)
740	1015	if (cores_info->regs[idx]) {
..	..	@@ -742,11 +1017,23 @@
742	1017	cores_info->regs[idx] = NULL;
743	1018	}
744	1019
745		-
746	1020	#if !defined(BCMBUSTYPE) \|\| (BCMBUSTYPE == SI_BUS)
747	1021	if (cores_info != &ksii_cores_info)
748	1022	#endif /* !BCMBUSTYPE \|\| (BCMBUSTYPE == SI_BUS) */
749	1023	MFREE(sii->osh, cores_info, sizeof(si_cores_info_t));
	1024	+
	1025	+#if defined(BCM_BACKPLANE_TIMEOUT)
	1026	+ if (sih->err_info) {
	1027	+ MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t));
	1028	+ sii->pub.err_info = NULL;
	1029	+ }
	1030	+#endif /* BCM_BACKPLANE_TIMEOUT */
	1031	+
	1032	+ if (sii->axi_wrapper) {
	1033	+ MFREE(sii->osh, sii->axi_wrapper,
	1034	+ (sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS));
	1035	+ sii->axi_wrapper = NULL;
	1036	+ }
750	1037
751	1038	#if !defined(BCMBUSTYPE) \|\| (BCMBUSTYPE == SI_BUS)
752	1039	if (sii != &ksii)
..	..	@@ -811,7 +1098,9 @@
811	1098
812	1099	if (CHIPTYPE(sih->socitype) == SOCI_SB)
813	1100	return sb_intflag(sih);
814		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1101	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1102	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1103	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
815	1104	return R_REG(sii->osh, ((uint32 *)(uintptr)
816	1105	(sii->oob_router + OOB_STATUSA)));
817	1106	else {
..	..	@@ -825,7 +1114,9 @@
825	1114	{
826	1115	if (CHIPTYPE(sih->socitype) == SOCI_SB)
827	1116	return sb_flag(sih);
828		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1117	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1118	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1119	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
829	1120	return ai_flag(sih);
830	1121	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
831	1122	return ub_flag(sih);
..	..	@@ -838,7 +1129,9 @@
838	1129	uint
839	1130	si_flag_alt(si_t *sih)
840	1131	{
841		- if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1132	+ if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1133	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1134	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
842	1135	return ai_flag_alt(sih);
843	1136	else {
844	1137	ASSERT(0);
..	..	@@ -851,12 +1144,31 @@
851	1144	{
852	1145	if (CHIPTYPE(sih->socitype) == SOCI_SB)
853	1146	sb_setint(sih, siflag);
854		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1147	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1148	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1149	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
855	1150	ai_setint(sih, siflag);
856	1151	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
857	1152	ub_setint(sih, siflag);
858	1153	else
859	1154	ASSERT(0);
	1155	+}
	1156	+
	1157	+uint32
	1158	+si_oobr_baseaddr(si_t *sih, bool second)
	1159	+{
	1160	+ si_info_t *sii = SI_INFO(sih);
	1161	+
	1162	+ if (CHIPTYPE(sih->socitype) == SOCI_SB)
	1163	+ return 0;
	1164	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1165	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1166	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1167	+ return (second ? sii->oob_router1 : sii->oob_router);
	1168	+ else {
	1169	+ ASSERT(0);
	1170	+ return 0;
	1171	+ }
860	1172	}
861	1173
862	1174	uint
..	..	@@ -877,7 +1189,7 @@
877	1189	return sii->curidx;
878	1190	}
879	1191
880		-void *
	1192	+volatile void *
881	1193	si_d11_switch_addrbase(si_t *sih, uint coreunit)
882	1194	{
883	1195	return si_setcore(sih, D11_CORE_ID, coreunit);
..	..	@@ -914,7 +1226,9 @@
914	1226	{
915	1227	if (CHIPTYPE(sih->socitype) == SOCI_SB)
916	1228	return sb_corevendor(sih);
917		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1229	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1230	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1231	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
918	1232	return ai_corevendor(sih);
919	1233	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
920	1234	return ub_corevendor(sih);
..	..	@@ -935,7 +1249,9 @@
935	1249	{
936	1250	if (CHIPTYPE(sih->socitype) == SOCI_SB)
937	1251	return sb_corerev(sih);
938		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1252	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1253	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1254	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
939	1255	return ai_corerev(sih);
940	1256	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
941	1257	return ub_corerev(sih);
..	..	@@ -945,6 +1261,15 @@
945	1261	}
946	1262	}
947	1263
	1264	+uint
	1265	+si_corerev_minor(si_t *sih)
	1266	+{
	1267	+ if (CHIPTYPE(sih->socitype) == SOCI_AI) {
	1268	+ return ai_corerev_minor(sih);
	1269	+ } else {
	1270	+ return 0;
	1271	+ }
	1272	+}
948	1273
949	1274	/* return index of coreid or BADIDX if not found */
950	1275	uint
..	..	@@ -954,7 +1279,6 @@
954	1279	si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
955	1280	uint found;
956	1281	uint i;
957		-
958	1282
959	1283	found = 0;
960	1284
..	..	@@ -1029,7 +1353,7 @@
1029	1353	}
1030	1354
1031	1355	/** return current register mapping */
1032		-void *
	1356	+volatile void *
1033	1357	si_coreregs(si_t *sih)
1034	1358	{
1035	1359	si_info_t *sii;
..	..	@@ -1045,7 +1369,7 @@
1045	1369	* must be called with interrupts off.
1046	1370	* Moreover, callers should keep interrupts off during switching out of and back to d11 core
1047	1371	*/
1048		-void *
	1372	+volatile void *
1049	1373	si_setcore(si_t *sih, uint coreid, uint coreunit)
1050	1374	{
1051	1375	uint idx;
..	..	@@ -1056,7 +1380,9 @@
1056	1380
1057	1381	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1058	1382	return sb_setcoreidx(sih, idx);
1059		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1383	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1384	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1385	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1060	1386	return ai_setcoreidx(sih, idx);
1061	1387	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1062	1388	return ub_setcoreidx(sih, idx);
..	..	@@ -1066,12 +1392,14 @@
1066	1392	}
1067	1393	}
1068	1394
1069		-void *
	1395	+volatile void *
1070	1396	si_setcoreidx(si_t *sih, uint coreidx)
1071	1397	{
1072	1398	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1073	1399	return sb_setcoreidx(sih, coreidx);
1074		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1400	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1401	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1402	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1075	1403	return ai_setcoreidx(sih, coreidx);
1076	1404	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1077	1405	return ub_setcoreidx(sih, coreidx);
..	..	@@ -1082,12 +1410,11 @@
1082	1410	}
1083	1411
1084	1412	/** Turn off interrupt as required by sb_setcore, before switch core */
1085		-void *
	1413	+volatile void *
1086	1414	si_switch_core(si_t sih, uint coreid, uint origidx, uint *intr_val)
1087	1415	{
1088		- void *cc;
	1416	+ volatile void *cc;
1089	1417	si_info_t *sii = SI_INFO(sih);
1090		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
1091	1418
1092	1419	if (SI_FAST(sii)) {
1093	1420	/* Overloading the origidx variable to remember the coreid,
..	..	@@ -1096,9 +1423,9 @@
1096	1423	*/
1097	1424	*origidx = coreid;
1098	1425	if (coreid == CC_CORE_ID)
1099		- return (void *)CCREGS_FAST(sii);
1100		- else if (coreid == sih->buscoretype)
1101		- return (void *)PCIEREGS(sii);
	1426	+ return (volatile void *)CCREGS_FAST(sii);
	1427	+ else if (coreid == BUSCORETYPE(sih->buscoretype))
	1428	+ return (volatile void *)PCIEREGS(sii);
1102	1429	}
1103	1430	INTR_OFF(sii, *intr_val);
1104	1431	*origidx = sii->curidx;
..	..	@@ -1113,9 +1440,8 @@
1113	1440	si_restore_core(si_t *sih, uint coreid, uint intr_val)
1114	1441	{
1115	1442	si_info_t *sii = SI_INFO(sih);
1116		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
1117	1443
1118		- if (SI_FAST(sii) && ((coreid == CC_CORE_ID) \|\| (coreid == sih->buscoretype)))
	1444	+ if (SI_FAST(sii) && ((coreid == CC_CORE_ID) \|\| (coreid == BUSCORETYPE(sih->buscoretype))))
1119	1445	return;
1120	1446
1121	1447	si_setcoreidx(sih, coreid);
..	..	@@ -1127,7 +1453,9 @@
1127	1453	{
1128	1454	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1129	1455	return sb_numaddrspaces(sih);
1130		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1456	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1457	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1458	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1131	1459	return ai_numaddrspaces(sih);
1132	1460	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1133	1461	return ub_numaddrspaces(sih);
..	..	@@ -1137,30 +1465,47 @@
1137	1465	}
1138	1466	}
1139	1467
	1468	+/* Return the address of the nth address space in the current core
	1469	+ * Arguments:
	1470	+ * sih : Pointer to struct si_t
	1471	+ * spidx : slave port index
	1472	+ * baidx : base address index
	1473	+ */
	1474	+
1140	1475	uint32
1141		-si_addrspace(si_t *sih, uint asidx)
	1476	+si_addrspace(si_t *sih, uint spidx, uint baidx)
1142	1477	{
1143	1478	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1144		- return sb_addrspace(sih, asidx);
1145		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
1146		- return ai_addrspace(sih, asidx);
	1479	+ return sb_addrspace(sih, baidx);
	1480	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1481	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1482	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1483	+ return ai_addrspace(sih, spidx, baidx);
1147	1484	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1148		- return ub_addrspace(sih, asidx);
	1485	+ return ub_addrspace(sih, baidx);
1149	1486	else {
1150	1487	ASSERT(0);
1151	1488	return 0;
1152	1489	}
1153	1490	}
1154	1491
	1492	+/* Return the size of the nth address space in the current core
	1493	+ * Arguments:
	1494	+ * sih : Pointer to struct si_t
	1495	+ * spidx : slave port index
	1496	+ * baidx : base address index
	1497	+ */
1155	1498	uint32
1156		-si_addrspacesize(si_t *sih, uint asidx)
	1499	+si_addrspacesize(si_t *sih, uint spidx, uint baidx)
1157	1500	{
1158	1501	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1159		- return sb_addrspacesize(sih, asidx);
1160		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
1161		- return ai_addrspacesize(sih, asidx);
	1502	+ return sb_addrspacesize(sih, baidx);
	1503	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1504	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1505	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1506	+ return ai_addrspacesize(sih, spidx, baidx);
1162	1507	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1163		- return ub_addrspacesize(sih, asidx);
	1508	+ return ub_addrspacesize(sih, baidx);
1164	1509	else {
1165	1510	ASSERT(0);
1166	1511	return 0;
..	..	@@ -1171,7 +1516,9 @@
1171	1516	si_coreaddrspaceX(si_t sih, uint asidx, uint32 addr, uint32 *size)
1172	1517	{
1173	1518	/* Only supported for SOCI_AI */
1174		- if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1519	+ if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1520	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1521	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1175	1522	ai_coreaddrspaceX(sih, asidx, addr, size);
1176	1523	else
1177	1524	*size = 0;
..	..	@@ -1182,7 +1529,9 @@
1182	1529	{
1183	1530	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1184	1531	return sb_core_cflags(sih, mask, val);
1185		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1532	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1533	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1534	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1186	1535	return ai_core_cflags(sih, mask, val);
1187	1536	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1188	1537	return ub_core_cflags(sih, mask, val);
..	..	@@ -1197,7 +1546,9 @@
1197	1546	{
1198	1547	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1199	1548	sb_core_cflags_wo(sih, mask, val);
1200		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1549	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1550	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1551	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1201	1552	ai_core_cflags_wo(sih, mask, val);
1202	1553	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1203	1554	ub_core_cflags_wo(sih, mask, val);
..	..	@@ -1210,7 +1561,9 @@
1210	1561	{
1211	1562	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1212	1563	return sb_core_sflags(sih, mask, val);
1213		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1564	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1565	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1566	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1214	1567	return ai_core_sflags(sih, mask, val);
1215	1568	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1216	1569	return ub_core_sflags(sih, mask, val);
..	..	@@ -1220,12 +1573,30 @@
1220	1573	}
1221	1574	}
1222	1575
	1576	+void
	1577	+si_commit(si_t *sih)
	1578	+{
	1579	+ if (CHIPTYPE(sih->socitype) == SOCI_SB)
	1580	+ sb_commit(sih);
	1581	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1582	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1583	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1584	+ ;
	1585	+ else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
	1586	+ ;
	1587	+ else {
	1588	+ ASSERT(0);
	1589	+ }
	1590	+}
	1591	+
1223	1592	bool
1224	1593	si_iscoreup(si_t *sih)
1225	1594	{
1226	1595	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1227	1596	return sb_iscoreup(sih);
1228		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1597	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1598	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1599	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1229	1600	return ai_iscoreup(sih);
1230	1601	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1231	1602	return ub_iscoreup(sih);
..	..	@@ -1239,7 +1610,9 @@
1239	1610	si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
1240	1611	{
1241	1612	/* only for AI back plane chips */
1242		- if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1613	+ if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1614	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1615	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1243	1616	return (ai_wrap_reg(sih, offset, mask, val));
1244	1617	return 0;
1245	1618	}
..	..	@@ -1272,13 +1645,20 @@
1272	1645	bcmerror = BCME_ERROR;
1273	1646	}
1274	1647	}
1275		-
1276	1648	return bcmerror;
1277	1649	}
1278		-uint
	1650	+
	1651	+void
	1652	+si_invalidate_second_bar0win(si_t *sih)
	1653	+{
	1654	+ si_info_t *sii = SI_INFO(sih);
	1655	+ sii->second_bar0win = ~0x0;
	1656	+}
	1657	+
	1658	+int
1279	1659	si_backplane_access(si_t sih, uint addr, uint size, uint val, bool read)
1280	1660	{
1281		- uint32 *r = NULL;
	1661	+ volatile uint32 *r = NULL;
1282	1662	uint32 region = 0;
1283	1663	si_info_t *sii = SI_INFO(sih);
1284	1664
..	..	@@ -1307,31 +1687,30 @@
1307	1687	* PCI_SECOND_BAR0_OFFSET : secondar bar-0 offset
1308	1688	* regoff : actual reg offset
1309	1689	*/
1310		- r = (uint32 )((char )sii->curmap + PCI_SECOND_BAR0_OFFSET + addr);
	1690	+ r = (volatile uint32 )((volatile char )sii->curmap + PCI_SECOND_BAR0_OFFSET + addr);
1311	1691
1312	1692	SI_VMSG(("si curmap %p region %x regaddr %x effective addr %p READ %d\n",
1313		- (char*)sii->curmap, region, addr, r, read));
	1693	+ (volatile char*)sii->curmap, region, addr, r, read));
1314	1694
1315	1695	switch (size) {
1316	1696	case sizeof(uint8) :
1317	1697	if (read)
1318		- val = R_REG(sii->osh, (uint8)r);
	1698	+ val = R_REG(sii->osh, (volatile uint8)r);
1319	1699	else
1320		- W_REG(sii->osh, (uint8)r, val);
	1700	+ W_REG(sii->osh, (volatile uint8)r, val);
1321	1701	break;
1322	1702	case sizeof(uint16) :
1323	1703	if (read)
1324		- val = R_REG(sii->osh, (uint16)r);
	1704	+ val = R_REG(sii->osh, (volatile uint16)r);
1325	1705	else
1326		- W_REG(sii->osh, (uint16)r, val);
	1706	+ W_REG(sii->osh, (volatile uint16)r, val);
1327	1707	break;
1328	1708	case sizeof(uint32) :
1329	1709	if (read)
1330		- val = R_REG(sii->osh, (uint32)r);
	1710	+ val = R_REG(sii->osh, (volatile uint32)r);
1331	1711	else
1332		- W_REG(sii->osh, (uint32)r, val);
	1712	+ W_REG(sii->osh, (volatile uint32)r, val);
1333	1713	break;
1334		-
1335	1714	default :
1336	1715	SI_ERROR(("Invalid size %d \n", size));
1337	1716	return (BCME_ERROR);
..	..	@@ -1345,7 +1724,9 @@
1345	1724	{
1346	1725	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1347	1726	return sb_corereg(sih, coreidx, regoff, mask, val);
1348		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1727	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1728	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1729	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1349	1730	return ai_corereg(sih, coreidx, regoff, mask, val);
1350	1731	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1351	1732	return ub_corereg(sih, coreidx, regoff, mask, val);
..	..	@@ -1353,6 +1734,12 @@
1353	1734	ASSERT(0);
1354	1735	return 0;
1355	1736	}
	1737	+}
	1738	+
	1739	+uint
	1740	+si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
	1741	+{
	1742	+ return ai_corereg_writeonly(sih, coreidx, regoff, mask, val);
1356	1743	}
1357	1744
1358	1745	/** ILP sensitive register access needs special treatment to avoid backplane stalls */
..	..	@@ -1375,7 +1762,7 @@
1375	1762	int pmustatus_offset;
1376	1763
1377	1764	/* prevent backplane stall on double write to 'ILP domain' registers in the PMU */
1378		- if (mask != 0 && sih->pmurev >= 22 &&
	1765	+ if (mask != 0 && PMUREV(sih->pmurev) >= 22 &&
1379	1766	si_pmu_is_ilp_sensitive(idx, regoff)) {
1380	1767	pmustatus_offset = AOB_ENAB(sih) ? OFFSETOF(pmuregs_t, pmustatus) :
1381	1768	OFFSETOF(chipcregs_t, pmustatus);
..	..	@@ -1396,12 +1783,14 @@
1396	1783	* For accessing registers that would need a core switch, this function will return
1397	1784	* NULL.
1398	1785	*/
1399		-uint32 *
	1786	+volatile uint32 *
1400	1787	si_corereg_addr(si_t *sih, uint coreidx, uint regoff)
1401	1788	{
1402	1789	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1403	1790	return sb_corereg_addr(sih, coreidx, regoff);
1404		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1791	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1792	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1793	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1405	1794	return ai_corereg_addr(sih, coreidx, regoff);
1406	1795	else {
1407	1796	return 0;
..	..	@@ -1413,7 +1802,9 @@
1413	1802	{
1414	1803	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1415	1804	sb_core_disable(sih, bits);
1416		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1805	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1806	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1807	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1417	1808	ai_core_disable(sih, bits);
1418	1809	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1419	1810	ub_core_disable(sih, bits);
..	..	@@ -1424,7 +1815,9 @@
1424	1815	{
1425	1816	if (CHIPTYPE(sih->socitype) == SOCI_SB)
1426	1817	sb_core_reset(sih, bits, resetbits);
1427		- else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\| (CHIPTYPE(sih->socitype) == SOCI_NAI))
	1818	+ else if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1819	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1820	+ (CHIPTYPE(sih->socitype) == SOCI_NAI))
1428	1821	ai_core_reset(sih, bits, resetbits);
1429	1822	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
1430	1823	ub_core_reset(sih, bits, resetbits);
..	..	@@ -1455,6 +1848,64 @@
1455	1848	return result;
1456	1849	}
1457	1850
	1851	+uint
	1852	+si_num_slaveports(si_t *sih, uint coreid)
	1853	+{
	1854	+ uint idx = si_findcoreidx(sih, coreid, 0);
	1855	+ uint num = 0;
	1856	+
	1857	+ if (idx != BADIDX) {
	1858	+ if (CHIPTYPE(sih->socitype) == SOCI_AI) {
	1859	+ num = ai_num_slaveports(sih, idx);
	1860	+ }
	1861	+ }
	1862	+ return num;
	1863	+}
	1864	+
	1865	+uint32
	1866	+si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx, uint core_id, uint coreunit)
	1867	+{
	1868	+ si_info_t *sii = SI_INFO(sih);
	1869	+ uint origidx = sii->curidx;
	1870	+ uint32 addr = 0x0;
	1871	+
	1872	+ if (!((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1873	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1874	+ (CHIPTYPE(sih->socitype) == SOCI_NAI)))
	1875	+ goto done;
	1876	+
	1877	+ si_setcore(sih, core_id, coreunit);
	1878	+
	1879	+ addr = ai_addrspace(sih, spidx, baidx);
	1880	+
	1881	+ si_setcoreidx(sih, origidx);
	1882	+
	1883	+done:
	1884	+ return addr;
	1885	+}
	1886	+
	1887	+uint32
	1888	+si_get_d11_slaveport_addr(si_t *sih, uint spidx, uint baidx, uint coreunit)
	1889	+{
	1890	+ si_info_t *sii = SI_INFO(sih);
	1891	+ uint origidx = sii->curidx;
	1892	+ uint32 addr = 0x0;
	1893	+
	1894	+ if (!((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	1895	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) \|\|
	1896	+ (CHIPTYPE(sih->socitype) == SOCI_NAI)))
	1897	+ goto done;
	1898	+
	1899	+ si_setcore(sih, D11_CORE_ID, coreunit);
	1900	+
	1901	+ addr = ai_addrspace(sih, spidx, baidx);
	1902	+
	1903	+ si_setcoreidx(sih, origidx);
	1904	+
	1905	+done:
	1906	+ return addr;
	1907	+}
	1908	+
1458	1909	static uint32
1459	1910	factor6(uint32 x)
1460	1911	{
..	..	@@ -1478,7 +1929,6 @@
1478	1929	{
1479	1930	return div ? clock / div : 0;
1480	1931	}
1481		-
1482	1932
1483	1933	/** calculate the speed the SI would run at given a set of clockcontrol values */
1484	1934	uint32
..	..	@@ -1562,7 +2012,6 @@
1562	2012
1563	2013	return (clock);
1564	2014	}
1565		- return 0;
1566	2015	}
1567	2016
1568	2017	/**
..	..	@@ -1575,7 +2024,13 @@
1575	2024	uint hosti = 0;
1576	2025
1577	2026	switch (CHIPID(sih->chip)) {
1578		-
	2027	+ case BCM43018_CHIP_ID:
	2028	+ case BCM43430_CHIP_ID:
	2029	+ hosti = CHIP_HOSTIF_SDIOMODE;
	2030	+ break;
	2031	+ case BCM43012_CHIP_ID:
	2032	+ hosti = CHIP_HOSTIF_SDIOMODE;
	2033	+ break;
1579	2034	CASE_BCM43602_CHIP:
1580	2035	hosti = CHIP_HOSTIF_PCIEMODE;
1581	2036	break;
..	..	@@ -1601,8 +2056,7 @@
1601	2056	hosti = CHIP_HOSTIF_PCIEMODE;
1602	2057	break;
1603	2058
1604		- case BCM4345_CHIP_ID:
1605		- case BCM43454_CHIP_ID:
	2059	+ CASE_BCM4345_CHIP:
1606	2060	if (CST4345_CHIPMODE_USB20D(sih->chipst) \|\| CST4345_CHIPMODE_HSIC(sih->chipst))
1607	2061	hosti = CHIP_HOSTIF_USBMODE;
1608	2062	else if (CST4345_CHIPMODE_SDIOD(sih->chipst))
..	..	@@ -1612,22 +2066,47 @@
1612	2066	break;
1613	2067
1614	2068	case BCM4349_CHIP_GRPID:
	2069	+ case BCM53573_CHIP_GRPID:
1615	2070	if (CST4349_CHIPMODE_SDIOD(sih->chipst))
1616	2071	hosti = CHIP_HOSTIF_SDIOMODE;
1617	2072	else if (CST4349_CHIPMODE_PCIE(sih->chipst))
1618	2073	hosti = CHIP_HOSTIF_PCIEMODE;
1619	2074	break;
	2075	+ case BCM4364_CHIP_ID:
	2076	+ if (CST4364_CHIPMODE_SDIOD(sih->chipst))
	2077	+ hosti = CHIP_HOSTIF_SDIOMODE;
	2078	+ else if (CST4364_CHIPMODE_PCIE(sih->chipst))
	2079	+ hosti = CHIP_HOSTIF_PCIEMODE;
	2080	+ break;
1620	2081	case BCM4373_CHIP_ID:
1621		- if (CST4373_CHIPMODE_USB20D(sih->chipst))
1622		- hosti = CHIP_HOSTIF_USBMODE;
1623		- else if (CST4373_CHIPMODE_SDIOD(sih->chipst))
1624		- hosti = CHIP_HOSTIF_SDIOMODE;
1625		- else if (CST4373_CHIPMODE_PCIE(sih->chipst))
1626		- hosti = CHIP_HOSTIF_PCIEMODE;
1627		- break;
	2082	+ if (CST4373_CHIPMODE_USB20D(sih->chipst))
	2083	+ hosti = CHIP_HOSTIF_USBMODE;
	2084	+ else if (CST4373_CHIPMODE_SDIOD(sih->chipst))
	2085	+ hosti = CHIP_HOSTIF_SDIOMODE;
	2086	+ else if (CST4373_CHIPMODE_PCIE(sih->chipst))
	2087	+ hosti = CHIP_HOSTIF_PCIEMODE;
	2088	+ break;
	2089	+
	2090	+ case BCM4347_CHIP_GRPID:
	2091	+ if (CST4347_CHIPMODE_SDIOD(sih->chipst))
	2092	+ hosti = CHIP_HOSTIF_SDIOMODE;
	2093	+ else if (CST4347_CHIPMODE_PCIE(sih->chipst))
	2094	+ hosti = CHIP_HOSTIF_PCIEMODE;
	2095	+ break;
	2096	+ case BCM4369_CHIP_GRPID:
	2097	+ if (CST4369_CHIPMODE_SDIOD(sih->chipst))
	2098	+ hosti = CHIP_HOSTIF_SDIOMODE;
	2099	+ else if (CST4369_CHIPMODE_PCIE(sih->chipst))
	2100	+ hosti = CHIP_HOSTIF_PCIEMODE;
	2101	+ break;
	2102	+#ifdef CHIPS_CUSTOMER_HW6
	2103	+ case BCM4368_CHIP_GRPID:
	2104	+ hosti = CHIP_HOSTIF_PCIEMODE;
	2105	+ break;
	2106	+#endif /* CHIPS_CUSTOMER_HW6 */
	2107	+
1628	2108	case BCM4350_CHIP_ID:
1629	2109	case BCM4354_CHIP_ID:
1630		- case BCM4356_CHIP_ID:
1631	2110	case BCM43556_CHIP_ID:
1632	2111	case BCM43558_CHIP_ID:
1633	2112	case BCM43566_CHIP_ID:
..	..	@@ -1654,26 +2133,15 @@
1654	2133	return hosti;
1655	2134	}
1656	2135
1657		-
1658	2136	/** set chip watchdog reset timer to fire in 'ticks' */
1659	2137	void
1660	2138	si_watchdog(si_t *sih, uint ticks)
1661	2139	{
1662	2140	uint nb, maxt;
	2141	+ uint pmu_wdt = 1;
1663	2142
1664		- if (PMUCTL_ENAB(sih)) {
1665		-
1666		-#if !defined(_CFEZ_) \|\| defined(CFG_WL)
1667		- if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) &&
1668		- (CHIPREV(sih->chiprev) == 0) && (ticks != 0)) {
1669		- si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), ~0, 0x2);
1670		- si_setcore(sih, USB20D_CORE_ID, 0);
1671		- si_core_disable(sih, 1);
1672		- si_setcore(sih, CC_CORE_ID, 0);
1673		- }
1674		-#endif
1675		-
1676		- nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);
	2143	+ if (PMUCTL_ENAB(sih) && pmu_wdt) {
	2144	+ nb = (CCREV(sih->ccrev) < 26) ? 16 : ((CCREV(sih->ccrev) >= 37) ? 32 : 24);
1677	2145	/* The mips compiler uses the sllv instruction,
1678	2146	* so we specially handle the 32-bit case.
1679	2147	*/
..	..	@@ -1694,8 +2162,13 @@
1694	2162	SPINWAIT((PMU_REG(sih, pmustatus, 0, 0) & PST_ILPFASTLPO),
1695	2163	PMU_MAX_TRANSITION_DLY);
1696	2164	}
1697		-
1698		- pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks);
	2165	+ if (sih->chip == CYW55500_CHIP_ID \|\|
	2166	+ sih->chip == CYW55560_CHIP_ID) {
	2167	+ si_corereg(sih, si_findcoreidx(sih, PMU_CORE_ID, 0),
	2168	+ OFFSETOF(pmuregs_t, pmuwatchdog), ~0, ticks);
	2169	+ } else {
	2170	+ pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks);
	2171	+ }
1699	2172	} else {
1700	2173	maxt = (1 << 28) - 1;
1701	2174	if (ticks > maxt)
..	..	@@ -1723,8 +2196,6 @@
1723	2196	return FALSE;
1724	2197	}
1725	2198
1726		-
1727		-
1728	2199	/** return the slow clock source - LPO, XTAL, or PCI */
1729	2200	static uint
1730	2201	si_slowclk_src(si_info_t *sii)
..	..	@@ -1733,14 +2204,14 @@
1733	2204
1734	2205	ASSERT(SI_FAST(sii) \|\| si_coreid(&sii->pub) == CC_CORE_ID);
1735	2206
1736		- if (sii->pub.ccrev < 6) {
	2207	+ if (CCREV(sii->pub.ccrev) < 6) {
1737	2208	if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
1738	2209	(OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &
1739	2210	PCI_CFG_GPIO_SCS))
1740	2211	return (SCC_SS_PCI);
1741	2212	else
1742	2213	return (SCC_SS_XTAL);
1743		- } else if (sii->pub.ccrev < 10) {
	2214	+ } else if (CCREV(sii->pub.ccrev) < 10) {
1744	2215	cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx);
1745	2216	ASSERT(cc);
1746	2217	return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
..	..	@@ -1761,12 +2232,12 @@
1761	2232	ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
1762	2233
1763	2234	slowclk = si_slowclk_src(sii);
1764		- if (sii->pub.ccrev < 6) {
	2235	+ if (CCREV(sii->pub.ccrev) < 6) {
1765	2236	if (slowclk == SCC_SS_PCI)
1766	2237	return (max_freq ? (PCIMAXFREQ / 64) : (PCIMINFREQ / 64));
1767	2238	else
1768	2239	return (max_freq ? (XTALMAXFREQ / 32) : (XTALMINFREQ / 32));
1769		- } else if (sii->pub.ccrev < 10) {
	2240	+ } else if (CCREV(sii->pub.ccrev) < 10) {
1770	2241	div = 4 *
1771	2242	(((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
1772	2243	if (slowclk == SCC_SS_LPO)
..	..	@@ -1804,7 +2275,7 @@
1804	2275	pll_delay += XTAL_ON_DELAY;
1805	2276
1806	2277	/* Starting with 4318 it is ILP that is used for the delays */
1807		- slowmaxfreq = si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? FALSE : TRUE, cc);
	2278	+ slowmaxfreq = si_slowclk_freq(sii, (CCREV(sii->pub.ccrev) >= 10) ? FALSE : TRUE, cc);
1808	2279
1809	2280	pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1810	2281	fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
..	..	@@ -1836,7 +2307,7 @@
1836	2307	ASSERT(cc != NULL);
1837	2308
1838	2309	/* set all Instaclk chip ILP to 1 MHz */
1839		- if (sih->ccrev >= 10)
	2310	+ if (CCREV(sih->ccrev) >= 10)
1840	2311	SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
1841	2312	(ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1842	2313
..	..	@@ -1848,9 +2319,8 @@
1848	2319	si_setcoreidx(sih, origidx);
1849	2320	}
1850	2321
1851		-
1852	2322	/** change logical "focus" to the gpio core for optimized access */
1853		-void *
	2323	+volatile void *
1854	2324	si_gpiosetcore(si_t *sih)
1855	2325	{
1856	2326	return (si_setcoreidx(sih, SI_CC_IDX));
..	..	@@ -2029,11 +2499,25 @@
2029	2499	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
2030	2500	}
2031	2501
	2502	+uint32
	2503	+si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)
	2504	+{
	2505	+ uint regoff;
	2506	+ /* gpios could be shared on router platforms */
	2507	+ if ((BUSTYPE(sih->bustype) == SI_BUS) && (val \|\| mask)) {
	2508	+ mask = priority ? (si_gpioreservation & mask) :
	2509	+ ((si_gpioreservation \| mask) & ~(si_gpioreservation));
	2510	+ val &= mask;
	2511	+ }
	2512	+ regoff = OFFSETOF(chipcregs_t, gpioeventintmask);
	2513	+ return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
	2514	+}
	2515	+
2032	2516	/* assign the gpio to an led */
2033	2517	uint32
2034	2518	si_gpioled(si_t *sih, uint32 mask, uint32 val)
2035	2519	{
2036		- if (sih->ccrev < 16)
	2520	+ if (CCREV(sih->ccrev) < 16)
2037	2521	return 0xffffffff;
2038	2522
2039	2523	/* gpio led powersave reg */
..	..	@@ -2044,7 +2528,7 @@
2044	2528	uint32
2045	2529	si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)
2046	2530	{
2047		- if (sih->ccrev < 16)
	2531	+ if (CCREV(sih->ccrev) < 16)
2048	2532	return 0xffffffff;
2049	2533
2050	2534	return (si_corereg(sih, SI_CC_IDX,
..	..	@@ -2056,7 +2540,7 @@
2056	2540	{
2057	2541	uint offs;
2058	2542
2059		- if (sih->ccrev < 20)
	2543	+ if (CCREV(sih->ccrev) < 20)
2060	2544	return 0xffffffff;
2061	2545
2062	2546	offs = (updown ? OFFSETOF(chipcregs_t, gpiopulldown) : OFFSETOF(chipcregs_t, gpiopullup));
..	..	@@ -2068,7 +2552,7 @@
2068	2552	{
2069	2553	uint offs;
2070	2554
2071		- if (sih->ccrev < 11)
	2555	+ if (CCREV(sih->ccrev) < 11)
2072	2556	return 0xffffffff;
2073	2557
2074	2558	if (regtype == GPIO_REGEVT)
..	..	@@ -2088,7 +2572,7 @@
2088	2572	{
2089	2573	uint offs;
2090	2574
2091		- if (sih->ccrev < 11)
	2575	+ if (CCREV(sih->ccrev) < 11)
2092	2576	return 0xffffffff;
2093	2577
2094	2578	offs = OFFSETOF(chipcregs_t, intmask);
..	..	@@ -2113,7 +2597,6 @@
2113	2597	si_sysmem_size(si_t *sih)
2114	2598	{
2115	2599	si_info_t *sii = SI_INFO(sih);
2116		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2117	2600	uint origidx;
2118	2601	uint intr_val = 0;
2119	2602
..	..	@@ -2170,7 +2653,6 @@
2170	2653	void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda)
2171	2654	{
2172	2655	si_info_t *sii = SI_INFO(sih);
2173		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2174	2656	uint origidx;
2175	2657	uint intr_val = 0;
2176	2658	sbsocramregs_t *regs;
..	..	@@ -2207,7 +2689,6 @@
2207	2689	si_socdevram(si_t sih, bool set, uint8 enable, uint8 protect, uint8 remap)
2208	2690	{
2209	2691	si_info_t *sii = SI_INFO(sih);
2210		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2211	2692	uint origidx;
2212	2693	uint intr_val = 0;
2213	2694	sbsocramregs_t *regs;
..	..	@@ -2255,8 +2736,7 @@
2255	2736	(1 << SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT);
2256	2737	}
2257	2738	W_REG(sii->osh, &regs->bankinfo, bankinfo);
2258		- }
2259		- else if (i == 0) {
	2739	+ } else if (i == 0) {
2260	2740	if (bankinfo & SOCRAM_BANKINFO_DEVRAMSEL_MASK) {
2261	2741	*enable = 1;
2262	2742	if (bankinfo & SOCRAM_BANKINFO_DEVRAMPRO_MASK)
..	..	@@ -2281,7 +2761,6 @@
2281	2761	si_socdevram_remap_isenb(si_t *sih)
2282	2762	{
2283	2763	si_info_t *sii = SI_INFO(sih);
2284		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2285	2764	uint origidx;
2286	2765	uint intr_val = 0;
2287	2766	sbsocramregs_t *regs;
..	..	@@ -2342,7 +2821,6 @@
2342	2821	si_socdevram_size(si_t *sih)
2343	2822	{
2344	2823	si_info_t *sii = SI_INFO(sih);
2345		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2346	2824	uint origidx;
2347	2825	uint intr_val = 0;
2348	2826	uint32 memsize = 0;
..	..	@@ -2389,7 +2867,6 @@
2389	2867	si_socdevram_remap_size(si_t *sih)
2390	2868	{
2391	2869	si_info_t *sii = SI_INFO(sih);
2392		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2393	2870	uint origidx;
2394	2871	uint intr_val = 0;
2395	2872	uint32 memsize = 0, banksz;
..	..	@@ -2455,7 +2932,6 @@
2455	2932	si_socram_size(si_t *sih)
2456	2933	{
2457	2934	si_info_t *sii = SI_INFO(sih);
2458		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2459	2935	uint origidx;
2460	2936	uint intr_val = 0;
2461	2937
..	..	@@ -2518,27 +2994,26 @@
2518	2994	return memsize;
2519	2995	}
2520	2996
2521		-
2522	2997	/** Return the TCM-RAM size of the ARMCR4 core. */
2523	2998	uint32
2524	2999	si_tcm_size(si_t *sih)
2525	3000	{
2526	3001	si_info_t *sii = SI_INFO(sih);
2527		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2528	3002	uint origidx;
2529	3003	uint intr_val = 0;
2530		- uint8 *regs;
2531		- bool wasup;
	3004	+ volatile uint8 *regs;
	3005	+ bool wasup = FALSE;
2532	3006	uint32 corecap;
2533	3007	uint memsize = 0;
	3008	+ uint banku_size = 0;
2534	3009	uint32 nab = 0;
2535	3010	uint32 nbb = 0;
2536	3011	uint32 totb = 0;
2537	3012	uint32 bxinfo = 0;
2538	3013	uint32 idx = 0;
2539		- uint32 *arm_cap_reg;
2540		- uint32 *arm_bidx;
2541		- uint32 *arm_binfo;
	3014	+ volatile uint32 *arm_cap_reg;
	3015	+ volatile uint32 *arm_bidx;
	3016	+ volatile uint32 *arm_binfo;
2542	3017
2543	3018	/* Block ints and save current core */
2544	3019	INTR_OFF(sii, intr_val);
..	..	@@ -2551,28 +3026,37 @@
2551	3026	/* Get info for determining size. If in reset, come out of reset,
2552	3027	* but remain in halt
2553	3028	*/
2554		- if (!(wasup = si_iscoreup(sih)))
2555		- si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT);
	3029	+ if (!sih->secureboot) {
	3030	+ if (!(wasup = si_iscoreup(sih)))
	3031	+ si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT);
	3032	+ }
2556	3033
2557		- arm_cap_reg = (uint32 *)(regs + SI_CR4_CAP);
	3034	+ arm_cap_reg = (volatile uint32 *)(regs + SI_CR4_CAP);
2558	3035	corecap = R_REG(sii->osh, arm_cap_reg);
2559	3036
2560	3037	nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
2561	3038	nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
2562	3039	totb = nab + nbb;
2563	3040
2564		- arm_bidx = (uint32 *)(regs + SI_CR4_BANKIDX);
2565		- arm_binfo = (uint32 *)(regs + SI_CR4_BANKINFO);
	3041	+ arm_bidx = (volatile uint32 *)(regs + SI_CR4_BANKIDX);
	3042	+ arm_binfo = (volatile uint32 *)(regs + SI_CR4_BANKINFO);
2566	3043	for (idx = 0; idx < totb; idx++) {
2567	3044	W_REG(sii->osh, arm_bidx, idx);
2568	3045
2569	3046	bxinfo = R_REG(sii->osh, arm_binfo);
2570		- memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
	3047	+ if (bxinfo & ARMCR4_BUNITSZ_MASK) {
	3048	+ banku_size = ARMCR4_BSZ_1K;
	3049	+ } else {
	3050	+ banku_size = ARMCR4_BSZ_8K;
	3051	+ }
	3052	+ memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * banku_size;
2571	3053	}
2572	3054
2573	3055	/* Return to previous state and core */
2574		- if (!wasup)
2575		- si_core_disable(sih, 0);
	3056	+ if (!sih->secureboot) {
	3057	+ if (!wasup)
	3058	+ si_core_disable(sih, 0);
	3059	+ }
2576	3060	si_setcoreidx(sih, origidx);
2577	3061
2578	3062	done:
..	..	@@ -2602,7 +3086,6 @@
2602	3086	si_socram_srmem_size(si_t *sih)
2603	3087	{
2604	3088	si_info_t *sii = SI_INFO(sih);
2605		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2606	3089	uint origidx;
2607	3090	uint intr_val = 0;
2608	3091
..	..	@@ -2611,10 +3094,6 @@
2611	3094	uint corerev;
2612	3095	uint32 coreinfo;
2613	3096	uint memsize = 0;
2614		-
2615		- if ((CHIPID(sih->chip) == BCM4334_CHIP_ID) && (CHIPREV(sih->chiprev) < 2)) {
2616		- return (32 * 1024);
2617		- }
2618	3097
2619	3098	if (CHIPID(sih->chip) == BCM43430_CHIP_ID \|\|
2620	3099	CHIPID(sih->chip) == BCM43018_CHIP_ID) {
..	..	@@ -2657,13 +3136,11 @@
2657	3136	return memsize;
2658	3137	}
2659	3138
2660		-
2661	3139	#if !defined(_CFEZ_) \|\| defined(CFG_WL)
2662	3140	void
2663	3141	si_btcgpiowar(si_t *sih)
2664	3142	{
2665	3143	si_info_t *sii = SI_INFO(sih);
2666		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2667	3144	uint origidx;
2668	3145	uint intr_val = 0;
2669	3146	chipcregs_t *cc;
..	..	@@ -2683,43 +3160,6 @@
2683	3160	ASSERT(cc != NULL);
2684	3161
2685	3162	W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) \| 0x04);
2686		-
2687		- /* restore the original index */
2688		- si_setcoreidx(sih, origidx);
2689		-
2690		- INTR_RESTORE(sii, intr_val);
2691		-}
2692		-
2693		-void
2694		-si_chipcontrl_btshd0_4331(si_t *sih, bool on)
2695		-{
2696		- si_info_t *sii = SI_INFO(sih);
2697		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
2698		- chipcregs_t *cc;
2699		- uint origidx;
2700		- uint32 val;
2701		- uint intr_val = 0;
2702		-
2703		- INTR_OFF(sii, intr_val);
2704		-
2705		- origidx = si_coreidx(sih);
2706		-
2707		- if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2708		- SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2709		- return;
2710		- }
2711		-
2712		- val = R_REG(sii->osh, &cc->chipcontrol);
2713		-
2714		- /* bt_shd0 controls are same for 4331 chiprevs 0 and 1, packages 12x9 and 12x12 */
2715		- if (on) {
2716		- /* Enable bt_shd0 on gpio4: */
2717		- val \|= (CCTRL4331_BT_SHD0_ON_GPIO4);
2718		- W_REG(sii->osh, &cc->chipcontrol, val);
2719		- } else {
2720		- val &= ~(CCTRL4331_BT_SHD0_ON_GPIO4);
2721		- W_REG(sii->osh, &cc->chipcontrol, val);
2722		- }
2723	3163
2724	3164	/* restore the original index */
2725	3165	si_setcoreidx(sih, origidx);
..	..	@@ -2759,42 +3199,6 @@
2759	3199	return val;
2760	3200	}
2761	3201
2762		-void
2763		-si_chipcontrl_epa4331(si_t *sih, bool on)
2764		-{
2765		- si_info_t *sii = SI_INFO(sih);
2766		- chipcregs_t *cc;
2767		- uint origidx = si_coreidx(sih);
2768		- uint32 val;
2769		-
2770		- if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2771		- SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2772		- return;
2773		- }
2774		- val = R_REG(sii->osh, &cc->chipcontrol);
2775		-
2776		- if (on) {
2777		- if (sih->chippkg == 9 \|\| sih->chippkg == 0xb) {
2778		- val \|= (CCTRL4331_EXTPA_EN \| CCTRL4331_EXTPA_ON_GPIO2_5);
2779		- /* Ext PA Controls for 4331 12x9 Package */
2780		- W_REG(sii->osh, &cc->chipcontrol, val);
2781		- } else {
2782		- /* Ext PA Controls for 4331 12x12 Package */
2783		- if (CHIPREV(sih->chiprev) > 0) {
2784		- W_REG(sii->osh, &cc->chipcontrol, val \|
2785		- (CCTRL4331_EXTPA_EN) \| (CCTRL4331_EXTPA_EN2));
2786		- } else {
2787		- W_REG(sii->osh, &cc->chipcontrol, val \| (CCTRL4331_EXTPA_EN));
2788		- }
2789		- }
2790		- } else {
2791		- val &= ~(CCTRL4331_EXTPA_EN \| CCTRL4331_EXTPA_EN2 \| CCTRL4331_EXTPA_ON_GPIO2_5);
2792		- W_REG(sii->osh, &cc->chipcontrol, val);
2793		- }
2794		-
2795		- si_setcoreidx(sih, origidx);
2796		-}
2797		-
2798	3202	/** switch muxed pins, on: SROM, off: FEMCTRL. Called for a family of ac chips, not just 4360. */
2799	3203	void
2800	3204	si_chipcontrl_srom4360(si_t *sih, bool on)
..	..	@@ -2824,141 +3228,41 @@
2824	3228	si_setcoreidx(sih, origidx);
2825	3229	}
2826	3230
	3231	+/**
	3232	+ * The SROM clock is derived from the backplane clock. 4365 (200Mhz) and 43684 (240Mhz) have a fast
	3233	+ * backplane clock that requires a higher-than-POR-default clock divisor ratio for the SROM clock.
	3234	+ */
2827	3235	void
2828		-si_clk_srom4365(si_t *sih)
	3236	+si_srom_clk_set(si_t *sih)
2829	3237	{
2830	3238	si_info_t *sii = SI_INFO(sih);
2831	3239	chipcregs_t *cc;
2832	3240	uint origidx = si_coreidx(sih);
2833	3241	uint32 val;
	3242	+ uint32 divisor = 1;
2834	3243
2835	3244	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2836	3245	SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2837	3246	return;
2838	3247	}
	3248	+
2839	3249	val = R_REG(sii->osh, &cc->clkdiv2);
2840		- W_REG(sii->osh, &cc->clkdiv2, ((val&~0xf) \| 0x4));
2841		-
2842		- si_setcoreidx(sih, origidx);
2843		-}
2844		-
2845		-void
2846		-si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih)
2847		-{
2848		-#if defined(WLRSDB) && !defined(WLRSDB_DISABLED)
2849		- ai_d11rsdb_core1_alt_reg_clk_dis(sih);
2850		-#endif /* defined(WLRSDB) && !defined(WLRSDB_DISABLED) */
2851		-}
2852		-
2853		-void
2854		-si_d11rsdb_core1_alt_reg_clk_en(si_t *sih)
2855		-{
2856		-#if defined(WLRSDB) && !defined(WLRSDB_DISABLED)
2857		- ai_d11rsdb_core1_alt_reg_clk_en(sih);
2858		-#endif /* defined(WLRSDB) && !defined(WLRSDB_DISABLED) */
2859		-}
2860		-
2861		-void
2862		-si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl)
2863		-{
2864		- si_info_t *sii;
2865		- chipcregs_t *cc;
2866		- uint origidx;
2867		- uint32 val;
2868		- bool sel_chip;
2869		-
2870		- sel_chip = (CHIPID(sih->chip) == BCM4331_CHIP_ID) \|\|
2871		- (CHIPID(sih->chip) == BCM43431_CHIP_ID);
2872		- sel_chip &= ((sih->chippkg == 9 \|\| sih->chippkg == 0xb));
2873		-
2874		- if (!sel_chip)
2875		- return;
2876		-
2877		- sii = SI_INFO(sih);
2878		- origidx = si_coreidx(sih);
2879		-
2880		- if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2881		- SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2882		- return;
2883		- }
2884		-
2885		- val = R_REG(sii->osh, &cc->chipcontrol);
2886		-
2887		- if (enter_wowl) {
2888		- val \|= CCTRL4331_EXTPA_EN;
2889		- W_REG(sii->osh, &cc->chipcontrol, val);
	3250	+ if (BCM4365_CHIP(sih->chip)) {
	3251	+ divisor = CLKD2_SROMDIV_192; /* divide 200 by 192 -> SPROM clock ~ 1.04Mhz */
2890	3252	} else {
2891		- val \|= (CCTRL4331_EXTPA_EN \| CCTRL4331_EXTPA_ON_GPIO2_5);
2892		- W_REG(sii->osh, &cc->chipcontrol, val);
2893		- }
2894		- si_setcoreidx(sih, origidx);
2895		-}
2896		-#endif
2897		-
2898		-uint
2899		-si_pll_reset(si_t *sih)
2900		-{
2901		- uint err = 0;
2902		-
2903		- return (err);
2904		-}
2905		-
2906		-/** Enable BT-COEX & Ex-PA for 4313 */
2907		-void
2908		-si_epa_4313war(si_t *sih)
2909		-{
2910		- si_info_t *sii = SI_INFO(sih);
2911		- chipcregs_t *cc;
2912		- uint origidx = si_coreidx(sih);
2913		-
2914		- if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2915		- SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2916		- return;
	3253	+ ASSERT(0);
2917	3254	}
2918	3255
2919		- /* EPA Fix */
2920		- W_REG(sii->osh, &cc->gpiocontrol,
2921		- R_REG(sii->osh, &cc->gpiocontrol) \| GPIO_CTRL_EPA_EN_MASK);
2922		-
	3256	+ W_REG(sii->osh, &cc->clkdiv2, ((val & ~CLKD2_SROM) \| divisor));
2923	3257	si_setcoreidx(sih, origidx);
2924	3258	}
2925		-
2926		-void
2927		-si_clk_pmu_htavail_set(si_t *sih, bool set_clear)
2928		-{
2929		-}
	3259	+#endif // endif
2930	3260
2931	3261	void
2932	3262	si_pmu_avb_clk_set(si_t sih, osl_t osh, bool set_flag)
2933	3263	{
2934	3264	}
2935	3265
2936		-/** Re-enable synth_pwrsw resource in min_res_mask for 4313 */
2937		-void
2938		-si_pmu_synth_pwrsw_4313_war(si_t *sih)
2939		-{
2940		-}
2941		-
2942		-/** WL/BT control for 4313 btcombo boards >= P250 */
2943		-void
2944		-si_btcombo_p250_4313_war(si_t *sih)
2945		-{
2946		- si_info_t *sii = SI_INFO(sih);
2947		- chipcregs_t *cc;
2948		- uint origidx = si_coreidx(sih);
2949		-
2950		- if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2951		- SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2952		- return;
2953		- }
2954		- W_REG(sii->osh, &cc->gpiocontrol,
2955		- R_REG(sii->osh, &cc->gpiocontrol) \| GPIO_CTRL_5_6_EN_MASK);
2956		-
2957		- W_REG(sii->osh, &cc->gpioouten,
2958		- R_REG(sii->osh, &cc->gpioouten) \| GPIO_CTRL_5_6_EN_MASK);
2959		-
2960		- si_setcoreidx(sih, origidx);
2961		-}
2962	3266	void
2963	3267	si_btc_enable_chipcontrol(si_t *sih)
2964	3268	{
..	..	@@ -2977,22 +3281,13 @@
2977	3281
2978	3282	si_setcoreidx(sih, origidx);
2979	3283	}
2980		-void
2981		-si_btcombo_43228_war(si_t *sih)
	3284	+
	3285	+/** cache device removed state */
	3286	+void si_set_device_removed(si_t *sih, bool status)
2982	3287	{
2983	3288	si_info_t *sii = SI_INFO(sih);
2984		- chipcregs_t *cc;
2985		- uint origidx = si_coreidx(sih);
2986	3289
2987		- if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
2988		- SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
2989		- return;
2990		- }
2991		-
2992		- W_REG(sii->osh, &cc->gpioouten, GPIO_CTRL_7_6_EN_MASK);
2993		- W_REG(sii->osh, &cc->gpioout, GPIO_OUT_7_EN_MASK);
2994		-
2995		- si_setcoreidx(sih, origidx);
	3290	+ sii->device_removed = status;
2996	3291	}
2997	3292
2998	3293	/** check if the device is removed */
..	..	@@ -3000,6 +3295,11 @@
3000	3295	si_deviceremoved(si_t *sih)
3001	3296	{
3002	3297	uint32 w;
	3298	+ si_info_t *sii = SI_INFO(sih);
	3299	+
	3300	+ if (sii->device_removed) {
	3301	+ return TRUE;
	3302	+ }
3003	3303
3004	3304	switch (BUSTYPE(sih->bustype)) {
3005	3305	case PCI_BUS:
..	..	@@ -3013,9 +3313,20 @@
3013	3313	}
3014	3314
3015	3315	bool
	3316	+si_is_warmboot(void)
	3317	+{
	3318	+
	3319	+#ifdef BCMULP
	3320	+ return (boot_type == WARM_BOOT);
	3321	+#else
	3322	+ return FALSE;
	3323	+#endif // endif
	3324	+}
	3325	+
	3326	+bool
3016	3327	si_is_sprom_available(si_t *sih)
3017	3328	{
3018		- if (sih->ccrev >= 31) {
	3329	+ if (CCREV(sih->ccrev) >= 31) {
3019	3330	si_info_t *sii;
3020	3331	uint origidx;
3021	3332	chipcregs_t *cc;
..	..	@@ -3034,52 +3345,35 @@
3034	3345	}
3035	3346
3036	3347	switch (CHIPID(sih->chip)) {
3037		- case BCM4312_CHIP_ID:
3038		- return ((sih->chipst & CST4312_SPROM_OTP_SEL_MASK) != CST4312_OTP_SEL);
3039		- case BCM4325_CHIP_ID:
3040		- return (sih->chipst & CST4325_SPROM_SEL) != 0;
3041		- case BCM4322_CHIP_ID: case BCM43221_CHIP_ID: case BCM43231_CHIP_ID:
3042		- case BCM43222_CHIP_ID: case BCM43111_CHIP_ID: case BCM43112_CHIP_ID:
3043		- case BCM4342_CHIP_ID: {
3044		- uint32 spromotp;
3045		- spromotp = (sih->chipst & CST4322_SPROM_OTP_SEL_MASK) >>
3046		- CST4322_SPROM_OTP_SEL_SHIFT;
3047		- return (spromotp & CST4322_SPROM_PRESENT) != 0;
3048		- }
3049		- case BCM4329_CHIP_ID:
3050		- return (sih->chipst & CST4329_SPROM_SEL) != 0;
3051		- case BCM4315_CHIP_ID:
3052		- return (sih->chipst & CST4315_SPROM_SEL) != 0;
3053		- case BCM4319_CHIP_ID:
3054		- return (sih->chipst & CST4319_SPROM_SEL) != 0;
3055		- case BCM4336_CHIP_ID:
3056		- case BCM43362_CHIP_ID:
3057		- return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
3058		- case BCM4330_CHIP_ID:
3059		- return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
3060		- case BCM4313_CHIP_ID:
3061		- return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
3062		- case BCM4331_CHIP_ID:
3063		- case BCM43431_CHIP_ID:
3064		- return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
3065		- case BCM43239_CHIP_ID:
3066		- return ((sih->chipst & CST43239_SPROM_MASK) &&
3067		- !(sih->chipst & CST43239_SFLASH_MASK));
3068		- case BCM4324_CHIP_ID:
3069		- case BCM43242_CHIP_ID:
3070		- return ((sih->chipst & CST4324_SPROM_MASK) &&
3071		- !(sih->chipst & CST4324_SFLASH_MASK));
	3348	+ case BCM43018_CHIP_ID:
	3349	+ case BCM43430_CHIP_ID:
	3350	+ return FALSE;
3072	3351	case BCM4335_CHIP_ID:
3073		- case BCM4345_CHIP_ID:
3074		- case BCM43454_CHIP_ID:
	3352	+ CASE_BCM4345_CHIP:
3075	3353	return ((sih->chipst & CST4335_SPROM_MASK) &&
3076	3354	!(sih->chipst & CST4335_SFLASH_MASK));
3077	3355	case BCM4349_CHIP_GRPID:
3078	3356	return (sih->chipst & CST4349_SPROM_PRESENT) != 0;
	3357	+ case BCM53573_CHIP_GRPID:
	3358	+ return FALSE; /* SPROM PRESENT is not defined for 53573 as of now */
	3359	+ case BCM4364_CHIP_ID:
	3360	+ return (sih->chipst & CST4364_SPROM_PRESENT) != 0;
	3361	+ case BCM4369_CHIP_GRPID:
	3362	+ if (CHIPREV(sih->chiprev) == 0) {
	3363	+ /* WAR for 4369a0: HW4369-1729. no sprom, default to otp always. */
	3364	+ return 0;
	3365	+ } else {
	3366	+ return (sih->chipst & CST4369_SPROM_PRESENT) != 0;
	3367	+ }
	3368	+#ifdef CHIPS_CUSTOMER_HW6
	3369	+ case BCM4368_CHIP_ID:
	3370	+ return FALSE;
	3371	+#endif /* CHIPS_CUSTOMER_HW6 */
	3372	+ case BCM4347_CHIP_GRPID:
	3373	+ return (sih->chipst & CST4347_SPROM_PRESENT) != 0;
3079	3374	break;
3080	3375	case BCM4350_CHIP_ID:
3081	3376	case BCM4354_CHIP_ID:
3082		- case BCM4356_CHIP_ID:
3083	3377	case BCM43556_CHIP_ID:
3084	3378	case BCM43558_CHIP_ID:
3085	3379	case BCM43566_CHIP_ID:
..	..	@@ -3092,15 +3386,15 @@
3092	3386	return (sih->chipst & CST43602_SPROM_PRESENT) != 0;
3093	3387	case BCM43131_CHIP_ID:
3094	3388	case BCM43217_CHIP_ID:
3095		- case BCM43227_CHIP_ID:
3096		- case BCM43228_CHIP_ID:
3097	3389	case BCM43428_CHIP_ID:
3098	3390	return (sih->chipst & CST43228_OTP_PRESENT) != CST43228_OTP_PRESENT;
	3391	+ case BCM4373_CHIP_ID:
	3392	+ case BCM43012_CHIP_ID:
	3393	+ return FALSE;
3099	3394	default:
3100	3395	return TRUE;
3101	3396	}
3102	3397	}
3103		-
3104	3398
3105	3399	uint32 si_get_sromctl(si_t *sih)
3106	3400	{
..	..	@@ -3156,7 +3450,6 @@
3156	3450	uint origidx, intr_val = 0;
3157	3451	uint ret_val;
3158	3452	si_info_t *sii = SI_INFO(sih);
3159		- si_cores_info_t cores_info = (si_cores_info_t )sii->cores_info;
3160	3453
3161	3454	origidx = si_coreidx(sih);
3162	3455
..	..	@@ -3171,7 +3464,6 @@
3171	3464	return ret_val;
3172	3465	}
3173	3466
3174		-
3175	3467	/* cleanup the timer from the host when ARM is been halted
3176	3468	* without a chance for ARM cleanup its resources
3177	3469	* If left not cleanup, Intr from a software timer can still
..	..	@@ -3183,8 +3475,7 @@
3183	3475	uint32 mask;
3184	3476
3185	3477	mask = PRRT_REQ_ACTIVE \| PRRT_INTEN \| PRRT_HT_REQ;
3186		- if (CHIPID(sih->chip) != BCM4328_CHIP_ID)
3187		- mask <<= 14;
	3478	+ mask <<= 14;
3188	3479	/* clear mask bits */
3189	3480	pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0);
3190	3481	/* readback to ensure write completes */
..	..	@@ -3197,67 +3488,17 @@
3197	3488	{
3198	3489	}
3199	3490
3200		-
3201		-#ifdef SURVIVE_PERST_ENAB
3202		-static uint32
3203		-si_pcie_survive_perst(si_t *sih, uint32 mask, uint32 val)
3204		-{
3205		- si_info_t *sii;
3206		-
3207		- sii = SI_INFO(sih);
3208		-
3209		- if (!PCIE(sii))
3210		- return (0);
3211		-
3212		- return pcie_survive_perst(sii->pch, mask, val);
3213		-}
3214		-
3215		-static void
3216		-si_watchdog_reset(si_t *sih)
3217		-{
3218		- uint32 i;
3219		-
3220		- /* issue a watchdog reset */
3221		- pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, 2, 2);
3222		- /* do busy wait for 20ms */
3223		- for (i = 0; i < 2000; i++) {
3224		- OSL_DELAY(10);
3225		- }
3226		-}
3227		-#endif /* SURVIVE_PERST_ENAB */
3228		-
	3491	+/* Caller of this function should make sure is on PCIE core
	3492	+ * Used in pciedev.c.
	3493	+ */
3229	3494	void
3230		-si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 sperst_val)
	3495	+si_pcie_disable_oobselltr(si_t *sih)
3231	3496	{
3232		-#ifdef SURVIVE_PERST_ENAB
3233		- if (BUSTYPE(sih->bustype) != PCI_BUS)
3234		- return;
3235		-
3236		- if ((CHIPID(sih->chip) != BCM4360_CHIP_ID && CHIPID(sih->chip) != BCM4352_CHIP_ID) \|\|
3237		- (CHIPREV(sih->chiprev) >= 4))
3238		- return;
3239		-
3240		- if (reset) {
3241		- si_info_t *sii = SI_INFO(sih);
3242		- uint32 bar0win, bar0win_after;
3243		-
3244		- /* save the bar0win */
3245		- bar0win = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
3246		-
3247		- si_watchdog_reset(sih);
3248		-
3249		- bar0win_after = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
3250		- if (bar0win_after != bar0win) {
3251		- SI_ERROR(("%s: bar0win before %08x, bar0win after %08x\n",
3252		- __FUNCTION__, bar0win, bar0win_after));
3253		- OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), bar0win);
3254		- }
3255		- }
3256		- if (sperst_mask) {
3257		- /* enable survive perst */
3258		- si_pcie_survive_perst(sih, sperst_mask, sperst_val);
3259		- }
3260		-#endif /* SURVIVE_PERST_ENAB */
	3497	+ ASSERT(si_coreid(sih) == PCIE2_CORE_ID);
	3498	+ if (PCIECOREREV(sih->buscorerev) >= 23)
	3499	+ si_wrapperreg(sih, AI_OOBSELIND74, ~0, 0);
	3500	+ else
	3501	+ si_wrapperreg(sih, AI_OOBSELIND30, ~0, 0);
3261	3502	}
3262	3503
3263	3504	void
..	..	@@ -3285,11 +3526,117 @@
3285	3526	{
3286	3527	}
3287	3528
	3529	+#if defined(AXI_TIMEOUTS) \|\| defined(BCM_BACKPLANE_TIMEOUT)
	3530	+uint32
	3531	+si_clear_backplane_to_per_core(si_t sih, uint coreid, uint coreunit, void wrap)
	3532	+{
	3533	+ if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	3534	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) {
	3535	+ return ai_clear_backplane_to_per_core(sih, coreid, coreunit, wrap);
	3536	+ }
3288	3537
	3538	+ return AXI_WRAP_STS_NONE;
	3539	+}
	3540	+#endif /* AXI_TIMEOUTS \|\| BCM_BACKPLANE_TIMEOUT */
	3541	+
	3542	+uint32
	3543	+si_clear_backplane_to(si_t *sih)
	3544	+{
	3545	+ if ((CHIPTYPE(sih->socitype) == SOCI_AI) \|\|
	3546	+ (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) {
	3547	+ return ai_clear_backplane_to(sih);
	3548	+ }
	3549	+
	3550	+ return 0;
	3551	+}
	3552	+
	3553	+void
	3554	+si_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout_exp, uint32 cid)
	3555	+{
	3556	+#if defined(AXI_TIMEOUTS) \|\| defined(BCM_BACKPLANE_TIMEOUT)
	3557	+ /* Enable only for AXI */
	3558	+ if (CHIPTYPE(sih->socitype) != SOCI_AI) {
	3559	+ return;
	3560	+ }
	3561	+
	3562	+ ai_update_backplane_timeouts(sih, enable, timeout_exp, cid);
	3563	+#endif /* AXI_TIMEOUTS \|\| BCM_BACKPLANE_TIMEOUT */
	3564	+}
	3565	+
	3566	+/*
	3567	+ * This routine adds the AXI timeouts for
	3568	+ * chipcommon, pcie and ARM slave wrappers
	3569	+ */
	3570	+void
	3571	+si_slave_wrapper_add(si_t *sih)
	3572	+{
	3573	+#if defined(AXI_TIMEOUTS) \|\| defined(BCM_BACKPLANE_TIMEOUT)
	3574	+ uint32 axi_to = 0;
	3575	+
	3576	+ /* Enable only for AXI */
	3577	+ if ((CHIPTYPE(sih->socitype) != SOCI_AI) &&
	3578	+ (CHIPTYPE(sih->socitype) != SOCI_DVTBUS)) {
	3579	+ return;
	3580	+ }
	3581	+
	3582	+ if (CHIPID(sih->chip) == BCM4345_CHIP_ID && CHIPREV(sih->chiprev) >= 6) {
	3583	+ si_info_t *sii = SI_INFO(sih);
	3584	+
	3585	+ int wrapper_idx = (int)sii->axi_num_wrappers - 1;
	3586	+
	3587	+ ASSERT(wrapper_idx >= 0); /* axi_wrapper[] not initialised */
	3588	+ do {
	3589	+ if (sii->axi_wrapper[wrapper_idx].wrapper_type == AI_SLAVE_WRAPPER &&
	3590	+ sii->axi_wrapper[wrapper_idx].cid == 0xfff) {
	3591	+ sii->axi_wrapper[wrapper_idx].wrapper_addr = 0x1810b000;
	3592	+ break;
	3593	+ }
	3594	+ } while (wrapper_idx-- > 0);
	3595	+ ASSERT(wrapper_idx >= 0); /* all addresses valid for the chiprev under test */
	3596	+ }
	3597	+
	3598	+ if (BCM4347_CHIP(sih->chip)) {
	3599	+ axi_to = AXI_TO_VAL_4347;
	3600	+ }
	3601	+ else {
	3602	+ axi_to = AXI_TO_VAL;
	3603	+ }
	3604	+
	3605	+ /* All required slave wrappers are added in ai_scan */
	3606	+ ai_update_backplane_timeouts(sih, TRUE, axi_to, 0);
	3607	+
	3608	+#ifdef DISABLE_PCIE2_AXI_TIMEOUT
	3609	+ ai_update_backplane_timeouts(sih, FALSE, 0, PCIE_CORE_ID);
	3610	+ ai_update_backplane_timeouts(sih, FALSE, 0, PCIE2_CORE_ID);
	3611	+#endif // endif
	3612	+
	3613	+#endif /* AXI_TIMEOUTS \|\| BCM_BACKPLANE_TIMEOUT */
	3614	+
	3615	+}
3289	3616
3290	3617	void
3291	3618	si_pll_sr_reinit(si_t *sih)
3292	3619	{
	3620	+}
	3621	+
	3622	+/* Programming d11 core oob settings for 4364
	3623	+ * WARs for HW4364-237 and HW4364-166
	3624	+*/
	3625	+void
	3626	+si_config_4364_d11_oob(si_t *sih, uint coreid)
	3627	+{
	3628	+ uint save_idx;
	3629	+
	3630	+ save_idx = si_coreidx(sih);
	3631	+ si_setcore(sih, coreid, 0);
	3632	+ si_wrapperreg(sih, AI_OOBSELINC30, ~0, 0x81828180);
	3633	+ si_wrapperreg(sih, AI_OOBSELINC74, ~0, 0x87868183);
	3634	+ si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, 0x84858484);
	3635	+ si_setcore(sih, coreid, 1);
	3636	+ si_wrapperreg(sih, AI_OOBSELINC30, ~0, 0x81828180);
	3637	+ si_wrapperreg(sih, AI_OOBSELINC74, ~0, 0x87868184);
	3638	+ si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, 0x84868484);
	3639	+ si_setcoreidx(sih, save_idx);
3293	3640	}
3294	3641
3295	3642	void
..	..	@@ -3301,6 +3648,7 @@
3301	3648	/* disable PLL open loop operation */
3302	3649	switch (CHIPID(sih->chip)) {
3303	3650	#ifdef SAVERESTORE
	3651	+ case BCM43018_CHIP_ID:
3304	3652	case BCM43430_CHIP_ID:
3305	3653	if (SR_ENAB() && sr_isenab(sih)) {
3306	3654	/* read back the pll openloop state */
..	..	@@ -3314,9 +3662,268 @@
3314	3662	}
3315	3663	break;
3316	3664	#endif /* SAVERESTORE */
	3665	+ case BCM4347_CHIP_GRPID:
	3666	+ case BCM4369_CHIP_GRPID:
	3667	+ si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
	3668	+ PMU_CC1_ENABLE_CLOSED_LOOP_MASK, PMU_CC1_ENABLE_CLOSED_LOOP);
	3669	+ break;
3317	3670	default:
3318	3671	/* any unsupported chip bail */
3319	3672	return;
3320	3673	}
3321		-#endif
	3674	+#endif // endif
	3675	+}
	3676	+
	3677	+#if defined(BCMSRPWR) && !defined(BCMSRPWR_DISABLED)
	3678	+bool _bcmsrpwr = TRUE;
	3679	+#else
	3680	+bool _bcmsrpwr = FALSE;
	3681	+#endif // endif
	3682	+
	3683	+#define PWRREQ_OFFSET(sih) OFFSETOF(chipcregs_t, powerctl)
	3684	+
	3685	+static void
	3686	+si_corereg_pciefast_write(si_t *sih, uint regoff, uint val)
	3687	+{
	3688	+ volatile uint32 *r = NULL;
	3689	+ si_info_t *sii = SI_INFO(sih);
	3690	+
	3691	+ ASSERT((BUSTYPE(sih->bustype) == PCI_BUS));
	3692	+
	3693	+ r = (volatile uint32 )((volatile char )sii->curmap +
	3694	+ PCI_16KB0_PCIREGS_OFFSET + regoff);
	3695	+
	3696	+ W_REG(sii->osh, r, val);
	3697	+}
	3698	+
	3699	+static uint
	3700	+si_corereg_pciefast_read(si_t *sih, uint regoff)
	3701	+{
	3702	+ volatile uint32 *r = NULL;
	3703	+ si_info_t *sii = SI_INFO(sih);
	3704	+
	3705	+ ASSERT((BUSTYPE(sih->bustype) == PCI_BUS));
	3706	+
	3707	+ r = (volatile uint32 )((volatile char )sii->curmap +
	3708	+ PCI_16KB0_PCIREGS_OFFSET + regoff);
	3709	+
	3710	+ return R_REG(sii->osh, r);
	3711	+}
	3712	+
	3713	+uint32
	3714	+si_srpwr_request(si_t *sih, uint32 mask, uint32 val)
	3715	+{
	3716	+ uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ?
	3717	+ OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih);
	3718	+ uint32 mask2 = mask;
	3719	+ uint32 val2 = val;
	3720	+ volatile uint32 fast_srpwr_addr = (volatile uint32 )((uintptr)SI_ENUM_BASE(sih)
	3721	+ + (uintptr)offset);
	3722	+
	3723	+ if (mask \|\| val) {
	3724	+ mask <<= SRPWR_REQON_SHIFT;
	3725	+ val <<= SRPWR_REQON_SHIFT;
	3726	+
	3727	+ /* Return if requested power request is already set */
	3728	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3729	+ r = R_REG(OSH_NULL, fast_srpwr_addr);
	3730	+ } else {
	3731	+ r = si_corereg_pciefast_read(sih, offset);
	3732	+ }
	3733	+
	3734	+ if ((r & mask) == val) {
	3735	+ return r;
	3736	+ }
	3737	+
	3738	+ r = (r & ~mask) \| val;
	3739	+
	3740	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3741	+ W_REG(OSH_NULL, fast_srpwr_addr, r);
	3742	+ r = R_REG(OSH_NULL, fast_srpwr_addr);
	3743	+ } else {
	3744	+ si_corereg_pciefast_write(sih, offset, r);
	3745	+ r = si_corereg_pciefast_read(sih, offset);
	3746	+ }
	3747	+
	3748	+ if (val2) {
	3749	+ if ((r & (mask2 << SRPWR_STATUS_SHIFT)) ==
	3750	+ (val2 << SRPWR_STATUS_SHIFT)) {
	3751	+ return r;
	3752	+ }
	3753	+ si_srpwr_stat_spinwait(sih, mask2, val2);
	3754	+ }
	3755	+ } else {
	3756	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3757	+ r = R_REG(OSH_NULL, fast_srpwr_addr);
	3758	+ } else {
	3759	+ r = si_corereg_pciefast_read(sih, offset);
	3760	+ }
	3761	+ }
	3762	+
	3763	+ return r;
	3764	+}
	3765	+
	3766	+uint32
	3767	+si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val)
	3768	+{
	3769	+ uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ?
	3770	+ OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih);
	3771	+ volatile uint32 fast_srpwr_addr = (volatile uint32 )((uintptr)SI_ENUM_BASE(sih)
	3772	+ + (uintptr)offset);
	3773	+
	3774	+ ASSERT(mask);
	3775	+ ASSERT(val);
	3776	+
	3777	+ /* spinwait on pwrstatus */
	3778	+ mask <<= SRPWR_STATUS_SHIFT;
	3779	+ val <<= SRPWR_STATUS_SHIFT;
	3780	+
	3781	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3782	+ SPINWAIT(((R_REG(OSH_NULL, fast_srpwr_addr) & mask) != val),
	3783	+ PMU_MAX_TRANSITION_DLY);
	3784	+ r = R_REG(OSH_NULL, fast_srpwr_addr) & mask;
	3785	+ ASSERT(r == val);
	3786	+ } else {
	3787	+ SPINWAIT(((si_corereg_pciefast_read(sih, offset) & mask) != val),
	3788	+ PMU_MAX_TRANSITION_DLY);
	3789	+ r = si_corereg_pciefast_read(sih, offset) & mask;
	3790	+ ASSERT(r == val);
	3791	+ }
	3792	+
	3793	+ r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK(sih);
	3794	+
	3795	+ return r;
	3796	+}
	3797	+
	3798	+uint32
	3799	+si_srpwr_stat(si_t *sih)
	3800	+{
	3801	+ uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ?
	3802	+ OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih);
	3803	+ uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx;
	3804	+
	3805	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3806	+ r = si_corereg(sih, cidx, offset, 0, 0);
	3807	+ } else {
	3808	+ r = si_corereg_pciefast_read(sih, offset);
	3809	+ }
	3810	+
	3811	+ r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK(sih);
	3812	+
	3813	+ return r;
	3814	+}
	3815	+
	3816	+uint32
	3817	+si_srpwr_domain(si_t *sih)
	3818	+{
	3819	+ uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ?
	3820	+ OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih);
	3821	+ uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx;
	3822	+
	3823	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3824	+ r = si_corereg(sih, cidx, offset, 0, 0);
	3825	+ } else {
	3826	+ r = si_corereg_pciefast_read(sih, offset);
	3827	+ }
	3828	+
	3829	+ r = (r >> SRPWR_DMN_ID_SHIFT) & SRPWR_DMN_ID_MASK;
	3830	+
	3831	+ return r;
	3832	+}
	3833	+
	3834	+uint32
	3835	+si_srpwr_domain_all_mask(si_t *sih)
	3836	+{
	3837	+ uint32 mask = SRPWR_DMN0_PCIE_MASK \|
	3838	+ SRPWR_DMN1_ARMBPSD_MASK \|
	3839	+ SRPWR_DMN2_MACAUX_MASK \|
	3840	+ SRPWR_DMN3_MACMAIN_MASK;
	3841	+
	3842	+ if (si_scan_core_present(sih)) {
	3843	+ mask \|= SRPWR_DMN4_MACSCAN_MASK;
	3844	+ }
	3845	+
	3846	+ return mask;
	3847	+}
	3848	+
	3849	+/* Utility API to read/write the raw registers with absolute address.
	3850	+ * This function can be invoked from either FW or host driver.
	3851	+ */
	3852	+uint32
	3853	+si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req)
	3854	+{
	3855	+ si_info_t *sii = SI_INFO(sih);
	3856	+ uint32 address_space = reg & ~0xFFF;
	3857	+ volatile uint32 * addr = (void*)(uintptr)(reg);
	3858	+ uint32 prev_value = 0;
	3859	+ uint32 cfg_reg = 0;
	3860	+
	3861	+ if (sii == NULL) {
	3862	+ return 0;
	3863	+ }
	3864	+
	3865	+ /* No need to translate the absolute address on SI bus */
	3866	+ if (BUSTYPE(sih->bustype) == SI_BUS) {
	3867	+ goto skip_cfg;
	3868	+ }
	3869	+
	3870	+ /* This API supports only the PCI host interface */
	3871	+ if (BUSTYPE(sih->bustype) != PCI_BUS) {
	3872	+ return ID32_INVALID;
	3873	+ }
	3874	+
	3875	+ if (PCIE_GEN2(sii)) {
	3876	+ /* Use BAR0 Secondary window is PCIe Gen2.
	3877	+ * Set the secondary BAR0 Window to current register of interest
	3878	+ */
	3879	+ addr = (volatile uint32)(((volatile uint8)sii->curmap) +
	3880	+ PCI_SEC_BAR0_WIN_OFFSET + (reg & 0xfff));
	3881	+ cfg_reg = PCIE2_BAR0_CORE2_WIN;
	3882	+
	3883	+ } else {
	3884	+ /* PCIe Gen1 do not have secondary BAR0 window.
	3885	+ * reuse the BAR0 WIN2
	3886	+ */
	3887	+ addr = (volatile uint32)(((volatile uint8)sii->curmap) +
	3888	+ PCI_BAR0_WIN2_OFFSET + (reg & 0xfff));
	3889	+ cfg_reg = PCI_BAR0_WIN2;
	3890	+ }
	3891	+
	3892	+ prev_value = OSL_PCI_READ_CONFIG(sii->osh, cfg_reg, 4);
	3893	+
	3894	+ if (prev_value != address_space) {
	3895	+ OSL_PCI_WRITE_CONFIG(sii->osh, cfg_reg,
	3896	+ sizeof(uint32), address_space);
	3897	+ } else {
	3898	+ prev_value = 0;
	3899	+ }
	3900	+
	3901	+skip_cfg:
	3902	+ if (wrire_req) {
	3903	+ W_REG(sii->osh, addr, val);
	3904	+ } else {
	3905	+ val = R_REG(sii->osh, addr);
	3906	+ }
	3907	+
	3908	+ if (prev_value) {
	3909	+ /* Restore BAR0 WIN2 for PCIE GEN1 devices */
	3910	+ OSL_PCI_WRITE_CONFIG(sii->osh,
	3911	+ cfg_reg, sizeof(uint32), prev_value);
	3912	+ }
	3913	+
	3914	+ return val;
	3915	+}
	3916	+
	3917	+uint8
	3918	+si_lhl_ps_mode(si_t *sih)
	3919	+{
	3920	+ si_info_t *sii = SI_INFO(sih);
	3921	+ return sii->lhl_ps_mode;
	3922	+}
	3923	+
	3924	+bool
	3925	+BCMRAMFN(si_scan_core_present)(si_t *sih)
	3926	+{
	3927	+ return ((si_numcoreunits(sih, D11_CORE_ID) >= 2) &&
	3928	+ (si_numcoreunits(sih, SR_CORE_ID) > 4));
3322	3929	}