add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/sdioh.h
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@@ -1,16 +1,17 @@
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-/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * SDIO Host Controller Spec header file
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  * Register map and definitions for the Standard Host Controller
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  *
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- * Copyright (C) 1999-2019, Broadcom Corporation
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- * 
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+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
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+ *
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+ * Copyright (C) 1999-2017, Broadcom Corporation
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+ *
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  *      Unless you and Broadcom execute a separate written software license
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  * agreement governing use of this software, this software is licensed to you
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  * under the terms of the GNU General Public License version 2 (the "GPL"),
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  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
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  * following added to such license:
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- * 
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+ *
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  *      As a special exception, the copyright holders of this software give you
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  * permission to link this software with independent modules, and to copy and
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  * distribute the resulting executable under terms of your choice, provided that
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@@ -18,7 +19,7 @@
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  * the license of that module.  An independent module is a module which is not
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  * derived from this software.  The special exception does not apply to any
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  * modifications of the software.
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- * 
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+ *
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  *      Notwithstanding the above, under no circumstances may you combine this
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  * software in any way with any other Broadcom software provided under a license
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  * other than the GPL, without Broadcom's express prior written consent.
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@@ -97,7 +98,6 @@
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 #define SD3_Tuning_Info_Register 0x0EC
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 #define SD3_WL_BT_reset_register 0x0F0
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-
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 /* preset value indices */
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 #define SD3_PRESETVAL_INITIAL_IX	0
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 #define SD3_PRESETVAL_DESPEED_IX	1
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@@ -141,7 +141,6 @@
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 #define SDIO_OCR_READ_FAIL	(2)
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-
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 #define CAP_ASYNCINT_SUP_M	BITFIELD_MASK(1)
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 #define CAP_ASYNCINT_SUP_S	29
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@@ -184,6 +183,10 @@
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 #define CAP3_RETUNING_MODES_M	BITFIELD_MASK(2)
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 #define CAP3_RETUNING_MODES_S	(46 - CAP3_MSBits_OFFSET)
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+#define CAP3_RETUNING_TC_DISABLED	(0x0)
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+#define CAP3_RETUNING_TC_1024S		(0xB)
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+#define CAP3_RETUNING_TC_OTHER		(0xF)
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+
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 #define CAP3_CLK_MULT_M		BITFIELD_MASK(8)
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 #define CAP3_CLK_MULT_S		(48 - CAP3_MSBits_OFFSET)
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