add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/sbpcmcia.h
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@@ -1,15 +1,16 @@
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-/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
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  *
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- * Copyright (C) 1999-2019, Broadcom Corporation
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- * 
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+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
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+ *
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+ * Copyright (C) 1999-2017, Broadcom Corporation
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+ *
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  *      Unless you and Broadcom execute a separate written software license
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  * agreement governing use of this software, this software is licensed to you
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  * under the terms of the GNU General Public License version 2 (the "GPL"),
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  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
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  * following added to such license:
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- * 
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+ *
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  *      As a special exception, the copyright holders of this software give you
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  * permission to link this software with independent modules, and to copy and
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  * distribute the resulting executable under terms of your choice, provided that
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@@ -17,7 +18,7 @@
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  * the license of that module.  An independent module is a module which is not
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  * derived from this software.  The special exception does not apply to any
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  * modifications of the software.
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- * 
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+ *
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  *      Notwithstanding the above, under no circumstances may you combine this
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  * software in any way with any other Broadcom software provided under a license
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  * other than the GPL, without Broadcom's express prior written consent.
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@@ -25,7 +26,7 @@
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  *
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  * <<Broadcom-WL-IPTag/Open:>>
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  *
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- * $Id: sbpcmcia.h 521344 2014-12-17 10:03:55Z $
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+ * $Id: sbpcmcia.h 647676 2016-07-07 02:59:05Z $
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  */
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 #ifndef	_SBPCMCIA_H
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@@ -61,12 +62,10 @@
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 #define	COR_BLREN		0x01
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 #define	COR_FUNEN		0x01
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-
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 #define	PCICIA_FCSR		(2 / 2)
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 #define	PCICIA_PRR		(4 / 2)
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 #define	PCICIA_SCR		(6 / 2)
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 #define	PCICIA_ESR		(8 / 2)
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-
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 #define PCM_MEMOFF		0x0000
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 #define F0_MEMOFF		0x1000
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@@ -106,6 +105,34 @@
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 #define	SRI_BLANK		0x04
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 #define	SRI_OTP			0x80
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+#define SROM16K_BANK_SEL_MASK		(3 << 11)
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+#define SROM16K_BANK_SHFT_MASK		11
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+#define SROM16K_ADDR_SEL_MASK	((1 << SROM16K_BANK_SHFT_MASK) - 1)
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+#define SROM_PRSNT_MASK		0x1
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+#define SROM_SUPPORT_SHIFT_MASK 30
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+#define SROM_SUPPORTED	(0x1 << SROM_SUPPORT_SHIFT_MASK)
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+#define SROM_SIZE_MASK    0x00000006
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+#define SROM_SIZE_2K	2
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+#define SROM_SIZE_512	1
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+#define SROM_SIZE_128	0
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+#define SROM_SIZE_SHFT_MASK  1
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+
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+/* Standard tuples we know about */
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+
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+#define CISTPL_NULL		0x00
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+#define	CISTPL_END		0xff		/* End of the CIS tuple chain */
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+#define CISTPL_OFFSET           0xC0
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+
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+#define	CISTPL_BRCM_HNBU	0x80
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+
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+#define HNBU_BOARDREV		0x02	/* One byte board revision */
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+
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+#define HNBU_BOARDTYPE		0x1b	/* 2 bytes; boardtype */
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+
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+#define HNBU_HNBUCIS		0x1d	/* what follows is proprietary HNBU CIS format */
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+
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+#define HNBU_CUSTOM1		0x82	/* 4 byte; For non-BRCM post-mfg additions */
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+#define HNBU_CUSTOM2		0x83	/* Reserved; For non-BRCM post-mfg additions */
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 /* sbtmstatelow */
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 #define SBTML_INT_ACK		0x40000		/* ack the sb interrupt */
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@@ -113,5 +140,4 @@
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 /* sbtmstatehigh */
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 #define SBTMH_INT_STATUS	0x40000		/* sb interrupt status */
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-
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 #endif	/* _SBPCMCIA_H */