~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,4 +1,3 @@
1		-/* SPDX-License-Identifier: GPL-2.0 */
2	1	/*
3	2	* SiliconBackplane Chipcommon core hardware definitions.
4	3	*
..	..	@@ -6,16 +5,18 @@
6	5	* JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
7	6	* GPIO interface, extbus, and support for serial and parallel flashes.
8	7	*
9		- * $Id: sbchipc.h 722050 2019-08-21 02:24:57Z $
	8	+ * $Id: sbchipc.h 701163 2017-05-23 22:21:03Z $
10	9	*
11		- * Copyright (C) 1999-2019, Broadcom Corporation
12		- *
	10	+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
	11	+ *
	12	+ * Copyright (C) 1999-2017, Broadcom Corporation
	13	+ *
13	14	* Unless you and Broadcom execute a separate written software license
14	15	* agreement governing use of this software, this software is licensed to you
15	16	* under the terms of the GNU General Public License version 2 (the "GPL"),
16	17	* available at http://www.broadcom.com/licenses/GPLv2.php, with the
17	18	* following added to such license:
18		- *
	19	+ *
19	20	* As a special exception, the copyright holders of this software give you
20	21	* permission to link this software with independent modules, and to copy and
21	22	* distribute the resulting executable under terms of your choice, provided that
..	..	@@ -23,7 +24,7 @@
23	24	* the license of that module. An independent module is a module which is not
24	25	* derived from this software. The special exception does not apply to any
25	26	* modifications of the software.
26		- *
	27	+ *
27	28	* Notwithstanding the above, under no circumstances may you combine this
28	29	* software in any way with any other Broadcom software provided under a license
29	30	* other than the GPL, without Broadcom's express prior written consent.
..	..	@@ -44,6 +45,8 @@
44	45	#define PAD _XSTR(__LINE__)
45	46	#endif /* PAD */
46	47
	48	+#define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb)))
	49	+
47	50	/**
48	51	* In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the
49	52	* 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to
..	..	@@ -53,62 +56,74 @@
53	56	*/
54	57	typedef volatile struct {
55	58	uint32 PAD[384];
56		- uint32 pmucontrol; /* 0x600 */
57		- uint32 pmucapabilities; /* 0x604 */
58		- uint32 pmustatus; /* 0x608 */
59		- uint32 res_state; /* 0x60C */
60		- uint32 res_pending; /* 0x610 */
61		- uint32 pmutimer; /* 0x614 */
62		- uint32 min_res_mask; /* 0x618 */
63		- uint32 max_res_mask; /* 0x61C */
64		- uint32 res_table_sel; /* 0x620 */
65		- uint32 res_dep_mask;
66		- uint32 res_updn_timer;
67		- uint32 res_timer;
68		- uint32 clkstretch;
69		- uint32 pmuwatchdog;
70		- uint32 gpiosel; /* 0x638, rev >= 1 */
71		- uint32 gpioenable; /* 0x63c, rev >= 1 */
72		- uint32 res_req_timer_sel; /* 0x640 */
73		- uint32 res_req_timer; /* 0x644 */
74		- uint32 res_req_mask; /* 0x648 */
75		- uint32 PAD; /* 0x64C */
76		- uint32 chipcontrol_addr; /* 0x650 */
77		- uint32 chipcontrol_data; /* 0x654 */
78		- uint32 regcontrol_addr;
79		- uint32 regcontrol_data;
80		- uint32 pllcontrol_addr;
81		- uint32 pllcontrol_data;
82		- uint32 pmustrapopt; /* 0x668, corerev >= 28 */
83		- uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
84		- uint32 retention_ctl; /* 0x670 */
85		- uint32 ILPPeriod; /* 0x674 */
	59	+ uint32 pmucontrol; /* 0x600 */
	60	+ uint32 pmucapabilities; /* 0x604 */
	61	+ uint32 pmustatus; /* 0x608 */
	62	+ uint32 res_state; /* 0x60C */
	63	+ uint32 res_pending; /* 0x610 */
	64	+ uint32 pmutimer; /* 0x614 */
	65	+ uint32 min_res_mask; /* 0x618 */
	66	+ uint32 max_res_mask; /* 0x61C */
	67	+ uint32 res_table_sel; /* 0x620 */
	68	+ uint32 res_dep_mask;
	69	+ uint32 res_updn_timer;
	70	+ uint32 res_timer;
	71	+ uint32 clkstretch;
	72	+ uint32 pmuwatchdog;
	73	+ uint32 gpiosel; /* 0x638, rev >= 1 */
	74	+ uint32 gpioenable; /* 0x63c, rev >= 1 */
	75	+ uint32 res_req_timer_sel; /* 0x640 */
	76	+ uint32 res_req_timer; /* 0x644 */
	77	+ uint32 res_req_mask; /* 0x648 */
	78	+ uint32 core_cap_ext; /* 0x64C */
	79	+ uint32 chipcontrol_addr; /* 0x650 */
	80	+ uint32 chipcontrol_data; /* 0x654 */
	81	+ uint32 regcontrol_addr;
	82	+ uint32 regcontrol_data;
	83	+ uint32 pllcontrol_addr;
	84	+ uint32 pllcontrol_data;
	85	+ uint32 pmustrapopt; /* 0x668, corerev >= 28 */
	86	+ uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
	87	+ uint32 retention_ctl; /* 0x670 */
	88	+ uint32 ILPPeriod; /* 0x674 */
86	89	uint32 PAD[2];
87		- uint32 retention_grpidx; /* 0x680 */
88		- uint32 retention_grpctl; /* 0x684 */
89		- uint32 mac_res_req_timer; /* 0x688 */
90		- uint32 mac_res_req_mask; /* 0x68c */
	90	+ uint32 retention_grpidx; /* 0x680 */
	91	+ uint32 retention_grpctl; /* 0x684 */
	92	+ uint32 mac_res_req_timer; /* 0x688 */
	93	+ uint32 mac_res_req_mask; /* 0x68c */
91	94	uint32 PAD[18];
92		- uint32 pmucontrol_ext; /* 0x6d8 */
93		- uint32 slowclkperiod; /* 0x6dc */
94		- uint32 PAD[8];
95		- uint32 pmuintmask0; /* 0x700 */
96		- uint32 pmuintmask1; /* 0x704 */
97		- uint32 PAD[14];
98		- uint32 pmuintstatus; /* 0x740 */
99		- uint32 extwakeupstatus; /* 0x744 */
100		- uint32 watchdog_res_mask; /* 0x748 */
101		- uint32 PAD[1]; /* 0x74C */
102		- uint32 swscratch; /* 0x750 */
103		- uint32 PAD[3]; /* 0x754-0x75C */
104		- uint32 extwakemask[2]; /* 0x760-0x764 */
105		- uint32 PAD[2]; /* 0x768-0x76C */
106		- uint32 extwakereqmask[2]; /* 0x770-0x774 */
107		- uint32 PAD[2]; /* 0x778-0x77C */
108		- uint32 pmuintctrl0; /* 0x780 */
109		- uint32 pmuintctrl1; /* 0x784 */
	95	+ uint32 pmucontrol_ext; /* 0x6d8 */
	96	+ uint32 slowclkperiod; /* 0x6dc */
	97	+ uint32 pmu_statstimer_addr; /* 0x6e0 */
	98	+ uint32 pmu_statstimer_ctrl; /* 0x6e4 */
	99	+ uint32 pmu_statstimer_N; /* 0x6e8 */
	100	+ uint32 PAD[1];
	101	+ uint32 mac_res_req_timer1; /* 0x6f0 */
	102	+ uint32 mac_res_req_mask1; /* 0x6f4 */
110	103	uint32 PAD[2];
111		- uint32 extwakectrl[2] ; /* 0x790 */
	104	+ uint32 pmuintmask0; /* 0x700 */
	105	+ uint32 pmuintmask1; /* 0x704 */
	106	+ uint32 PAD[14];
	107	+ uint32 pmuintstatus; /* 0x740 */
	108	+ uint32 extwakeupstatus; /* 0x744 */
	109	+ uint32 watchdog_res_mask; /* 0x748 */
	110	+ uint32 PAD[1]; /* 0x74C */
	111	+ uint32 swscratch; /* 0x750 */
	112	+ uint32 PAD[3]; /* 0x754-0x75C */
	113	+ uint32 extwakemask0; /* 0x760 */
	114	+ uint32 extwakemask1; /* 0x764 */
	115	+ uint32 PAD[2]; /* 0x768-0x76C */
	116	+ uint32 extwakereqmask[2]; /* 0x770-0x774 */
	117	+ uint32 PAD[2]; /* 0x778-0x77C */
	118	+ uint32 pmuintctrl0; /* 0x780 */
	119	+ uint32 pmuintctrl1; /* 0x784 */
	120	+ uint32 PAD[2];
	121	+ uint32 extwakectrl[2]; /* 0x790 */
	122	+ uint32 PAD[7];
	123	+ uint32 fis_ctrl_status; /* 0x7b4 */
	124	+ uint32 fis_min_res_mask; /* 0x7b8 */
	125	+ uint32 PAD[1];
	126	+ uint32 PrecisionTmrCtrlStatus; /* 0x7c0 */
112	127	} pmuregs_t;
113	128
114	129	typedef struct eci_prerev35 {
..	..	@@ -307,7 +322,8 @@
307	322	/* Clock control and hardware workarounds (corerev >= 20) */
308	323	uint32 clk_ctl_st; /* 0x1e0 */
309	324	uint32 hw_war;
310		- uint32 PAD[70];
	325	+ uint32 powerctl; /* 0x1e8 */
	326	+ uint32 PAD[69];
311	327
312	328	/* UARTs */
313	329	uint8 uart0data; /* 0x300 */
..	..	@@ -328,15 +344,21 @@
328	344	uint8 uart1lsr;
329	345	uint8 uart1msr;
330	346	uint8 uart1scratch; /* 0x407 */
331		- uint32 PAD[62];
	347	+ uint32 PAD[50];
	348	+ uint32 sr_memrw_addr; /* 0x4d0 */
	349	+ uint32 sr_memrw_data; /* 0x4d4 */
	350	+ uint32 PAD[10];
332	351
333	352	/* save/restore, corerev >= 48 */
334	353	uint32 sr_capability; /* 0x500 */
335	354	uint32 sr_control0; /* 0x504 */
336	355	uint32 sr_control1; /* 0x508 */
337	356	uint32 gpio_control; /* 0x50C */
338		- uint32 PAD[60];
339		-
	357	+ uint32 PAD[29];
	358	+ /* 2 SR engines case */
	359	+ uint32 sr1_control0; /* 0x584 */
	360	+ uint32 sr1_control1; /* 0x588 */
	361	+ uint32 PAD[29];
340	362	/* PMU registers (corerev >= 20) */
341	363	/* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP.
342	364	* The CPU must read them twice, compare, and retry if different.
..	..	@@ -370,20 +392,40 @@
370	392	uint32 pmustrapopt; /* 0x668, corerev >= 28 */
371	393	uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
372	394	uint32 retention_ctl; /* 0x670 */
373		- uint32 PAD[3];
	395	+ uint32 ILPPeriod; /* 0x674 */
	396	+ uint32 PAD[2];
374	397	uint32 retention_grpidx; /* 0x680 */
375	398	uint32 retention_grpctl; /* 0x684 */
376		- uint32 PAD[20];
	399	+ uint32 mac_res_req_timer; /* 0x688 */
	400	+ uint32 mac_res_req_mask; /* 0x68c */
	401	+ uint32 PAD[18];
377	402	uint32 pmucontrol_ext; /* 0x6d8 */
378	403	uint32 slowclkperiod; /* 0x6dc */
379		- uint32 PAD[8];
	404	+ uint32 pmu_statstimer_addr; /* 0x6e0 */
	405	+ uint32 pmu_statstimer_ctrl; /* 0x6e4 */
	406	+ uint32 pmu_statstimer_N; /* 0x6e8 */
	407	+ uint32 PAD[1];
	408	+ uint32 mac_res_req_timer1; /* 0x6f0 */
	409	+ uint32 mac_res_req_mask1; /* 0x6f4 */
	410	+ uint32 PAD[2];
380	411	uint32 pmuintmask0; /* 0x700 */
381	412	uint32 pmuintmask1; /* 0x704 */
382	413	uint32 PAD[14];
383	414	uint32 pmuintstatus; /* 0x740 */
384		- uint32 PAD[15];
	415	+ uint32 extwakeupstatus; /* 0x744 */
	416	+ uint32 PAD[6];
	417	+ uint32 extwakemask0; /* 0x760 */
	418	+ uint32 extwakemask1; /* 0x764 */
	419	+ uint32 PAD[2]; /* 0x768-0x76C */
	420	+ uint32 extwakereqmask[2]; /* 0x770-0x774 */
	421	+ uint32 PAD[2]; /* 0x778-0x77C */
385	422	uint32 pmuintctrl0; /* 0x780 */
386		- uint32 PAD[31];
	423	+ uint32 PAD[3]; /* 0x784 - 0x78c */
	424	+ uint32 extwakectrl[1]; /* 0x790 */
	425	+ uint32 PAD[8];
	426	+ uint32 fis_ctrl_status; /* 0x7b4 */
	427	+ uint32 fis_min_res_mask; /* 0x7b8 */
	428	+ uint32 PAD[17];
387	429	uint16 sromotp[512]; /* 0x800 */
388	430	#ifdef CCNFLASH_SUPPORT
389	431	/* Nand flash MLC controller registers (corerev >= 38) */
..	..	@@ -464,7 +506,7 @@
464	506	uint32 gci_gpioctl; /* 0xC44 */
465	507	uint32 gci_gpiostatus;
466	508	uint32 gci_gpiomask; /* 0xC4C */
467		- uint32 PAD;
	509	+ uint32 gci_eventsummary; /* 0xC50 */
468	510	uint32 gci_miscctl; /* 0xC54 */
469	511	uint32 gci_gpiointmask;
470	512	uint32 gci_gpiowakemask;
..	..	@@ -492,7 +534,7 @@
492	534	uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */
493	535	uint32 gci_rxfifoctrl; /* 0xDC8 */
494	536	uint32 gci_uartreadid; /* DCC */
495		- uint32 gci_uartescval; /* DD0 */
	537	+ uint32 gci_seciuartescval; /* DD0 */
496	538	uint32 PAD;
497	539	uint32 gci_secififolevel; /* DD8 */
498	540	uint32 gci_seciuartdata; /* DDC */
..	..	@@ -522,7 +564,6 @@
522	564	} chipcregs_t;
523	565
524	566	#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
525		-
526	567
527	568	#define CC_CHIPID 0
528	569	#define CC_CAPABILITIES 4
..	..	@@ -574,7 +615,13 @@
574	615	#define PMU_PLL_CONTROL_DATA 0x664
575	616
576	617	#define CC_SROM_CTRL 0x190
577		-#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
	618	+#define CC_SROM_ADDRESS 0x194u
	619	+#define CC_SROM_DATA 0x198u
	620	+#ifdef SROM16K_4364_ADDRSPACE
	621	+#define CC_SROM_OTP 0xa000 /* SROM/OTP address space */
	622	+#else
	623	+#define CC_SROM_OTP 0x0800
	624	+#endif // endif
578	625	#define CC_GCI_INDIRECT_ADDR_REG 0xC40
579	626	#define CC_GCI_CHIP_CTRL_REG 0xE00
580	627	#define CC_GCI_CC_OFFSET_2 2
..	..	@@ -582,6 +629,10 @@
582	629	#define CC_SWD_CTRL 0x380
583	630	#define CC_SWD_REQACK 0x384
584	631	#define CC_SWD_DATA 0x388
	632	+#define GPIO_SEL_0 0x00001111
	633	+#define GPIO_SEL_1 0x11110000
	634	+#define GPIO_SEL_8 0x00001111
	635	+#define GPIO_SEL_9 0x11110000
585	636
586	637	#define CHIPCTRLREG0 0x0
587	638	#define CHIPCTRLREG1 0x1
..	..	@@ -623,6 +674,44 @@
623	674	#define CC_BP_IND_ACCESS_RDWR_MASK (1 << CC_BP_IND_ACCESS_RDWR_SHIFT)
624	675	#define CC_BP_IND_ACCESS_ERROR_SHIFT 10
625	676	#define CC_BP_IND_ACCESS_ERROR_MASK (1 << CC_BP_IND_ACCESS_ERROR_SHIFT)
	677	+
	678	+#define LPO_SEL_TIMEOUT 1000
	679	+
	680	+#define LPO_FINAL_SEL_SHIFT 18
	681	+
	682	+#define LHL_LPO1_SEL 0
	683	+#define LHL_LPO2_SEL 0x1
	684	+#define LHL_32k_SEL 0x2
	685	+#define LHL_EXT_SEL 0x3
	686	+
	687	+#define EXTLPO_BUF_PD 0x40
	688	+#define LPO1_PD_EN 0x1
	689	+#define LPO1_PD_SEL 0x6
	690	+#define LPO1_PD_SEL_VAL 0x4
	691	+#define LPO2_PD_EN 0x8
	692	+#define LPO2_PD_SEL 0x30
	693	+#define LPO2_PD_SEL_VAL 0x20
	694	+#define OSC_32k_PD 0x80
	695	+
	696	+#define LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL 0x3
	697	+
	698	+#define LHL_LPO_AUTO 0x0
	699	+#define LHL_LPO1_ENAB 0x1
	700	+#define LHL_LPO2_ENAB 0x2
	701	+#define LHL_OSC_32k_ENAB 0x3
	702	+#define LHL_EXT_LPO_ENAB 0x4
	703	+#define RADIO_LPO_ENAB 0x5
	704	+
	705	+#define LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN 0x4
	706	+#define LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR 0x8
	707	+#define LHL_CLK_DET_CNT 0xF0
	708	+#define LHL_CLK_DET_CNT_SHIFT 4
	709	+#define LPO_SEL_SHIFT 9
	710	+
	711	+#define LHL_MAIN_CTL_ADR_FINAL_CLK_SEL 0x3C0000
	712	+#define LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL 0x600
	713	+
	714	+#define CLK_DET_CNT_THRESH 8
626	715
627	716	#ifdef SR_DEBUG
628	717	#define SUBCORE_POWER_ON 0x0001
..	..	@@ -689,14 +778,27 @@
689	778	#define CC_CAP2_GSIO 0x00000002 /*< GSIO (spi/i2c) present, rev >= 37 /
690	779
691	780	/* capabilities extension */
692		-#define CC_CAP_EXT_SECI_PRESENT 0x00000001 /*< SECI present /
693		-#define CC_CAP_EXT_GSIO_PRESENT 0x00000002 /*< GSIO present /
694		-#define CC_CAP_EXT_GCI_PRESENT 0x00000004 /*< GCI present /
695		-#define CC_CAP_EXT_AOB_PRESENT 0x00000040 /*< AOB present /
696		-#define CC_CAP_EXT_SWD_PRESENT 0x00000400 /*< SWD present /
	781	+#define CC_CAP_EXT_SECI_PRESENT 0x00000001 /*< SECI present /
	782	+#define CC_CAP_EXT_GSIO_PRESENT 0x00000002 /*< GSIO present /
	783	+#define CC_CAP_EXT_GCI_PRESENT 0x00000004 /*< GCI present /
	784	+#define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /*< UART present /
	785	+#define CC_CAP_EXT_AOB_PRESENT 0x00000040 /*< AOB present /
	786	+#define CC_CAP_EXT_SWD_PRESENT 0x00000400 /*< SWD present /
697	787
698	788	/* WL Channel Info to BT via GCI - bits 40 - 47 */
699	789	#define GCI_WL_CHN_INFO_MASK (0xFF00)
	790	+/* WL indication of MCHAN enabled/disabled to BT in awdl mode- bit 36 */
	791	+#define GCI_WL_MCHAN_BIT_MASK (0x0010)
	792	+
	793	+#ifdef WLC_SW_DIVERSITY
	794	+/* WL indication of SWDIV enabled/disabled to BT - bit 33 */
	795	+#define GCI_WL_SWDIV_ANT_VALID_BIT_MASK (0x0002)
	796	+#define GCI_SWDIV_ANT_VALID_SHIFT 0x1
	797	+#define GCI_SWDIV_ANT_VALID_DISABLE 0x0
	798	+#endif // endif
	799	+
	800	+/* WL Strobe to BT */
	801	+#define GCI_WL_STROBE_BIT_MASK (0x0020)
700	802	/* bits [51:48] - reserved for wlan TX pwr index */
701	803	/* bits [55:52] btc mode indication */
702	804	#define GCI_WL_BTC_MODE_SHIFT (20)
..	..	@@ -741,6 +843,8 @@
741	843	#define NS_SLOW_MEM_CLOCK 400000000
742	844	#endif /* CFG_SIM */
743	845
	846	+#define ALP_CLOCK_53573 40000000
	847	+
744	848	/* HT clock */
745	849	#define HT_CLOCK 80000000
746	850
..	..	@@ -755,8 +859,6 @@
755	859	#define RCTL_MEM_RET_SLEEP_LOG_MASK (1 << RCTL_MEM_RET_SLEEP_LOG_SHIFT)
756	860
757	861	/* 4321 chipcontrol */
758		-#define CHIPCTRL_4321A0_DEFAULT 0x3a4
759		-#define CHIPCTRL_4321A1_DEFAULT 0x0a4
760	862	#define CHIPCTRL_4321_PLL_DOWN 0x800000 /*< serdes PLL down override /
761	863
762	864	/* Fields in the otpstatus register in rev >= 21 */
..	..	@@ -836,6 +938,7 @@
836	938	#define OTPL_WRAP_TYPE_SHIFT 16
837	939	#define OTPL_WRAP_TYPE_65NM 0
838	940	#define OTPL_WRAP_TYPE_40NM 1
	941	+#define OTPL_WRAP_TYPE_28NM 2
839	942	#define OTPL_ROW_SIZE_MASK 0x0000F000
840	943	#define OTPL_ROW_SIZE_SHIFT 12
841	944
..	..	@@ -871,9 +974,47 @@
871	974	#define OTPPOC_OVST_READ_40NM 14
872	975	#define OTPPOC_OVST_PROG_40NM 15
873	976
	977	+/* Opcodes for OTPP_OC field (28NM) */
	978	+#define OTPPOC_READ_28NM 0
	979	+#define OTPPOC_READBURST_28NM 1
	980	+#define OTPPOC_PROG_ENABLE_28NM 2
	981	+#define OTPPOC_PROG_DISABLE_28NM 3
	982	+#define OTPPOC_PRESCREEN_28NM 4
	983	+#define OTPPOC_PRESCREEN_RP_28NM 5
	984	+#define OTPPOC_FLUSH_28NM 6
	985	+#define OTPPOC_NOP_28NM 7
	986	+#define OTPPOC_PROG_ECC_28NM 8
	987	+#define OTPPOC_PROG_ECC_READ_28NM 9
	988	+#define OTPPOC_PROG_28NM 10
	989	+#define OTPPOC_PROGRAM_RP_28NM 11
	990	+#define OTPPOC_PROGRAM_OVST_28NM 12
	991	+#define OTPPOC_RELOAD_28NM 13
	992	+#define OTPPOC_ERASE_28NM 14
	993	+#define OTPPOC_LOAD_RF_28NM 15
	994	+#define OTPPOC_CTRL_WR_28NM 16
	995	+#define OTPPOC_CTRL_RD_28NM 17
	996	+#define OTPPOC_READ_HP_28NM 18
	997	+#define OTPPOC_READ_OVST_28NM 19
	998	+#define OTPPOC_READ_VERIFY0_28NM 20
	999	+#define OTPPOC_READ_VERIFY1_28NM 21
	1000	+#define OTPPOC_READ_FORCE0_28NM 22
	1001	+#define OTPPOC_READ_FORCE1_28NM 23
	1002	+#define OTPPOC_BURNIN_28NM 24
	1003	+#define OTPPOC_PROGRAM_LOCK_28NM 25
	1004	+#define OTPPOC_PROGRAM_TESTCOL_28NM 26
	1005	+#define OTPPOC_READ_TESTCOL_28NM 27
	1006	+#define OTPPOC_READ_FOUT_28NM 28
	1007	+#define OTPPOC_SFT_RESET_28NM 29
	1008	+
	1009	+#define OTPP_OC_MASK_28NM 0x0f800000
	1010	+#define OTPP_OC_SHIFT_28NM 23
	1011	+#define OTPC_PROGEN_28NM 0x8
	1012	+#define OTPC_DBLERRCLR 0x20
	1013	+#define OTPC_CLK_EN_MASK 0x00000040
	1014	+#define OTPC_CLK_DIV_MASK 0x00000F80
	1015	+
874	1016	/* Fields in otplayoutextension */
875	1017	#define OTPLAYOUTEXT_FUSE_MASK 0x3FF
876		-
877	1018
878	1019	/* Jtagm characteristics that appeared at a given corerev */
879	1020	#define JTAGM_CREV_OLD 10 /*< Old command set, 16bit max IR /
..	..	@@ -931,7 +1072,15 @@
931	1072	#define CLKD_JTAG_SHIFT 8
932	1073	#define CLKD_UART 0x000000ff
933	1074
934		-#define CLKD2_SROM 0x00000003
	1075	+#define CLKD2_SROM 0x00000007
	1076	+#define CLKD2_SROMDIV_32 0
	1077	+#define CLKD2_SROMDIV_64 1
	1078	+#define CLKD2_SROMDIV_96 2
	1079	+#define CLKD2_SROMDIV_128 3
	1080	+#define CLKD2_SROMDIV_192 4
	1081	+#define CLKD2_SROMDIV_256 5
	1082	+#define CLKD2_SROMDIV_384 6
	1083	+#define CLKD2_SROMDIV_512 7
935	1084	#define CLKD2_SWD 0xf8000000
936	1085	#define CLKD2_SWD_SHIFT 27
937	1086
..	..	@@ -943,6 +1092,7 @@
943	1092	#define CI_ECI 0x00000010 /*< eci intr (corerev >= 21) /
944	1093	#define CI_PMU 0x00000020 /*< pmu intr (corerev >= 21) /
945	1094	#define CI_UART 0x00000040 /*< uart intr (corerev >= 21) /
	1095	+#define CI_WECI 0x00000080 /* eci wakeup intr (corerev >= 21) */
946	1096	#define CI_WDRESET 0x80000000 /*< watchdog reset occurred /
947	1097
948	1098	/* slow_clk_ctl */
..	..	@@ -975,6 +1125,19 @@
975	1125	#define SYCC_HR 0x00000010 /*< Force HT /
976	1126	#define SYCC_CD_MASK 0xffff0000 /*< ClkDiv (ILP = 1/(4 (divisor + 1)) */
977	1127	#define SYCC_CD_SHIFT 16
	1128	+
	1129	+/* watchdogcounter */
	1130	+/* WL sub-system reset */
	1131	+#define WD_SSRESET_PCIE_F0_EN 0x10000000
	1132	+/* BT sub-system reset */
	1133	+#define WD_SSRESET_PCIE_F1_EN 0x20000000
	1134	+#define WD_SSRESET_PCIE_F2_EN 0x40000000
	1135	+/* Both WL and BT sub-system reset */
	1136	+#define WD_SSRESET_PCIE_ALL_FN_EN 0x80000000
	1137	+#define WD_COUNTER_MASK 0x0fffffff
	1138	+#define WD_ENABLE_MASK \
	1139	+ (WD_SSRESET_PCIE_F0_EN \| WD_SSRESET_PCIE_F1_EN \| \
	1140	+ WD_SSRESET_PCIE_F2_EN \| WD_SSRESET_PCIE_ALL_FN_EN)
978	1141
979	1142	/* Indirect backplane access */
980	1143	#define BPIA_BYTEEN 0x0000000f
..	..	@@ -1084,7 +1247,13 @@
1084	1247	#define PCTL_XTALFREQ_SHIFT 2
1085	1248	#define PCTL_ILP_DIV_EN 0x00000002
1086	1249	#define PCTL_LPO_SEL 0x00000001
	1250	+
	1251	+/* Fields in pmucontrol_ext */
	1252	+#define PCTL_EXT_USE_LHL_TIMER 0x00000010
	1253	+#define PCTL_EXT_FASTLPO_ENAB 0x00000080
1087	1254	#define PCTL_EXT_FASTLPO_SWENAB 0x00000200
	1255	+#define PCTL_EXT_FASTSEQ_ENAB 0x00001000
	1256	+#define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000 /*< rev33 for FLL1M /
1088	1257
1089	1258	#define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77
1090	1259
..	..	@@ -1108,16 +1277,11 @@
1108	1277	#define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15)
1109	1278	#define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16
1110	1279	#define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16)
1111		-/* Retention Group Control special for 4334 */
1112		-#define PMU4334_RCTLGRP_CHAIN_LEN_GRP0 338
1113		-#define PMU4334_RCTLGRP_CHAIN_LEN_GRP1 315
1114		-/* Retention Group Control special for 43341 */
1115		-#define PMU43341_RCTLGRP_CHAIN_LEN_GRP0 366
1116		-#define PMU43341_RCTLGRP_CHAIN_LEN_GRP1 330
1117	1280
1118	1281	/* Fields in clkstretch */
1119	1282	#define CSTRETCH_HT 0xffff0000
1120	1283	#define CSTRETCH_ALP 0x0000ffff
	1284	+#define CSTRETCH_REDUCE_8 0x00080008
1121	1285
1122	1286	/* gpiotimerval */
1123	1287	#define GPIO_ONTIME_SHIFT 16
..	..	@@ -1209,7 +1373,6 @@
1209	1373	#define CC_EB_PCMCIA1_CFG 0x1ac00000 /*< PCMCIA 1 config base address /
1210	1374	#define CC_EB_PROGIF 0x1b000000 /*< ProgIF Async/Sync base address /
1211	1375
1212		-
1213	1376	/* Start/busy bit in flashcontrol */
1214	1377	#define SFLASH_OPCODE 0x000000ff
1215	1378	#define SFLASH_ACTION 0x00000700
..	..	@@ -1240,8 +1403,13 @@
1240	1403	#define SFLASH_ST_CSA 0x1000 /*< Keep chip select asserted /
1241	1404	#define SFLASH_ST_SSE 0x0220 /*< Sub-sector Erase /
1242	1405
1243		-#define SFLASH_MXIC_RDID 0x0390 /*< Read Manufacture ID /
1244		-#define SFLASH_MXIC_MFID 0xc2 /*< MXIC Manufacture ID /
	1406	+#define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */
	1407	+#define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */
	1408	+#define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */
	1409	+#define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */
	1410	+
	1411	+#define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */
	1412	+#define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */
1245	1413
1246	1414	/* Status register bits for ST flashes */
1247	1415	#define SFLASH_ST_WIP 0x01 /*< Write In Progress /
..	..	@@ -1282,6 +1450,12 @@
1282	1450	/* SPI register bits, corerev >= 37 */
1283	1451	#define GSIO_START 0x80000000
1284	1452	#define GSIO_BUSY GSIO_START
	1453	+
	1454	+/* GCI UART Function sel related */
	1455	+#define MUXENAB_GCI_UART_MASK (0x00000f00)
	1456	+#define MUXENAB_GCI_UART_SHIFT 8
	1457	+#define MUXENAB_GCI_UART_FNSEL_MASK (0x00003000)
	1458	+#define MUXENAB_GCI_UART_FNSEL_SHIFT 12
1285	1459
1286	1460	/*
1287	1461	* These are the UART port assignments, expressed as offsets from the base
..	..	@@ -1365,11 +1539,39 @@
1365	1539	#define PCAP5_CC_MASK 0xf8000000
1366	1540	#define PCAP5_CC_SHIFT 27
1367	1541
	1542	+/* pmucapabilities ext */
	1543	+#define PCAP_EXT_ST_NUM_SHIFT (8) /* stat timer number */
	1544	+#define PCAP_EXT_ST_NUM_MASK (0xf << PCAP_EXT_ST_NUM_SHIFT)
	1545	+#define PCAP_EXT_ST_SRC_NUM_SHIFT (12) /* stat timer source number */
	1546	+#define PCAP_EXT_ST_SRC_NUM_MASK (0xf << PCAP_EXT_ST_SRC_NUM_SHIFT)
	1547	+
	1548	+/* pmustattimer ctrl */
	1549	+#define PMU_ST_SRC_SHIFT (0) /* stat timer source number */
	1550	+#define PMU_ST_SRC_MASK (0xff << PMU_ST_SRC_SHIFT)
	1551	+#define PMU_ST_CNT_MODE_SHIFT (10) /* stat timer count mode */
	1552	+#define PMU_ST_CNT_MODE_MASK (0x3 << PMU_ST_CNT_MODE_SHIFT)
	1553	+#define PMU_ST_EN_SHIFT (8) /* stat timer enable */
	1554	+#define PMU_ST_EN_MASK (0x1 << PMU_ST_EN_SHIFT)
	1555	+#define PMU_ST_ENAB 1
	1556	+#define PMU_ST_DISAB 0
	1557	+#define PMU_ST_INT_EN_SHIFT (9) /* stat timer enable */
	1558	+#define PMU_ST_INT_EN_MASK (0x1 << PMU_ST_INT_EN_SHIFT)
	1559	+#define PMU_ST_INT_ENAB 1
	1560	+#define PMU_ST_INT_DISAB 0
	1561	+
	1562	+/* CoreCapabilitiesExtension */
	1563	+#define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000
	1564	+
1368	1565	/* PMU Resource Request Timer registers */
1369	1566	/* This is based on PmuRev0 */
1370	1567	#define PRRT_TIME_MASK 0x03ff
1371	1568	#define PRRT_INTEN 0x0400
1372		-#define PRRT_REQ_ACTIVE 0x0800
	1569	+/* ReqActive 25
	1570	+ * The hardware sets this field to 1 when the timer expires.
	1571	+ * Software writes this field to 1 to make immediate resource requests.
	1572	+ */
	1573	+#define PRRT_REQ_ACTIVE 0x0800 /* To check h/w status */
	1574	+#define PRRT_IMMEDIATE_RES_REQ 0x0800 /* macro for sw immediate res req */
1373	1575	#define PRRT_ALP_REQ 0x1000
1374	1576	#define PRRT_HT_REQ 0x2000
1375	1577	#define PRRT_HQ_REQ 0x4000
..	..	@@ -1381,6 +1583,11 @@
1381	1583
1382	1584	/* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */
1383	1585	#define RSRC_INTR_MASK_TIMER_INT_0 1
	1586	+#define PMU_INTR_MASK_EXTWAKE_REQ_ACTIVE_0 (1 << 20)
	1587	+
	1588	+/* bit 16 of the PMU interrupt vector - Stats Timer Interrupt */
	1589	+#define PMU_INT_STAT_TIMER_INT_SHIFT 16
	1590	+#define PMU_INT_STAT_TIMER_INT_MASK (1 << PMU_INT_STAT_TIMER_INT_SHIFT)
1384	1591
1385	1592	/* PMU resource bit position */
1386	1593	#define PMURES_BIT(bit) (1 << (bit))
..	..	@@ -1390,7 +1597,15 @@
1390	1597
1391	1598	/* PMU chip control0 register */
1392	1599	#define PMU_CHIPCTL0 0
1393		-#define PMU43143_CC0_SDIO_DRSTR_OVR (1 << 31) /* sdio drive strength override enable */
	1600	+
	1601	+#define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0)
	1602	+#define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0)
	1603	+#define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0xF << 6)
	1604	+#define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6)
	1605	+#define PMU_CC0_4369_XTAL_RES_BYPASS_START_VAL (0 << 12)
	1606	+#define PMU_CC0_4369_XTAL_RES_BYPASS_START_MASK (0x7 << 12)
	1607	+#define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_VAL (0x1 << 15)
	1608	+#define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15)
1394	1609
1395	1610	/* clock req types */
1396	1611	#define PMU_CC1_CLKREQ_TYPE_SHIFT 19
..	..	@@ -1398,6 +1613,10 @@
1398	1613
1399	1614	#define CLKREQ_TYPE_CONFIG_OPENDRAIN 0
1400	1615	#define CLKREQ_TYPE_CONFIG_PUSHPULL 1
	1616	+
	1617	+/* Power Control */
	1618	+#define PWRCTL_ENAB_MEM_CLK_GATE_SHIFT 5
	1619	+#define PWRCTL_AUTO_MEM_STBYRET 28
1401	1620
1402	1621	/* PMU chip control1 register */
1403	1622	#define PMU_CHIPCTL1 1
..	..	@@ -1418,21 +1637,46 @@
1418	1637	#define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080
1419	1638	#define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000
1420	1639
	1640	+#define PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK 0x00003F00u
	1641	+#define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00000400u
	1642	+
1421	1643	/* PMU chip control2 register */
	1644	+#define PMU_CC2_RFLDO3P3_PU_FORCE_ON (1 << 15)
	1645	+#define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000
	1646	+
	1647	+#define PMU_CC2_WL2CDIG_I_PMU_SLEEP (1 << 16)
1422	1648	#define PMU_CHIPCTL2 2
1423		-#define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1 << 18)
1424		-#define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1 << 19)
1425		-#define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1 << 20)
1426		-#define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1 << 21)
	1649	+#define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1 << 18)
	1650	+#define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1 << 19)
	1651	+#define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1 << 20)
	1652	+#define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1 << 21)
1427	1653	#define PMU_CC2_MASK_WL_DEV_WAKE (1 << 22)
1428	1654	#define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE (1 << 25)
	1655	+#define PMU_CC2_GCI2_WAKE (1 << 31)
1429	1656
	1657	+#define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3 << 26)
	1658	+#define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3 << 26)
	1659	+#define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0 << 28)
	1660	+#define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3 << 28)
1430	1661
1431	1662	/* PMU chip control3 register */
1432	1663	#define PMU_CHIPCTL3 3
1433	1664	#define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19
1434	1665	#define PMU_CC3_ENABLE_RF_SHIFT 22
1435	1666	#define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23
	1667	+
	1668	+#define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3F << 0)
	1669	+#define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3F << 0)
	1670	+#define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15)
	1671	+#define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15)
	1672	+#define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3F << 6)
	1673	+#define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3F << 6)
	1674	+#define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21)
	1675	+#define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21)
	1676	+#define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2 << 12)
	1677	+#define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7 << 12)
	1678	+#define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x6 << 27)
	1679	+#define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27)
1436	1680
1437	1681	/* PMU chip control4 register */
1438	1682	#define PMU_CHIPCTL4 4
..	..	@@ -1448,14 +1692,33 @@
1448	1692	#define PMU_CC4_SW_TYPE_EPHYMII 0x00004000
1449	1693	#define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000
1450	1694	#define PMU_CC4_SW_TYPE_RGMII 0x0000c000
	1695	+#define PMU_CC4_DISABLE_LQ_AVAIL (1<<27)
	1696	+
	1697	+#define PMU_CC4_4369_MAIN_PD_CBUCK2VDDB_ON (1u << 15u)
	1698	+#define PMU_CC4_4369_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u)
	1699	+#define PMU_CC4_4369_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u)
	1700	+#define PMU_CC4_4369_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u)
	1701	+
	1702	+#define PMU_CC4_4369_AUX_PD_CBUCK2VDDB_ON (1u << 21u)
	1703	+#define PMU_CC4_4369_AUX_PD_CBUCK2VDDRET_ON (1u << 22u)
	1704	+#define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u)
	1705	+#define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u)
1451	1706
1452	1707	/* PMU chip control5 register */
1453	1708	#define PMU_CHIPCTL5 5
	1709	+
	1710	+#define PMU_CC5_4369_SUBCORE_CBUCK2VDDB_ON (1u << 9u)
	1711	+#define PMU_CC5_4369_SUBCORE_CBUCK2VDDRET_ON (1u << 10u)
	1712	+#define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u)
	1713	+#define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u)
1454	1714
1455	1715	/* PMU chip control6 register */
1456	1716	#define PMU_CHIPCTL6 6
1457	1717	#define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4)
1458	1718	#define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6)
	1719	+#define PMU_CC6_ENABLE_PCIE_RETENTION (1 << 12)
	1720	+#define PMU_CC6_ENABLE_PMU_EXT_PERST (1 << 13)
	1721	+#define PMU_CC6_ENABLE_PMU_WAKEUP_PERST (1 << 14)
1459	1722
1460	1723	/* PMU chip control7 register */
1461	1724	#define PMU_CHIPCTL7 7
..	..	@@ -1467,6 +1730,63 @@
1467	1730	#define PMU_CC7_IF_TYPE_MII 0x00000040
1468	1731	#define PMU_CC7_IF_TYPE_RGMII 0x00000080
1469	1732
	1733	+#define PMU_CHIPCTL8 8
	1734	+#define PMU_CHIPCTL9 9
	1735	+
	1736	+#define PMU_CHIPCTL10 10
	1737	+#define PMU_CC10_PCIE_PWRSW_RESET0_CNT_SHIFT 0
	1738	+#define PMU_CC10_PCIE_PWRSW_RESET0_CNT_MASK 0x000000ff
	1739	+#define PMU_CC10_PCIE_PWRSW_RESET1_CNT_SHIFT 8
	1740	+#define PMU_CC10_PCIE_PWRSW_RESET1_CNT_MASK 0x0000ff00
	1741	+#define PMU_CC10_PCIE_PWRSW_UP_DLY_SHIFT 16
	1742	+#define PMU_CC10_PCIE_PWRSW_UP_DLY_MASK 0x000f0000
	1743	+#define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_SHIFT 20
	1744	+#define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_MASK 0x00f00000
	1745	+#define PMU_CC10_FORCE_PCIE_ON (1 << 24)
	1746	+#define PMU_CC10_FORCE_PCIE_SW_ON (1 << 25)
	1747	+#define PMU_CC10_FORCE_PCIE_RETNT_ON (1 << 26)
	1748	+
	1749	+#define PMU_CC10_PCIE_PWRSW_RESET_CNT_4US 1
	1750	+#define PMU_CC10_PCIE_PWRSW_RESET_CNT_8US 2
	1751	+
	1752	+#define PMU_CC10_PCIE_PWRSW_UP_DLY_0US 0
	1753	+
	1754	+#define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_4US 1
	1755	+
	1756	+#define PMU_CHIPCTL11 11
	1757	+#define PMU_CHIPCTL12 12
	1758	+
	1759	+/* PMU chip control13 register */
	1760	+#define PMU_CHIPCTL13 13
	1761	+
	1762	+#define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u)
	1763	+#define PMU_CC13_SUBCORE_CBUCK2VDDRET_OFF (1u << 1u)
	1764	+#define PMU_CC13_SUBCORE_MEMLPLDO2VDDB_OFF (1u << 2u)
	1765	+#define PMU_CC13_SUBCORE_MEMLPLDO2VDDRET_OFF (1u << 3u)
	1766	+
	1767	+#define PMU_CC13_MAIN_CBUCK2VDDB_OFF (1u << 4u)
	1768	+#define PMU_CC13_MAIN_CBUCK2VDDRET_OFF (1u << 5u)
	1769	+#define PMU_CC13_MAIN_MEMLPLDO2VDDB_OFF (1u << 6u)
	1770	+#define PMU_CC13_MAIN_MEMLPLDO2VDDRET_OFF (1u << 7u)
	1771	+
	1772	+#define PMU_CC13_AUX_CBUCK2VDDB_OFF (1u << 8u)
	1773	+#define PMU_CC13_AUX_MEMLPLDO2VDDB_OFF (1u << 10u)
	1774	+#define PMU_CC13_AUX_MEMLPLDO2VDDRET_OFF (1u << 11u)
	1775	+#define PMU_CC13_AUX_CBUCK2VDDRET_OFF (1u << 12u)
	1776	+
	1777	+#define PMU_CHIPCTL14 14
	1778	+#define PMU_CHIPCTL15 15
	1779	+#define PMU_CHIPCTL16 16
	1780	+#define PMU_CC16_CLK4M_DIS (1 << 4)
	1781	+#define PMU_CC16_FF_ZERO_ADJ (4 << 5)
	1782	+
	1783	+/* PMU chip control14 register */
	1784	+#define PMU_CC14_MAIN_VDDB2VDDRET_UP_DLY_MASK (0xF)
	1785	+#define PMU_CC14_MAIN_VDDB2VDD_UP_DLY_MASK (0xF << 4)
	1786	+#define PMU_CC14_AUX_VDDB2VDDRET_UP_DLY_MASK (0xF << 8)
	1787	+#define PMU_CC14_AUX_VDDB2VDD_UP_DLY_MASK (0xF << 12)
	1788	+#define PMU_CC14_PCIE_VDDB2VDDRET_UP_DLY_MASK (0xF << 16)
	1789	+#define PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK (0xF << 20)
1470	1790
1471	1791	/* PMU corerev and chip specific PLL controls.
1472	1792	* PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
..	..	@@ -1526,7 +1846,8 @@
1526	1846	#define PMU1_PLL0_PC1_M4DIV_BY_18 0x12
1527	1847	#define PMU1_PLL0_PC1_M4DIV_BY_36 0x24
1528	1848	#define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C
1529		-
	1849	+#define PMU1_PLL0_PC1_M2_M4DIV_MASK 0xff00ff00
	1850	+#define PMU1_PLL0_PC1_HOLD_LOAD_CH 0x28
1530	1851	#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
1531	1852	#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1532	1853	#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
..	..	@@ -1537,7 +1858,10 @@
1537	1858	#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
1538	1859	#define PMU1_PLL0_PC2_M5DIV_BY_12 0xc
1539	1860	#define PMU1_PLL0_PC2_M5DIV_BY_18 0x12
	1861	+#define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f
1540	1862	#define PMU1_PLL0_PC2_M5DIV_BY_36 0x24
	1863	+#define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a
	1864	+#define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c
1541	1865	#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
1542	1866	#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
1543	1867	#define PMU1_PLL0_PC2_M6DIV_BY_18 0x12
..	..	@@ -1559,8 +1883,11 @@
1559	1883
1560	1884	/* pll_ctrl, vco_rng, clkdrive_ch<x> */
1561	1885	#define PMU1_PLL0_PLLCTL5 5
1562		-#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
1563		-#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
	1886	+#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
	1887	+#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
	1888	+#define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000
	1889	+#define PMU1_PLL0_PC5_ASSERT_CH_SHIFT 24
	1890	+#define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000
1564	1891
1565	1892	#define PMU1_PLL0_PLLCTL6 6
1566	1893	#define PMU1_PLL0_PLLCTL7 7
..	..	@@ -1568,6 +1895,10 @@
1568	1895
1569	1896	#define PMU1_PLLCTL8_OPENLOOP_MASK (1 << 1)
1570	1897	#define PMU_PLL4350_OPENLOOP_MASK (1 << 7)
	1898	+
	1899	+#define PMU1_PLL0_PLLCTL9 9
	1900	+
	1901	+#define PMU1_PLL0_PLLCTL10 10
1571	1902
1572	1903	/* PMU rev 2 control words */
1573	1904	#define PMU2_PHY_PLL_PLLCTL 4
..	..	@@ -1660,18 +1991,6 @@
1660	1991	#define PMU5_MAINPLL_CPU 1
1661	1992	#define PMU5_MAINPLL_MEM 2
1662	1993	#define PMU5_MAINPLL_SI 3
1663		-
1664		-/* 4706 PMU */
1665		-#define PMU4706_MAINPLL_PLL0 0
1666		-#define PMU6_4706_PROCPLL_OFF 4 /*< The CPU PLL /
1667		-#define PMU6_4706_PROC_P2DIV_MASK 0x000f0000
1668		-#define PMU6_4706_PROC_P2DIV_SHIFT 16
1669		-#define PMU6_4706_PROC_P1DIV_MASK 0x0000f000
1670		-#define PMU6_4706_PROC_P1DIV_SHIFT 12
1671		-#define PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
1672		-#define PMU6_4706_PROC_NDIV_INT_SHIFT 3
1673		-#define PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1674		-#define PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1675	1994
1676	1995	#define PMU7_PLL_PLLCTL7 7
1677	1996	#define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000
..	..	@@ -1800,7 +2119,6 @@
1800	2119	#define PMU15_ARM_98MHZ 98400000 /*< 98.4 Mhz /
1801	2120	#define PMU15_ARM_97MHZ 97000000 /*< 97 Mhz /
1802	2121
1803		-
1804	2122	#define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070
1805	2123	#define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4
1806	2124
..	..	@@ -1824,228 +2142,48 @@
1824	2142	#define PMU4335_PLL0_PC1_MDIV2_MASK 0x0000ff00
1825	2143	#define PMU4335_PLL0_PC1_MDIV2_SHIFT 8
1826	2144
	2145	+/* PLL usage in 4347 */
	2146	+#define PMU4347_PLL0_PC2_P1DIV_MASK 0x000f0000
	2147	+#define PMU4347_PLL0_PC2_P1DIV_SHIFT 16
	2148	+#define PMU4347_PLL0_PC2_NDIV_INT_MASK 0x3ff00000
	2149	+#define PMU4347_PLL0_PC2_NDIV_INT_SHIFT 20
	2150	+#define PMU4347_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff
	2151	+#define PMU4347_PLL0_PC3_NDIV_FRAC_SHIFT 0
	2152	+#define PMU4347_PLL1_PC5_P1DIV_MASK 0xc0000000
	2153	+#define PMU4347_PLL1_PC5_P1DIV_SHIFT 30
	2154	+#define PMU4347_PLL1_PC6_P1DIV_MASK 0x00000003
	2155	+#define PMU4347_PLL1_PC6_P1DIV_SHIFT 0
	2156	+#define PMU4347_PLL1_PC6_NDIV_INT_MASK 0x00000ffc
	2157	+#define PMU4347_PLL1_PC6_NDIV_INT_SHIFT 2
	2158	+#define PMU4347_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000
	2159	+#define PMU4347_PLL1_PC6_NDIV_FRAC_SHIFT 12
1827	2160
1828		-/* PLL usage in 5356/5357 */
1829		-#define PMU5356_MAINPLL_PLL0 0
1830		-#define PMU5357_MAINPLL_PLL0 0
1831		-
1832		-/* 4716/47162 resources */
1833		-#define RES4716_PROC_PLL_ON 0x00000040
1834		-#define RES4716_PROC_HT_AVAIL 0x00000080
1835		-
1836		-/* 4716/4717/4718 Chip specific ChipControl register bits */
1837		-#define CCTRL_471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared w/ pflash */
1838		-
1839		-/* 5357 Chip specific ChipControl register bits */
1840		-/* 2nd - 32-bit reg */
1841		-#define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 /* I2S pins enable */
1842		-#define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 /* I2C/SPI pins enable */
1843		-
1844		-/* 5354 resources */
1845		-#define RES5354_EXT_SWITCHER_PWM 0 /*< 0x00001 /
1846		-#define RES5354_BB_SWITCHER_PWM 1 /*< 0x00002 /
1847		-#define RES5354_BB_SWITCHER_BURST 2 /*< 0x00004 /
1848		-#define RES5354_BB_EXT_SWITCHER_BURST 3 /*< 0x00008 /
1849		-#define RES5354_ILP_REQUEST 4 /*< 0x00010 /
1850		-#define RES5354_RADIO_SWITCHER_PWM 5 /*< 0x00020 /
1851		-#define RES5354_RADIO_SWITCHER_BURST 6 /*< 0x00040 /
1852		-#define RES5354_ROM_SWITCH 7 /*< 0x00080 /
1853		-#define RES5354_PA_REF_LDO 8 /*< 0x00100 /
1854		-#define RES5354_RADIO_LDO 9 /*< 0x00200 /
1855		-#define RES5354_AFE_LDO 10 /*< 0x00400 /
1856		-#define RES5354_PLL_LDO 11 /*< 0x00800 /
1857		-#define RES5354_BG_FILTBYP 12 /*< 0x01000 /
1858		-#define RES5354_TX_FILTBYP 13 /*< 0x02000 /
1859		-#define RES5354_RX_FILTBYP 14 /*< 0x04000 /
1860		-#define RES5354_XTAL_PU 15 /*< 0x08000 /
1861		-#define RES5354_XTAL_EN 16 /*< 0x10000 /
1862		-#define RES5354_BB_PLL_FILTBYP 17 /*< 0x20000 /
1863		-#define RES5354_RF_PLL_FILTBYP 18 /*< 0x40000 /
1864		-#define RES5354_BB_PLL_PU 19 /*< 0x80000 /
	2161	+/* Even though the masks are same as 4347, separate macros are
	2162	+created for 4369
	2163	+*/
	2164	+/* PLL usage in 4369 */
	2165	+#define PMU4369_PLL0_PC2_PDIV_MASK 0x000f0000
	2166	+#define PMU4369_PLL0_PC2_PDIV_SHIFT 16
	2167	+#define PMU4369_PLL0_PC2_NDIV_INT_MASK 0x3ff00000
	2168	+#define PMU4369_PLL0_PC2_NDIV_INT_SHIFT 20
	2169	+#define PMU4369_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff
	2170	+#define PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT 0
	2171	+#define PMU4369_PLL1_PC5_P1DIV_MASK 0xc0000000
	2172	+#define PMU4369_PLL1_PC5_P1DIV_SHIFT 30
	2173	+#define PMU4369_PLL1_PC6_P1DIV_MASK 0x00000003
	2174	+#define PMU4369_PLL1_PC6_P1DIV_SHIFT 0
	2175	+#define PMU4369_PLL1_PC6_NDIV_INT_MASK 0x00000ffc
	2176	+#define PMU4369_PLL1_PC6_NDIV_INT_SHIFT 2
	2177	+#define PMU4369_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000
	2178	+#define PMU4369_PLL1_PC6_NDIV_FRAC_SHIFT 12
1865	2179
1866	2180	/* 5357 Chip specific ChipControl register bits */
1867	2181	#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
1868	2182	#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
1869	2183	#define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */
1870		-
1871	2184	/* 43217 Chip specific ChipControl register bits */
1872	2185	#define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */
1873	2186	#define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */
1874		-
1875		-/* 43228 Chip specific ChipControl register bits */
1876		-#define CCTRL43228_EXTPA_C0 (1<<14) /* core1 extPA in ChipControl 1, bit 14 */
1877		-#define CCTRL43228_EXTPA_C1 (1<<9) /* core0 extPA in ChipControl 1, bit 1 */
1878		-
1879		-/* 4328 resources */
1880		-#define RES4328_EXT_SWITCHER_PWM 0 /*< 0x00001 /
1881		-#define RES4328_BB_SWITCHER_PWM 1 /*< 0x00002 /
1882		-#define RES4328_BB_SWITCHER_BURST 2 /*< 0x00004 /
1883		-#define RES4328_BB_EXT_SWITCHER_BURST 3 /*< 0x00008 /
1884		-#define RES4328_ILP_REQUEST 4 /*< 0x00010 /
1885		-#define RES4328_RADIO_SWITCHER_PWM 5 /*< 0x00020 /
1886		-#define RES4328_RADIO_SWITCHER_BURST 6 /*< 0x00040 /
1887		-#define RES4328_ROM_SWITCH 7 /*< 0x00080 /
1888		-#define RES4328_PA_REF_LDO 8 /*< 0x00100 /
1889		-#define RES4328_RADIO_LDO 9 /*< 0x00200 /
1890		-#define RES4328_AFE_LDO 10 /*< 0x00400 /
1891		-#define RES4328_PLL_LDO 11 /*< 0x00800 /
1892		-#define RES4328_BG_FILTBYP 12 /*< 0x01000 /
1893		-#define RES4328_TX_FILTBYP 13 /*< 0x02000 /
1894		-#define RES4328_RX_FILTBYP 14 /*< 0x04000 /
1895		-#define RES4328_XTAL_PU 15 /*< 0x08000 /
1896		-#define RES4328_XTAL_EN 16 /*< 0x10000 /
1897		-#define RES4328_BB_PLL_FILTBYP 17 /*< 0x20000 /
1898		-#define RES4328_RF_PLL_FILTBYP 18 /*< 0x40000 /
1899		-#define RES4328_BB_PLL_PU 19 /*< 0x80000 /
1900		-
1901		-/* 4325 A0/A1 resources */
1902		-#define RES4325_BUCK_BOOST_BURST 0 /*< 0x00000001 /
1903		-#define RES4325_CBUCK_BURST 1 /*< 0x00000002 /
1904		-#define RES4325_CBUCK_PWM 2 /*< 0x00000004 /
1905		-#define RES4325_CLDO_CBUCK_BURST 3 /*< 0x00000008 /
1906		-#define RES4325_CLDO_CBUCK_PWM 4 /*< 0x00000010 /
1907		-#define RES4325_BUCK_BOOST_PWM 5 /*< 0x00000020 /
1908		-#define RES4325_ILP_REQUEST 6 /*< 0x00000040 /
1909		-#define RES4325_ABUCK_BURST 7 /*< 0x00000080 /
1910		-#define RES4325_ABUCK_PWM 8 /*< 0x00000100 /
1911		-#define RES4325_LNLDO1_PU 9 /*< 0x00000200 /
1912		-#define RES4325_OTP_PU 10 /*< 0x00000400 /
1913		-#define RES4325_LNLDO3_PU 11 /*< 0x00000800 /
1914		-#define RES4325_LNLDO4_PU 12 /*< 0x00001000 /
1915		-#define RES4325_XTAL_PU 13 /*< 0x00002000 /
1916		-#define RES4325_ALP_AVAIL 14 /*< 0x00004000 /
1917		-#define RES4325_RX_PWRSW_PU 15 /*< 0x00008000 /
1918		-#define RES4325_TX_PWRSW_PU 16 /*< 0x00010000 /
1919		-#define RES4325_RFPLL_PWRSW_PU 17 /*< 0x00020000 /
1920		-#define RES4325_LOGEN_PWRSW_PU 18 /*< 0x00040000 /
1921		-#define RES4325_AFE_PWRSW_PU 19 /*< 0x00080000 /
1922		-#define RES4325_BBPLL_PWRSW_PU 20 /*< 0x00100000 /
1923		-#define RES4325_HT_AVAIL 21 /*< 0x00200000 /
1924		-
1925		-/* 4325 B0/C0 resources */
1926		-#define RES4325B0_CBUCK_LPOM 1 /*< 0x00000002 /
1927		-#define RES4325B0_CBUCK_BURST 2 /*< 0x00000004 /
1928		-#define RES4325B0_CBUCK_PWM 3 /*< 0x00000008 /
1929		-#define RES4325B0_CLDO_PU 4 /*< 0x00000010 /
1930		-
1931		-/* 4325 C1 resources */
1932		-#define RES4325C1_LNLDO2_PU 12 /*< 0x00001000 /
1933		-
1934		-/* 4325 chip-specific ChipStatus register bits */
1935		-#define CST4325_SPROM_OTP_SEL_MASK 0x00000003
1936		-#define CST4325_DEFCIS_SEL 0 /*< OTP is powered up, use def. CIS, no SPROM /
1937		-#define CST4325_SPROM_SEL 1 /*< OTP is powered up, SPROM is present /
1938		-#define CST4325_OTP_SEL 2 /*< OTP is powered up, no SPROM /
1939		-#define CST4325_OTP_PWRDN 3 /*< OTP is powered down, SPROM is present /
1940		-#define CST4325_SDIO_USB_MODE_MASK 0x00000004
1941		-#define CST4325_SDIO_USB_MODE_SHIFT 2
1942		-#define CST4325_RCAL_VALID_MASK 0x00000008
1943		-#define CST4325_RCAL_VALID_SHIFT 3
1944		-#define CST4325_RCAL_VALUE_MASK 0x000001f0
1945		-#define CST4325_RCAL_VALUE_SHIFT 4
1946		-#define CST4325_PMUTOP_2B_MASK 0x00000200 /*< 1 for 2b, 0 for to 2a /
1947		-#define CST4325_PMUTOP_2B_SHIFT 9
1948		-
1949		-#define RES4329_RESERVED0 0 /*< 0x00000001 /
1950		-#define RES4329_CBUCK_LPOM 1 /*< 0x00000002 /
1951		-#define RES4329_CBUCK_BURST 2 /*< 0x00000004 /
1952		-#define RES4329_CBUCK_PWM 3 /*< 0x00000008 /
1953		-#define RES4329_CLDO_PU 4 /*< 0x00000010 /
1954		-#define RES4329_PALDO_PU 5 /*< 0x00000020 /
1955		-#define RES4329_ILP_REQUEST 6 /*< 0x00000040 /
1956		-#define RES4329_RESERVED7 7 /*< 0x00000080 /
1957		-#define RES4329_RESERVED8 8 /*< 0x00000100 /
1958		-#define RES4329_LNLDO1_PU 9 /*< 0x00000200 /
1959		-#define RES4329_OTP_PU 10 /*< 0x00000400 /
1960		-#define RES4329_RESERVED11 11 /*< 0x00000800 /
1961		-#define RES4329_LNLDO2_PU 12 /*< 0x00001000 /
1962		-#define RES4329_XTAL_PU 13 /*< 0x00002000 /
1963		-#define RES4329_ALP_AVAIL 14 /*< 0x00004000 /
1964		-#define RES4329_RX_PWRSW_PU 15 /*< 0x00008000 /
1965		-#define RES4329_TX_PWRSW_PU 16 /*< 0x00010000 /
1966		-#define RES4329_RFPLL_PWRSW_PU 17 /*< 0x00020000 /
1967		-#define RES4329_LOGEN_PWRSW_PU 18 /*< 0x00040000 /
1968		-#define RES4329_AFE_PWRSW_PU 19 /*< 0x00080000 /
1969		-#define RES4329_BBPLL_PWRSW_PU 20 /*< 0x00100000 /
1970		-#define RES4329_HT_AVAIL 21 /*< 0x00200000 /
1971		-
1972		-#define CST4329_SPROM_OTP_SEL_MASK 0x00000003
1973		-#define CST4329_DEFCIS_SEL 0 /*< OTP is powered up, use def. CIS, no SPROM /
1974		-#define CST4329_SPROM_SEL 1 /*< OTP is powered up, SPROM is present /
1975		-#define CST4329_OTP_SEL 2 /*< OTP is powered up, no SPROM /
1976		-#define CST4329_OTP_PWRDN 3 /*< OTP is powered down, SPROM is present /
1977		-#define CST4329_SPI_SDIO_MODE_MASK 0x00000004
1978		-#define CST4329_SPI_SDIO_MODE_SHIFT 2
1979		-
1980		-/* 4312 chip-specific ChipStatus register bits */
1981		-#define CST4312_SPROM_OTP_SEL_MASK 0x00000003
1982		-#define CST4312_DEFCIS_SEL 0 /*< OTP is powered up, use def. CIS, no SPROM /
1983		-#define CST4312_SPROM_SEL 1 /*< OTP is powered up, SPROM is present /
1984		-#define CST4312_OTP_SEL 2 /*< OTP is powered up, no SPROM /
1985		-#define CST4312_OTP_BAD 3 /*< OTP is broken, SPROM is present /
1986		-
1987		-/* 4312 resources (all PMU chips with little memory constraint) */
1988		-#define RES4312_SWITCHER_BURST 0 /*< 0x00000001 /
1989		-#define RES4312_SWITCHER_PWM 1 /*< 0x00000002 /
1990		-#define RES4312_PA_REF_LDO 2 /*< 0x00000004 /
1991		-#define RES4312_CORE_LDO_BURST 3 /*< 0x00000008 /
1992		-#define RES4312_CORE_LDO_PWM 4 /*< 0x00000010 /
1993		-#define RES4312_RADIO_LDO 5 /*< 0x00000020 /
1994		-#define RES4312_ILP_REQUEST 6 /*< 0x00000040 /
1995		-#define RES4312_BG_FILTBYP 7 /*< 0x00000080 /
1996		-#define RES4312_TX_FILTBYP 8 /*< 0x00000100 /
1997		-#define RES4312_RX_FILTBYP 9 /*< 0x00000200 /
1998		-#define RES4312_XTAL_PU 10 /*< 0x00000400 /
1999		-#define RES4312_ALP_AVAIL 11 /*< 0x00000800 /
2000		-#define RES4312_BB_PLL_FILTBYP 12 /*< 0x00001000 /
2001		-#define RES4312_RF_PLL_FILTBYP 13 /*< 0x00002000 /
2002		-#define RES4312_HT_AVAIL 14 /*< 0x00004000 /
2003		-
2004		-/* 4322 resources */
2005		-#define RES4322_RF_LDO 0
2006		-#define RES4322_ILP_REQUEST 1
2007		-#define RES4322_XTAL_PU 2
2008		-#define RES4322_ALP_AVAIL 3
2009		-#define RES4322_SI_PLL_ON 4
2010		-#define RES4322_HT_SI_AVAIL 5
2011		-#define RES4322_PHY_PLL_ON 6
2012		-#define RES4322_HT_PHY_AVAIL 7
2013		-#define RES4322_OTP_PU 8
2014		-
2015		-/* 4322 chip-specific ChipStatus register bits */
2016		-#define CST4322_XTAL_FREQ_20_40MHZ 0x00000020
2017		-#define CST4322_SPROM_OTP_SEL_MASK 0x000000c0
2018		-#define CST4322_SPROM_OTP_SEL_SHIFT 6
2019		-#define CST4322_NO_SPROM_OTP 0 /*< no OTP, no SPROM /
2020		-#define CST4322_SPROM_PRESENT 1 /*< SPROM is present /
2021		-#define CST4322_OTP_PRESENT 2 /*< OTP is present /
2022		-#define CST4322_PCI_OR_USB 0x00000100
2023		-#define CST4322_BOOT_MASK 0x00000600
2024		-#define CST4322_BOOT_SHIFT 9
2025		-#define CST4322_BOOT_FROM_SRAM 0 /*< boot from SRAM, ARM in reset /
2026		-#define CST4322_BOOT_FROM_ROM 1 /*< boot from ROM /
2027		-#define CST4322_BOOT_FROM_FLASH 2 /*< boot from FLASH /
2028		-#define CST4322_BOOT_FROM_INVALID 3
2029		-#define CST4322_ILP_DIV_EN 0x00000800
2030		-#define CST4322_FLASH_TYPE_MASK 0x00001000
2031		-#define CST4322_FLASH_TYPE_SHIFT 12
2032		-#define CST4322_FLASH_TYPE_SHIFT_ST 0 /*< ST serial FLASH /
2033		-#define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /*< ATMEL flash /
2034		-#define CST4322_ARM_TAP_SEL 0x00002000
2035		-#define CST4322_RES_INIT_MODE_MASK 0x0000c000
2036		-#define CST4322_RES_INIT_MODE_SHIFT 14
2037		-#define CST4322_RES_INIT_MODE_ILPAVAIL 0 /*< resinitmode: ILP available /
2038		-#define CST4322_RES_INIT_MODE_ILPREQ 1 /*< resinitmode: ILP request /
2039		-#define CST4322_RES_INIT_MODE_ALPAVAIL 2 /*< resinitmode: ALP available /
2040		-#define CST4322_RES_INIT_MODE_HTAVAIL 3 /*< resinitmode: HT available /
2041		-#define CST4322_PCIPLLCLK_GATING 0x00010000
2042		-#define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000
2043		-#define CST4322_PCI_CARDBUS_MODE 0x00040000
2044		-
2045		-/* 43224 chip-specific ChipControl register bits */
2046		-#define CCTRL43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
2047		-#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
2048		-#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
2049	2187
2050	2188	/* 43236 resources */
2051	2189	#define RES43236_REGULATOR 0
..	..	@@ -2075,329 +2213,22 @@
2075	2213	#define CST43236_BOOT_FROM_FLASH 2 /*< boot from FLASH /
2076	2214	#define CST43236_BOOT_FROM_INVALID 3
2077	2215
2078		-/* 43237 resources */
2079		-#define RES43237_REGULATOR 0
2080		-#define RES43237_ILP_REQUEST 1
2081		-#define RES43237_XTAL_PU 2
2082		-#define RES43237_ALP_AVAIL 3
2083		-#define RES43237_SI_PLL_ON 4
2084		-#define RES43237_HT_SI_AVAIL 5
2085		-
2086		-/* 43237 chip-specific ChipControl register bits */
2087		-#define CCTRL43237_BT_COEXIST (1<<0) /*< 0 disable /
2088		-#define CCTRL43237_SECI (1<<1) /*< 0 SECI is disabled (JATG functional) /
2089		-#define CCTRL43237_EXT_LNA (1<<2) /*< 0 disable /
2090		-#define CCTRL43237_ANT_MUX_2o3 (1<<3) /*< 2o3 mux, chipcontrol bit 3 /
2091		-#define CCTRL43237_GSIO (1<<4) /*< 0 disable /
2092		-
2093		-/* 43237 Chip specific ChipStatus register bits */
2094		-#define CST43237_SFLASH_MASK 0x00000040
2095		-#define CST43237_OTP_SEL_MASK 0x00000080
2096		-#define CST43237_OTP_SEL_SHIFT 7
2097		-#define CST43237_HSIC_MASK 0x00000100 /*< USB/HSIC /
2098		-#define CST43237_BP_CLK 0x00000200 /*< 120/96Mbps /
2099		-#define CST43237_BOOT_MASK 0x00001800
2100		-#define CST43237_BOOT_SHIFT 11
2101		-#define CST43237_BOOT_FROM_SRAM 0 /*< boot from SRAM, ARM in reset /
2102		-#define CST43237_BOOT_FROM_ROM 1 /*< boot from ROM /
2103		-#define CST43237_BOOT_FROM_FLASH 2 /*< boot from FLASH /
2104		-#define CST43237_BOOT_FROM_INVALID 3
2105		-
2106		-/* 43239 resources */
2107		-#define RES43239_OTP_PU 9
2108		-#define RES43239_MACPHY_CLKAVAIL 23
2109		-#define RES43239_HT_AVAIL 24
2110		-
2111		-/* 43239 Chip specific ChipStatus register bits */
2112		-#define CST43239_SPROM_MASK 0x00000002
2113		-#define CST43239_SFLASH_MASK 0x00000004
2114		-#define CST43239_RES_INIT_MODE_SHIFT 7
2115		-#define CST43239_RES_INIT_MODE_MASK 0x000001f0
2116		-#define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15)) /*< SDIO \|\| gSPI /
2117		-#define CST43239_CHIPMODE_USB20D(cs) (~(cs) & (1 << 15)) /*< USB \|\| USBDA /
2118		-#define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0) /*< SDIO /
2119		-#define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) /*< gSPI /
2120		-
2121		-/* 4324 resources */
2122		-/* 43242 use same PMU as 4324 */
2123		-#define RES4324_LPLDO_PU 0
2124		-#define RES4324_RESET_PULLDN_DIS 1
2125		-#define RES4324_PMU_BG_PU 2
2126		-#define RES4324_HSIC_LDO_PU 3
2127		-#define RES4324_CBUCK_LPOM_PU 4
2128		-#define RES4324_CBUCK_PFM_PU 5
2129		-#define RES4324_CLDO_PU 6
2130		-#define RES4324_LPLDO2_LVM 7
2131		-#define RES4324_LNLDO1_PU 8
2132		-#define RES4324_LNLDO2_PU 9
2133		-#define RES4324_LDO3P3_PU 10
2134		-#define RES4324_OTP_PU 11
2135		-#define RES4324_XTAL_PU 12
2136		-#define RES4324_BBPLL_PU 13
2137		-#define RES4324_LQ_AVAIL 14
2138		-#define RES4324_WL_CORE_READY 17
2139		-#define RES4324_ILP_REQ 18
2140		-#define RES4324_ALP_AVAIL 19
2141		-#define RES4324_PALDO_PU 20
2142		-#define RES4324_RADIO_PU 21
2143		-#define RES4324_SR_CLK_STABLE 22
2144		-#define RES4324_SR_SAVE_RESTORE 23
2145		-#define RES4324_SR_PHY_PWRSW 24
2146		-#define RES4324_SR_PHY_PIC 25
2147		-#define RES4324_SR_SUBCORE_PWRSW 26
2148		-#define RES4324_SR_SUBCORE_PIC 27
2149		-#define RES4324_SR_MEM_PM0 28
2150		-#define RES4324_HT_AVAIL 29
2151		-#define RES4324_MACPHY_CLKAVAIL 30
2152		-
2153		-/* 4324 Chip specific ChipStatus register bits */
2154		-#define CST4324_SPROM_MASK 0x00000080
2155		-#define CST4324_SFLASH_MASK 0x00400000
2156		-#define CST4324_RES_INIT_MODE_SHIFT 10
2157		-#define CST4324_RES_INIT_MODE_MASK 0x00000c00
2158		-#define CST4324_CHIPMODE_MASK 0x7
2159		-#define CST4324_CHIPMODE_SDIOD(cs) ((~(cs)) & (1 << 2)) /*< SDIO \|\| gSPI /
2160		-#define CST4324_CHIPMODE_USB20D(cs) (((cs) & CST4324_CHIPMODE_MASK) == 0x6) /*< USB \|\| USBDA /
2161		-
2162		-/* 43242 Chip specific ChipStatus register bits */
2163		-#define CST43242_SFLASH_MASK 0x00000008
2164		-#define CST43242_SR_HALT (1<<25)
2165		-#define CST43242_SR_CHIP_STATUS_2 27 /* bit 27 */
2166		-
2167		-/* 4331 resources */
2168		-#define RES4331_REGULATOR 0
2169		-#define RES4331_ILP_REQUEST 1
2170		-#define RES4331_XTAL_PU 2
2171		-#define RES4331_ALP_AVAIL 3
2172		-#define RES4331_SI_PLL_ON 4
2173		-#define RES4331_HT_SI_AVAIL 5
2174		-
2175		-/* 4331 chip-specific ChipControl register bits */
2176		-#define CCTRL4331_BT_COEXIST (1<<0) /*< 0 disable /
2177		-#define CCTRL4331_SECI (1<<1) /*< 0 SECI is disabled (JATG functional) /
2178		-#define CCTRL4331_EXT_LNA_G (1<<2) /*< 0 disable /
2179		-#define CCTRL4331_SPROM_GPIO13_15 (1<<3) /*< sprom/gpio13-15 mux /
2180		-#define CCTRL4331_EXTPA_EN (1<<4) /*< 0 ext pa disable, 1 ext pa enabled /
2181		-#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /*< set drive out GPIO_CLK on sprom_cs pin /
2182		-#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /*< use sprom_cs pin as PCIE mdio interface /
2183		-#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */
2184		-#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /*< override core control on pipe_AuxClkEnable /
2185		-#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /*< override core control on pipe_AuxPowerDown /
2186		-#define CCTRL4331_PCIE_AUXCLKEN (1<<10) /*< pcie_auxclkenable /
2187		-#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /*< pcie_pipe_pllpowerdown /
2188		-#define CCTRL4331_EXTPA_EN2 (1<<12) /*< 0 ext pa disable, 1 ext pa enabled /
2189		-#define CCTRL4331_EXT_LNA_A (1<<13) /*< 0 disable /
2190		-#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /*< enable bt_shd0 at gpio4 /
2191		-#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /*< enable bt_shd1 at gpio5 /
2192		-#define CCTRL4331_EXTPA_ANA_EN (1<<24) /*< 0 ext pa disable, 1 ext pa enabled /
2193		-
2194		-/* 4331 Chip specific ChipStatus register bits */
2195		-#define CST4331_XTAL_FREQ 0x00000001 /*< crystal frequency 20/40Mhz /
2196		-#define CST4331_SPROM_OTP_SEL_MASK 0x00000006
2197		-#define CST4331_SPROM_OTP_SEL_SHIFT 1
2198		-#define CST4331_SPROM_PRESENT 0x00000002
2199		-#define CST4331_OTP_PRESENT 0x00000004
2200		-#define CST4331_LDO_RF 0x00000008
2201		-#define CST4331_LDO_PAR 0x00000010
2202		-
2203		-/* 4315 resource */
2204		-#define RES4315_CBUCK_LPOM 1 /*< 0x00000002 /
2205		-#define RES4315_CBUCK_BURST 2 /*< 0x00000004 /
2206		-#define RES4315_CBUCK_PWM 3 /*< 0x00000008 /
2207		-#define RES4315_CLDO_PU 4 /*< 0x00000010 /
2208		-#define RES4315_PALDO_PU 5 /*< 0x00000020 /
2209		-#define RES4315_ILP_REQUEST 6 /*< 0x00000040 /
2210		-#define RES4315_LNLDO1_PU 9 /*< 0x00000200 /
2211		-#define RES4315_OTP_PU 10 /*< 0x00000400 /
2212		-#define RES4315_LNLDO2_PU 12 /*< 0x00001000 /
2213		-#define RES4315_XTAL_PU 13 /*< 0x00002000 /
2214		-#define RES4315_ALP_AVAIL 14 /*< 0x00004000 /
2215		-#define RES4315_RX_PWRSW_PU 15 /*< 0x00008000 /
2216		-#define RES4315_TX_PWRSW_PU 16 /*< 0x00010000 /
2217		-#define RES4315_RFPLL_PWRSW_PU 17 /*< 0x00020000 /
2218		-#define RES4315_LOGEN_PWRSW_PU 18 /*< 0x00040000 /
2219		-#define RES4315_AFE_PWRSW_PU 19 /*< 0x00080000 /
2220		-#define RES4315_BBPLL_PWRSW_PU 20 /*< 0x00100000 /
2221		-#define RES4315_HT_AVAIL 21 /*< 0x00200000 /
2222		-
2223		-/* 4315 chip-specific ChipStatus register bits */
2224		-#define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /*< gpio [7:6], SDIO CIS selection /
2225		-#define CST4315_DEFCIS_SEL 0x00000000 /*< use default CIS, OTP is powered up /
2226		-#define CST4315_SPROM_SEL 0x00000001 /*< use SPROM, OTP is powered up /
2227		-#define CST4315_OTP_SEL 0x00000002 /*< use OTP, OTP is powered up /
2228		-#define CST4315_OTP_PWRDN 0x00000003 /*< use SPROM, OTP is powered down /
2229		-#define CST4315_SDIO_MODE 0x00000004 /*< gpio [8], sdio/usb mode /
2230		-#define CST4315_RCAL_VALID 0x00000008
2231		-#define CST4315_RCAL_VALUE_MASK 0x000001f0
2232		-#define CST4315_RCAL_VALUE_SHIFT 4
2233		-#define CST4315_PALDO_EXTPNP 0x00000200 /*< PALDO is configured with external PNP /
2234		-#define CST4315_CBUCK_MODE_MASK 0x00000c00
2235		-#define CST4315_CBUCK_MODE_BURST 0x00000400
2236		-#define CST4315_CBUCK_MODE_LPBURST 0x00000c00
2237		-
2238		-/* 4319 resources */
2239		-#define RES4319_CBUCK_LPOM 1 /*< 0x00000002 /
2240		-#define RES4319_CBUCK_BURST 2 /*< 0x00000004 /
2241		-#define RES4319_CBUCK_PWM 3 /*< 0x00000008 /
2242		-#define RES4319_CLDO_PU 4 /*< 0x00000010 /
2243		-#define RES4319_PALDO_PU 5 /*< 0x00000020 /
2244		-#define RES4319_ILP_REQUEST 6 /*< 0x00000040 /
2245		-#define RES4319_LNLDO1_PU 9 /*< 0x00000200 /
2246		-#define RES4319_OTP_PU 10 /*< 0x00000400 /
2247		-#define RES4319_LNLDO2_PU 12 /*< 0x00001000 /
2248		-#define RES4319_XTAL_PU 13 /*< 0x00002000 /
2249		-#define RES4319_ALP_AVAIL 14 /*< 0x00004000 /
2250		-#define RES4319_RX_PWRSW_PU 15 /*< 0x00008000 /
2251		-#define RES4319_TX_PWRSW_PU 16 /*< 0x00010000 /
2252		-#define RES4319_RFPLL_PWRSW_PU 17 /*< 0x00020000 /
2253		-#define RES4319_LOGEN_PWRSW_PU 18 /*< 0x00040000 /
2254		-#define RES4319_AFE_PWRSW_PU 19 /*< 0x00080000 /
2255		-#define RES4319_BBPLL_PWRSW_PU 20 /*< 0x00100000 /
2256		-#define RES4319_HT_AVAIL 21 /*< 0x00200000 /
2257		-
2258		-/* 4319 chip-specific ChipStatus register bits */
2259		-#define CST4319_SPI_CPULESSUSB 0x00000001
2260		-#define CST4319_SPI_CLK_POL 0x00000002
2261		-#define CST4319_SPI_CLK_PH 0x00000008
2262		-#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /*< gpio [7:6], SDIO CIS selection /
2263		-#define CST4319_SPROM_OTP_SEL_SHIFT 6
2264		-#define CST4319_DEFCIS_SEL 0x00000000 /*< use default CIS, OTP is powered up /
2265		-#define CST4319_SPROM_SEL 0x00000040 /*< use SPROM, OTP is powered up /
2266		-#define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */
2267		-#define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */
2268		-#define CST4319_SDIO_USB_MODE 0x00000100 /*< gpio [8], sdio/usb mode /
2269		-#define CST4319_REMAP_SEL_MASK 0x00000600
2270		-#define CST4319_ILPDIV_EN 0x00000800
2271		-#define CST4319_XTAL_PD_POL 0x00001000
2272		-#define CST4319_LPO_SEL 0x00002000
2273		-#define CST4319_RES_INIT_MODE 0x0000c000
2274		-#define CST4319_PALDO_EXTPNP 0x00010000 /*< PALDO is configured with external PNP /
2275		-#define CST4319_CBUCK_MODE_MASK 0x00060000
2276		-#define CST4319_CBUCK_MODE_BURST 0x00020000
2277		-#define CST4319_CBUCK_MODE_LPBURST 0x00060000
2278		-#define CST4319_RCAL_VALID 0x01000000
2279		-#define CST4319_RCAL_VALUE_MASK 0x3e000000
2280		-#define CST4319_RCAL_VALUE_SHIFT 25
2281		-
2282	2216	#define PMU1_PLL0_CHIPCTL0 0
2283	2217	#define PMU1_PLL0_CHIPCTL1 1
2284	2218	#define PMU1_PLL0_CHIPCTL2 2
2285		-#define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
2286		-#define CCTL_4319USB_XTAL_SEL_SHIFT 19
2287		-#define CCTL_4319USB_48MHZ_PLL_SEL 1
2288		-#define CCTL_4319USB_24MHZ_PLL_SEL 2
2289	2219
2290		-/* PMU resources for 4336 */
2291		-#define RES4336_CBUCK_LPOM 0
2292		-#define RES4336_CBUCK_BURST 1
2293		-#define RES4336_CBUCK_LP_PWM 2
2294		-#define RES4336_CBUCK_PWM 3
2295		-#define RES4336_CLDO_PU 4
2296		-#define RES4336_DIS_INT_RESET_PD 5
2297		-#define RES4336_ILP_REQUEST 6
2298		-#define RES4336_LNLDO_PU 7
2299		-#define RES4336_LDO3P3_PU 8
2300		-#define RES4336_OTP_PU 9
2301		-#define RES4336_XTAL_PU 10
2302		-#define RES4336_ALP_AVAIL 11
2303		-#define RES4336_RADIO_PU 12
2304		-#define RES4336_BG_PU 13
2305		-#define RES4336_VREG1p4_PU_PU 14
2306		-#define RES4336_AFE_PWRSW_PU 15
2307		-#define RES4336_RX_PWRSW_PU 16
2308		-#define RES4336_TX_PWRSW_PU 17
2309		-#define RES4336_BB_PWRSW_PU 18
2310		-#define RES4336_SYNTH_PWRSW_PU 19
2311		-#define RES4336_MISC_PWRSW_PU 20
2312		-#define RES4336_LOGEN_PWRSW_PU 21
2313		-#define RES4336_BBPLL_PWRSW_PU 22
2314		-#define RES4336_MACPHY_CLKAVAIL 23
2315		-#define RES4336_HT_AVAIL 24
2316		-#define RES4336_RSVD 25
2317		-
2318		-/* 4336 chip-specific ChipStatus register bits */
2319		-#define CST4336_SPI_MODE_MASK 0x00000001
2320		-#define CST4336_SPROM_PRESENT 0x00000002
2321		-#define CST4336_OTP_PRESENT 0x00000004
2322		-#define CST4336_ARMREMAP_0 0x00000008
2323		-#define CST4336_ILPDIV_EN_MASK 0x00000010
2324		-#define CST4336_ILPDIV_EN_SHIFT 4
2325		-#define CST4336_XTAL_PD_POL_MASK 0x00000020
2326		-#define CST4336_XTAL_PD_POL_SHIFT 5
2327		-#define CST4336_LPO_SEL_MASK 0x00000040
2328		-#define CST4336_LPO_SEL_SHIFT 6
2329		-#define CST4336_RES_INIT_MODE_MASK 0x00000180
2330		-#define CST4336_RES_INIT_MODE_SHIFT 7
2331		-#define CST4336_CBUCK_MODE_MASK 0x00000600
2332		-#define CST4336_CBUCK_MODE_SHIFT 9
2333		-
2334		-/* 4336 Chip specific PMU ChipControl register bits */
2335		-#define PCTL_4336_SERIAL_ENAB (1 << 24)
2336		-
2337		-/* 4330 resources */
2338		-#define RES4330_CBUCK_LPOM 0
2339		-#define RES4330_CBUCK_BURST 1
2340		-#define RES4330_CBUCK_LP_PWM 2
2341		-#define RES4330_CBUCK_PWM 3
2342		-#define RES4330_CLDO_PU 4
2343		-#define RES4330_DIS_INT_RESET_PD 5
2344		-#define RES4330_ILP_REQUEST 6
2345		-#define RES4330_LNLDO_PU 7
2346		-#define RES4330_LDO3P3_PU 8
2347		-#define RES4330_OTP_PU 9
2348		-#define RES4330_XTAL_PU 10
2349		-#define RES4330_ALP_AVAIL 11
2350		-#define RES4330_RADIO_PU 12
2351		-#define RES4330_BG_PU 13
2352		-#define RES4330_VREG1p4_PU_PU 14
2353		-#define RES4330_AFE_PWRSW_PU 15
2354		-#define RES4330_RX_PWRSW_PU 16
2355		-#define RES4330_TX_PWRSW_PU 17
2356		-#define RES4330_BB_PWRSW_PU 18
2357		-#define RES4330_SYNTH_PWRSW_PU 19
2358		-#define RES4330_MISC_PWRSW_PU 20
2359		-#define RES4330_LOGEN_PWRSW_PU 21
2360		-#define RES4330_BBPLL_PWRSW_PU 22
2361		-#define RES4330_MACPHY_CLKAVAIL 23
2362		-#define RES4330_HT_AVAIL 24
2363		-#define RES4330_5gRX_PWRSW_PU 25
2364		-#define RES4330_5gTX_PWRSW_PU 26
2365		-#define RES4330_5g_LOGEN_PWRSW_PU 27
2366		-
2367		-/* 4330 chip-specific ChipStatus register bits */
2368		-#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /*< SDIO \|\| gSPI /
2369		-#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /*< USB \|\| USBDA /
2370		-#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /*< SDIO /
2371		-#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /*< gSPI /
2372		-#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /*< USB packet-oriented /
2373		-#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /*< USB Direct Access /
2374		-#define CST4330_OTP_PRESENT 0x00000010
2375		-#define CST4330_LPO_AUTODET_EN 0x00000020
2376		-#define CST4330_ARMREMAP_0 0x00000040
2377		-#define CST4330_SPROM_PRESENT 0x00000080 /*< takes priority over OTP if both set /
2378		-#define CST4330_ILPDIV_EN 0x00000100
2379		-#define CST4330_LPO_SEL 0x00000200
2380		-#define CST4330_RES_INIT_MODE_SHIFT 10
2381		-#define CST4330_RES_INIT_MODE_MASK 0x00000c00
2382		-#define CST4330_CBUCK_MODE_SHIFT 12
2383		-#define CST4330_CBUCK_MODE_MASK 0x00003000
2384		-#define CST4330_CBUCK_POWER_OK 0x00004000
2385		-#define CST4330_BB_PLL_LOCKED 0x00008000
2386	2220	#define SOCDEVRAM_BP_ADDR 0x1E000000
2387	2221	#define SOCDEVRAM_ARM_ADDR 0x00800000
2388	2222
2389		-/* 4330 Chip specific PMU ChipControl register bits */
2390		-#define PCTL_4330_SERIAL_ENAB (1 << 24)
2391		-
2392		-/* 4330 Chip specific ChipControl register bits */
2393		-#define CCTRL_4330_GPIO_SEL 0x00000001 /* 1=select GPIOs to be muxed out */
2394		-#define CCTRL_4330_ERCX_SEL 0x00000002 /* 1=select ERCX BT coex to be muxed out */
2395		-#define CCTRL_4330_SDIO_HOST_WAKE 0x00000004 /* SDIO: 1=configure GPIO0 for host wake */
2396		-#define CCTRL_4330_JTAG_DISABLE 0x00000008 /* 1=disable JTAG interface on mux'd pins */
2397		-
2398		-#define PMU_VREG0_ADDR 0
	2223	+#define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0
2399	2224	#define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2
2400	2225	#define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3
	2226	+#define PMU_VREG0_CBUCKFSW_ADJ_SHIFT 7
	2227	+#define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F
	2228	+#define PMU_VREG0_RAMP_SEL_SHIFT 13
	2229	+#define PMU_VREG0_RAMP_SEL_MASK 0x7
	2230	+#define PMU_VREG0_VFB_RSEL_SHIFT 17
	2231	+#define PMU_VREG0_VFB_RSEL_MASK 3
2401	2232
2402	2233	#define PMU_VREG4_ADDR 4
2403	2234
..	..	@@ -2445,233 +2276,8 @@
2445	2276	#define PMU_VREG5_HSICDVDD_PD_SHIFT 11
2446	2277	#define PMU_VREG5_HSICDVDD_PD_MASK 0x1
2447	2278
2448		-/* 4334 resources */
2449		-#define RES4334_LPLDO_PU 0
2450		-#define RES4334_RESET_PULLDN_DIS 1
2451		-#define RES4334_PMU_BG_PU 2
2452		-#define RES4334_HSIC_LDO_PU 3
2453		-#define RES4334_CBUCK_LPOM_PU 4
2454		-#define RES4334_CBUCK_PFM_PU 5
2455		-#define RES4334_CLDO_PU 6
2456		-#define RES4334_LPLDO2_LVM 7
2457		-#define RES4334_LNLDO_PU 8
2458		-#define RES4334_LDO3P3_PU 9
2459		-#define RES4334_OTP_PU 10
2460		-#define RES4334_XTAL_PU 11
2461		-#define RES4334_WL_PWRSW_PU 12
2462		-#define RES4334_LQ_AVAIL 13
2463		-#define RES4334_LOGIC_RET 14
2464		-#define RES4334_MEM_SLEEP 15
2465		-#define RES4334_MACPHY_RET 16
2466		-#define RES4334_WL_CORE_READY 17
2467		-#define RES4334_ILP_REQ 18
2468		-#define RES4334_ALP_AVAIL 19
2469		-#define RES4334_MISC_PWRSW_PU 20
2470		-#define RES4334_SYNTH_PWRSW_PU 21
2471		-#define RES4334_RX_PWRSW_PU 22
2472		-#define RES4334_RADIO_PU 23
2473		-#define RES4334_WL_PMU_PU 24
2474		-#define RES4334_VCO_LDO_PU 25
2475		-#define RES4334_AFE_LDO_PU 26
2476		-#define RES4334_RX_LDO_PU 27
2477		-#define RES4334_TX_LDO_PU 28
2478		-#define RES4334_HT_AVAIL 29
2479		-#define RES4334_MACPHY_CLK_AVAIL 30
2480		-
2481		-/* 4334 chip-specific ChipStatus register bits */
2482		-#define CST4334_CHIPMODE_MASK 7
2483		-#define CST4334_SDIO_MODE 0x00000000
2484		-#define CST4334_SPI_MODE 0x00000004
2485		-#define CST4334_HSIC_MODE 0x00000006
2486		-#define CST4334_BLUSB_MODE 0x00000007
2487		-#define CST4334_CHIPMODE_HSIC(cs) (((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE)
2488		-#define CST4334_OTP_PRESENT 0x00000010
2489		-#define CST4334_LPO_AUTODET_EN 0x00000020
2490		-#define CST4334_ARMREMAP_0 0x00000040
2491		-#define CST4334_SPROM_PRESENT 0x00000080
2492		-#define CST4334_ILPDIV_EN_MASK 0x00000100
2493		-#define CST4334_ILPDIV_EN_SHIFT 8
2494		-#define CST4334_LPO_SEL_MASK 0x00000200
2495		-#define CST4334_LPO_SEL_SHIFT 9
2496		-#define CST4334_RES_INIT_MODE_MASK 0x00000C00
2497		-#define CST4334_RES_INIT_MODE_SHIFT 10
2498		-
2499		-/* 4334 Chip specific PMU ChipControl register bits */
2500		-#define PCTL_4334_GPIO3_ENAB (1 << 3)
2501		-
2502		-/* 4334 Chip control */
2503		-#define CCTRL4334_PMU_WAKEUP_GPIO1 (1 << 0)
2504		-#define CCTRL4334_PMU_WAKEUP_HSIC (1 << 1)
2505		-#define CCTRL4334_PMU_WAKEUP_AOS (1 << 2)
2506		-#define CCTRL4334_HSIC_WAKE_MODE (1 << 3)
2507		-#define CCTRL4334_HSIC_INBAND_GPIO1 (1 << 4)
2508		-#define CCTRL4334_HSIC_LDO_PU (1 << 23)
2509		-
2510		-/* 4334 Chip control 3 */
2511		-#define CCTRL4334_BLOCK_EXTRNL_WAKE (1 << 4)
2512		-#define CCTRL4334_SAVERESTORE_FIX (1 << 5)
2513		-
2514		-/* 43341 Chip control 3 */
2515		-#define CCTRL43341_BLOCK_EXTRNL_WAKE (1 << 13)
2516		-#define CCTRL43341_SAVERESTORE_FIX (1 << 14)
2517		-#define CCTRL43341_BT_ISO_SEL (1 << 16)
2518		-
2519		-/* 4334 Chip specific ChipControl1 register bits */
2520		-#define CCTRL1_4334_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2521		-#define CCTRL1_4334_ERCX_SEL (1 << 1) /* 1=select ERCX BT coex to be muxed out */
2522		-#define CCTRL1_4334_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2523		-#define CCTRL1_4334_JTAG_DISABLE (1 << 3) /* 1=disable JTAG interface on mux'd pins */
2524		-#define CCTRL1_4334_UART_ON_4_5 (1 << 28) /*< 1=UART_TX/UART_RX muxed on GPIO_4/5 (4334B0/1) /
2525		-
2526		-/* 4324 Chip specific ChipControl1 register bits */
2527		-#define CCTRL1_4324_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2528		-#define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2529		-
2530		-/* 43143 chip-specific ChipStatus register bits based on Confluence documentation */
2531		-/* register contains strap values sampled during POR */
2532		-#define CST43143_REMAP_TO_ROM (3 << 0) /* 00=Boot SRAM, 01=Boot ROM, 10=Boot SFLASH */
2533		-#define CST43143_SDIO_EN (1 << 2) /* 0 = USB Enab, SDIO pins are GPIO or I2S */
2534		-#define CST43143_SDIO_ISO (1 << 3) /* 1 = SDIO isolated */
2535		-#define CST43143_USB_CPU_LESS (1 << 4) /* 1 = CPULess mode Enabled */
2536		-#define CST43143_CBUCK_MODE (3 << 6) /* Indicates what controller mode CBUCK is in */
2537		-#define CST43143_POK_CBUCK (1 << 8) /* 1 = 1.2V CBUCK voltage ready */
2538		-#define CST43143_PMU_OVRSPIKE (1 << 9)
2539		-#define CST43143_PMU_OVRTEMP (0xF << 10)
2540		-#define CST43143_SR_FLL_CAL_DONE (1 << 14)
2541		-#define CST43143_USB_PLL_LOCKDET (1 << 15)
2542		-#define CST43143_PMU_PLL_LOCKDET (1 << 16)
2543		-#define CST43143_CHIPMODE_SDIOD(cs) (((cs) & CST43143_SDIO_EN) != 0) /* SDIO */
2544		-
2545		-/* 43143 Chip specific ChipControl register bits */
2546		-/* 00: SECI is disabled (JATG functional), 01: 2 wire, 10: 4 wire */
2547		-#define CCTRL_43143_SECI (1<<0)
2548		-#define CCTRL_43143_BT_LEGACY (1<<1)
2549		-#define CCTRL_43143_I2S_MODE (1<<2) /*< 0: SDIO enabled /
2550		-#define CCTRL_43143_I2S_MASTER (1<<3) /*< 0: I2S MCLK input disabled /
2551		-#define CCTRL_43143_I2S_FULL (1<<4) /*< 0: I2S SDIN and SPDIF_TX inputs disabled /
2552		-#define CCTRL_43143_GSIO (1<<5) /*< 0: sFlash enabled /
2553		-#define CCTRL_43143_RF_SWCTRL_MASK (7<<6) /*< 0: disabled /
2554		-#define CCTRL_43143_RF_SWCTRL_0 (1<<6)
2555		-#define CCTRL_43143_RF_SWCTRL_1 (2<<6)
2556		-#define CCTRL_43143_RF_SWCTRL_2 (4<<6)
2557		-#define CCTRL_43143_RF_XSWCTRL (1<<9) /*< 0: UART enabled /
2558		-#define CCTRL_43143_HOST_WAKE0 (1<<11) /*< 1: SDIO separate interrupt output from GPIO4 /
2559		-#define CCTRL_43143_HOST_WAKE1 (1<<12) /* 1: SDIO separate interrupt output from GPIO16 */
2560		-
2561		-/* 43143 resources, based on pmu_params.xls V1.19 */
2562		-#define RES43143_EXT_SWITCHER_PWM 0 /*< 0x00001 /
2563		-#define RES43143_XTAL_PU 1 /*< 0x00002 /
2564		-#define RES43143_ILP_REQUEST 2 /*< 0x00004 /
2565		-#define RES43143_ALP_AVAIL 3 /*< 0x00008 /
2566		-#define RES43143_WL_CORE_READY 4 /*< 0x00010 /
2567		-#define RES43143_BBPLL_PWRSW_PU 5 /*< 0x00020 /
2568		-#define RES43143_HT_AVAIL 6 /*< 0x00040 /
2569		-#define RES43143_RADIO_PU 7 /*< 0x00080 /
2570		-#define RES43143_MACPHY_CLK_AVAIL 8 /*< 0x00100 /
2571		-#define RES43143_OTP_PU 9 /*< 0x00200 /
2572		-#define RES43143_LQ_AVAIL 10 /*< 0x00400 /
2573		-
2574		-#define PMU43143_XTAL_CORE_SIZE_MASK 0x3F
2575		-
2576		-/* 4313 resources */
2577		-#define RES4313_BB_PU_RSRC 0
2578		-#define RES4313_ILP_REQ_RSRC 1
2579		-#define RES4313_XTAL_PU_RSRC 2
2580		-#define RES4313_ALP_AVAIL_RSRC 3
2581		-#define RES4313_RADIO_PU_RSRC 4
2582		-#define RES4313_BG_PU_RSRC 5
2583		-#define RES4313_VREG1P4_PU_RSRC 6
2584		-#define RES4313_AFE_PWRSW_RSRC 7
2585		-#define RES4313_RX_PWRSW_RSRC 8
2586		-#define RES4313_TX_PWRSW_RSRC 9
2587		-#define RES4313_BB_PWRSW_RSRC 10
2588		-#define RES4313_SYNTH_PWRSW_RSRC 11
2589		-#define RES4313_MISC_PWRSW_RSRC 12
2590		-#define RES4313_BB_PLL_PWRSW_RSRC 13
2591		-#define RES4313_HT_AVAIL_RSRC 14
2592		-#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
2593		-
2594		-/* 4313 chip-specific ChipStatus register bits */
2595		-#define CST4313_SPROM_PRESENT 1
2596		-#define CST4313_OTP_PRESENT 2
2597		-#define CST4313_SPROM_OTP_SEL_MASK 0x00000002
2598		-#define CST4313_SPROM_OTP_SEL_SHIFT 0
2599		-
2600		-/* 4313 Chip specific ChipControl register bits */
2601		-#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2602		-
2603		-/* PMU respources for 4314 */
2604		-#define RES4314_LPLDO_PU 0
2605		-#define RES4314_PMU_SLEEP_DIS 1
2606		-#define RES4314_PMU_BG_PU 2
2607		-#define RES4314_CBUCK_LPOM_PU 3
2608		-#define RES4314_CBUCK_PFM_PU 4
2609		-#define RES4314_CLDO_PU 5
2610		-#define RES4314_LPLDO2_LVM 6
2611		-#define RES4314_WL_PMU_PU 7
2612		-#define RES4314_LNLDO_PU 8
2613		-#define RES4314_LDO3P3_PU 9
2614		-#define RES4314_OTP_PU 10
2615		-#define RES4314_XTAL_PU 11
2616		-#define RES4314_WL_PWRSW_PU 12
2617		-#define RES4314_LQ_AVAIL 13
2618		-#define RES4314_LOGIC_RET 14
2619		-#define RES4314_MEM_SLEEP 15
2620		-#define RES4314_MACPHY_RET 16
2621		-#define RES4314_WL_CORE_READY 17
2622		-#define RES4314_ILP_REQ 18
2623		-#define RES4314_ALP_AVAIL 19
2624		-#define RES4314_MISC_PWRSW_PU 20
2625		-#define RES4314_SYNTH_PWRSW_PU 21
2626		-#define RES4314_RX_PWRSW_PU 22
2627		-#define RES4314_RADIO_PU 23
2628		-#define RES4314_VCO_LDO_PU 24
2629		-#define RES4314_AFE_LDO_PU 25
2630		-#define RES4314_RX_LDO_PU 26
2631		-#define RES4314_TX_LDO_PU 27
2632		-#define RES4314_HT_AVAIL 28
2633		-#define RES4314_MACPHY_CLK_AVAIL 29
2634		-
2635		-/* 4314 chip-specific ChipStatus register bits */
2636		-#define CST4314_OTP_ENABLED 0x00200000
2637		-
2638		-/* 43228 resources */
2639		-#define RES43228_NOT_USED 0
2640		-#define RES43228_ILP_REQUEST 1
2641		-#define RES43228_XTAL_PU 2
2642		-#define RES43228_ALP_AVAIL 3
2643		-#define RES43228_PLL_EN 4
2644		-#define RES43228_HT_PHY_AVAIL 5
2645		-
2646	2279	/* 43228 chipstatus reg bits */
2647		-#define CST43228_ILP_DIV_EN 0x1
2648	2280	#define CST43228_OTP_PRESENT 0x2
2649		-#define CST43228_SERDES_REFCLK_PADSEL 0x4
2650		-#define CST43228_SDIO_MODE 0x8
2651		-#define CST43228_SDIO_OTP_PRESENT 0x10
2652		-#define CST43228_SDIO_RESET 0x20
2653		-
2654		-/* 4706 chipstatus reg bits */
2655		-#define CST4706_PKG_OPTION (1<<0) /* 0: full-featured package 1: low-cost package */
2656		-#define CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */
2657		-#define CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2658		-#define CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */
2659		-#define CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */
2660		-
2661		-/* 4706 flashstrconfig reg bits */
2662		-#define FLSTRCF4706_MASK 0x000000ff
2663		-#define FLSTRCF4706_SF1 0x00000001 /*< 2nd serial flash present /
2664		-#define FLSTRCF4706_PF1 0x00000002 /*< 2nd parallel flash present /
2665		-#define FLSTRCF4706_SF1_TYPE 0x00000004 /*< 2nd serial flash type : 0 : ST, 1 : Atmel /
2666		-#define FLSTRCF4706_NF1 0x00000008 /*< 2nd NAND flash present /
2667		-#define FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /*< Valid value mask /
2668		-#define FLSTRCF4706_1ST_MADDR_SEG_4MB 0x00000010 /*< 4MB /
2669		-#define FLSTRCF4706_1ST_MADDR_SEG_8MB 0x00000020 /*< 8MB /
2670		-#define FLSTRCF4706_1ST_MADDR_SEG_16MB 0x00000030 /*< 16MB /
2671		-#define FLSTRCF4706_1ST_MADDR_SEG_32MB 0x00000040 /*< 32MB /
2672		-#define FLSTRCF4706_1ST_MADDR_SEG_64MB 0x00000050 /*< 64MB /
2673		-#define FLSTRCF4706_1ST_MADDR_SEG_128MB 0x00000060 /*< 128MB /
2674		-#define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 /*< 256MB /
2675	2281
2676	2282	/* 4360 Chip specific ChipControl register bits */
2677	2283	#define CCTRL4360_I2C_MODE (1 << 0)
..	..	@@ -2719,12 +2325,14 @@
2719	2325	#define CST4360_AVBBPLL_LOCK 0x00001000
2720	2326	#define CST4360_USBBBPLL_LOCK 0x00002000
2721	2327	#define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \
2722		- CST4360_RSRC_INIT_MODE_SHIFT)
	2328	+ CST4360_RSRC_INIT_MODE_SHIFT)
2723	2329
2724		-#define CCTRL_4360_UART_SEL 0x2
	2330	+#define CCTRL_4360_UART_SEL 0x2
	2331	+
2725	2332	#define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \
2726		- CST4360_RSRC_INIT_MODE_SHIFT)
	2333	+ CST4360_RSRC_INIT_MODE_SHIFT)
2727	2334
	2335	+#define PMU4360_CC1_GPIO7_OVRD (1<<23) /* GPIO7 override */
2728	2336
2729	2337	/* 43602 PMU resources based on pmu_params.xls version v0.95 */
2730	2338	#define RES43602_LPLDO_PU 0
..	..	@@ -2795,6 +2403,35 @@
2795	2403	#define RES4365_RADIO_PU 12
2796	2404	#define RES4365_MACPHY_CLK_AVAIL 13
2797	2405
	2406	+/* 43684 PMU resources */
	2407	+#define RES43684_REGULATOR_PU 0
	2408	+#define RES43684_PCIE_LDO_BG_PU 1
	2409	+#define RES43684_XTAL_LDO_PU 2
	2410	+#define RES43684_XTAL_PU 3
	2411	+#define RES43684_CPU_PLL_LDO_PU 4
	2412	+#define RES43684_CPU_PLL_PU 5
	2413	+#define RES43684_WL_CORE_RDY 6
	2414	+#define RES43684_ILP_REQ 7
	2415	+#define RES43684_ALP_AVAIL 8
	2416	+#define RES43684_HT_AVAIL 9
	2417	+#define RES43684_BB_PLL_LDO_PU 10
	2418	+#define RES43684_BB_PLL_PU 11
	2419	+#define RES43684_MINI_PMU_PU 12
	2420	+#define RES43684_RADIO_PU 13
	2421	+#define RES43684_MACPHY_CLK_AVAIL 14
	2422	+#define RES43684_PCIE_LDO_PU 15
	2423	+
	2424	+/* 7271 PMU resources */
	2425	+#define RES7271_REGULATOR_PU 0
	2426	+#define RES7271_WL_CORE_RDY 1
	2427	+#define RES7271_ILP_REQ 2
	2428	+#define RES7271_ALP_AVAIL 3
	2429	+#define RES7271_HT_AVAIL 4
	2430	+#define RES7271_BB_PLL_PU 5
	2431	+#define RES7271_MINIPMU_PU 6
	2432	+#define RES7271_RADIO_PU 7
	2433	+#define RES7271_MACPHY_CLK_AVAIL 8
	2434	+
2798	2435	/* 4349 related */
2799	2436	#define RES4349_LPLDO_PU 0
2800	2437	#define RES4349_BG_PU 1
..	..	@@ -2828,58 +2465,679 @@
2828	2465	#define RES4349_HT_AVAIL 29
2829	2466	#define RES4349_MACPHY_CLKAVAIL 30
2830	2467
2831		-#define CR4_4349_RAM_BASE (0x180000)
2832		-#define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000)
	2468	+/* 4373 PMU resources */
	2469	+#define RES4373_LPLDO_PU 0
	2470	+#define RES4373_BG_PU 1
	2471	+#define RES4373_PMU_SLEEP 2
	2472	+#define RES4373_PALDO3P3_PU 3
	2473	+#define RES4373_CBUCK_LPOM_PU 4
	2474	+#define RES4373_CBUCK_PFM_PU 5
	2475	+#define RES4373_COLD_START_WAIT 6
	2476	+#define RES4373_RSVD_7 7
	2477	+#define RES4373_LNLDO_PU 8
	2478	+#define RES4373_XTALLDO_PU 9
	2479	+#define RES4373_LDO3P3_PU 10
	2480	+#define RES4373_OTP_PU 11
	2481	+#define RES4373_XTAL_PU 12
	2482	+#define RES4373_SR_CLK_START 13
	2483	+#define RES4373_LQ_AVAIL 14
	2484	+#define RES4373_LQ_START 15
	2485	+#define RES4373_PERST_OVR 16
	2486	+#define RES4373_WL_CORE_RDY 17
	2487	+#define RES4373_ILP_REQ 18
	2488	+#define RES4373_ALP_AVAIL 19
	2489	+#define RES4373_MINI_PMU 20
	2490	+#define RES4373_RADIO_PU 21
	2491	+#define RES4373_SR_CLK_STABLE 22
	2492	+#define RES4373_SR_SAVE_RESTORE 23
	2493	+#define RES4373_SR_PHY_PWRSW 24
	2494	+#define RES4373_SR_VDDM_PWRSW 25
	2495	+#define RES4373_SR_SUBCORE_PWRSW 26
	2496	+#define RES4373_SR_SLEEP 27
	2497	+#define RES4373_HT_START 28
	2498	+#define RES4373_HT_AVAIL 29
	2499	+#define RES4373_MACPHY_CLKAVAIL 30
	2500	+/* SR Control0 bits */
	2501	+#define CC_SR0_4349_SR_ENG_EN_MASK 0x1
	2502	+#define CC_SR0_4349_SR_ENG_EN_SHIFT 0
	2503	+#define CC_SR0_4349_SR_ENG_CLK_EN (1 << 1)
	2504	+#define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2)
	2505	+#define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6)
	2506	+#define CC_SR0_4349_SR_MEM_STBY_ALLOW_MSK (1 << 16)
	2507	+#define CC_SR0_4349_SR_MEM_STBY_ALLOW_SHIFT 16
	2508	+#define CC_SR0_4349_SR_ENABLE_ILP (1 << 17)
	2509	+#define CC_SR0_4349_SR_ENABLE_ALP (1 << 18)
	2510	+#define CC_SR0_4349_SR_ENABLE_HT (1 << 19)
	2511	+#define CC_SR0_4349_SR_ALLOW_PIC (3 << 20)
	2512	+#define CC_SR0_4349_SR_PMU_MEM_DISABLE (1 << 30)
	2513	+/* SR Control0 bits */
	2514	+#define CC_SR0_4349_SR_ENG_EN_MASK 0x1
	2515	+#define CC_SR0_4349_SR_ENG_EN_SHIFT 0
	2516	+#define CC_SR0_4349_SR_ENG_CLK_EN (1 << 1)
	2517	+#define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2)
	2518	+#define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6)
	2519	+#define CC_SR0_4349_SR_MEM_STBY_ALLOW (1 << 16)
	2520	+#define CC_SR0_4349_SR_ENABLE_ILP (1 << 17)
	2521	+#define CC_SR0_4349_SR_ENABLE_ALP (1 << 18)
	2522	+#define CC_SR0_4349_SR_ENABLE_HT (1 << 19)
	2523	+#define CC_SR0_4349_SR_ALLOW_PIC (3 << 20)
	2524	+#define CC_SR0_4349_SR_PMU_MEM_DISABLE (1 << 30)
2833	2525
2834	2526	/* SR binary offset is at 8K */
2835	2527	#define CC_SR1_4349_SR_ASM_ADDR (0x10)
2836		-
2837	2528	#define CST4349_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
2838	2529	#define CST4349_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
2839		-
2840	2530	#define CST4349_SPROM_PRESENT 0x00000010
2841	2531
	2532	+/* 4373 related */
	2533	+#define CST4373_CHIPMODE_USB20D(cs) (((cs) & (1 << 8)) != 0) /* USB */
	2534	+#define CST4373_CHIPMODE_SDIOD(cs) (((cs) & (1 << 7)) != 0) /* SDIO */
	2535	+#define CST4373_CHIPMODE_PCIE(cs) (((cs) & (1 << 6)) != 0) /* PCIE */
	2536	+#define CST4373_SFLASH_PRESENT 0x00000010
	2537	+
	2538	+#define VREG4_4349_MEMLPLDO_PWRUP_MASK (1 << 31)
	2539	+#define VREG4_4349_MEMLPLDO_PWRUP_SHIFT (31)
	2540	+#define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_MASK (0x7 << 15)
	2541	+#define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_SHIFT (15)
	2542	+#define CC2_4349_PHY_PWRSE_RST_CNT_MASK (0xF << 0)
	2543	+#define CC2_4349_PHY_PWRSE_RST_CNT_SHIFT (0)
2842	2544	#define CC2_4349_VDDM_PWRSW_EN_MASK (1 << 20)
2843	2545	#define CC2_4349_VDDM_PWRSW_EN_SHIFT (20)
	2546	+#define CC2_4349_MEMLPLDO_PWRSW_EN_MASK (1 << 21)
	2547	+#define CC2_4349_MEMLPLDO_PWRSW_EN_SHIFT (21)
2844	2548	#define CC2_4349_SDIO_AOS_WAKEUP_MASK (1 << 24)
2845	2549	#define CC2_4349_SDIO_AOS_WAKEUP_SHIFT (24)
	2550	+#define CC2_4349_PMUWAKE_EN_MASK (1 << 31)
	2551	+#define CC2_4349_PMUWAKE_EN_SHIFT (31)
2846	2552
	2553	+#define CC5_4349_MAC_PHY_CLK_8_DIV (1 << 27)
2847	2554
2848	2555	#define CC6_4349_PCIE_CLKREQ_WAKEUP_MASK (1 << 4)
2849	2556	#define CC6_4349_PCIE_CLKREQ_WAKEUP_SHIFT (4)
2850	2557	#define CC6_4349_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6)
2851	2558	#define CC6_4349_PMU_WAKEUP_ALPAVAIL_SHIFT (6)
2852	2559	#define CC6_4349_PMU_EN_EXT_PERST_MASK (1 << 13)
	2560	+#define CC6_4349_PMU_EN_L2_DEASSERT_MASK (1 << 14)
	2561	+#define CC6_4349_PMU_EN_L2_DEASSERT_SHIF (14)
2853	2562	#define CC6_4349_PMU_ENABLE_L2REFCLKPAD_PWRDWN (1 << 15)
2854	2563	#define CC6_4349_PMU_EN_MDIO_MASK (1 << 16)
2855	2564	#define CC6_4349_PMU_EN_ASSERT_L2_MASK (1 << 25)
2856	2565
2857		-#define CR4_4373_RAM_BASE (0x160000)
	2566	+/* 4349 GCI function sel values */
	2567	+/*
	2568	+ * Reference
	2569	+ * http://hwnbu-twiki.sj.broadcom.com/bin/view/Mwgroup/ToplevelArchitecture4349B0#Function_Sel
	2570	+ */
	2571	+#define CC4349_FNSEL_HWDEF (0)
	2572	+#define CC4349_FNSEL_SAMEASPIN (1)
	2573	+#define CC4349_FNSEL_GPIO (2)
	2574	+#define CC4349_FNSEL_FAST_UART (3)
	2575	+#define CC4349_FNSEL_GCI0 (4)
	2576	+#define CC4349_FNSEL_GCI1 (5)
	2577	+#define CC4349_FNSEL_DGB_UART (6)
	2578	+#define CC4349_FNSEL_I2C (7)
	2579	+#define CC4349_FNSEL_SPROM (8)
	2580	+#define CC4349_FNSEL_MISC0 (9)
	2581	+#define CC4349_FNSEL_MISC1 (10)
	2582	+#define CC4349_FNSEL_MISC2 (11)
	2583	+#define CC4349_FNSEL_IND (12)
	2584	+#define CC4349_FNSEL_PDN (13)
	2585	+#define CC4349_FNSEL_PUP (14)
	2586	+#define CC4349_FNSEL_TRISTATE (15)
2858	2587
2859		-#define CST4373_JTAG_ENABLE(cs) (((cs) & (1 << 0)) != 0)
2860		-#define CST4373_CHIPMODE_RSRC_INIT0(cs) (((cs) & (1 << 1)) != 0)
2861		-#define CST4373_SFLASH_PRESENT(cs) (((cs) & (1 << 4)) != 0)
2862		-#define CST4373_SDIO_PADVDDIO(cs) (((cs) & (1 << 5)) != 0)
2863		-#define CST4373_CHIPMODE_PCIE(cs) (((cs) & (1 << 6)) != 0)
2864		-#define CST4373_CHIPMODE_SDIOD(cs) (((cs) & (1 << 7)) != 0)
2865		-#define CST4373_CHIPMODE_USB20D(cs) (((cs) & (1 << 8)) != 0)
2866		-#define CST4373_USBHUB_BYPASS(cs) (((cs) & (1 << 9)) != 0)
2867		-#define STRAP4373_CHIPMODE_RSRC_INIT1 0x1
2868		-#define STRAP4373_VTRIM_EN 0x1
2869		-#define STRAP4373_SFLASH_PRESENT 0x1
2870		-#define OTP4373_SFLASH_BYTE_OFFSET 680
2871		-#define OTP4373_SFLASH_MASK 0x3F
2872		-#define OTP4373_SFLASH_PRESENT_MASK 0x1
2873		-#define OTP4373_SFLASH_TYPE_MASK 0x2
2874		-#define OTP4373_SFLASH_TYPE_SHIFT 0x1
2875		-#define OTP4373_SFLASH_CLKDIV_MASK 0x3C
2876		-#define OTP4373_SFLASH_CLKDIV_SHIFT 0x2
2877		-#define SPROM4373_OTP_SELECT 0x00000010
2878		-#define SPROM4373_OTP_PRESENT 0x00000020
2879		-#define CC4373_SFLASH_CLKDIV_MASK 0x1F000000
2880		-#define CC4373_SFLASH_CLKDIV_SHIFT 25
	2588	+/* 4364 related */
	2589	+#define RES4364_LPLDO_PU 0
	2590	+#define RES4364_BG_PU 1
	2591	+#define RES4364_MEMLPLDO_PU 2
	2592	+#define RES4364_PALDO3P3_PU 3
	2593	+#define RES4364_CBUCK_1P2 4
	2594	+#define RES4364_CBUCK_1V8 5
	2595	+#define RES4364_COLD_START_WAIT 6
	2596	+#define RES4364_SR_3x3_VDDM_PWRSW 7
	2597	+#define RES4364_3x3_MACPHY_CLKAVAIL 8
	2598	+#define RES4364_XTALLDO_PU 9
	2599	+#define RES4364_LDO3P3_PU 10
	2600	+#define RES4364_OTP_PU 11
	2601	+#define RES4364_XTAL_PU 12
	2602	+#define RES4364_SR_CLK_START 13
	2603	+#define RES4364_3x3_RADIO_PU 14
	2604	+#define RES4364_RF_LDO 15
	2605	+#define RES4364_PERST_OVR 16
	2606	+#define RES4364_WL_CORE_RDY 17
	2607	+#define RES4364_ILP_REQ 18
	2608	+#define RES4364_ALP_AVAIL 19
	2609	+#define RES4364_1x1_MINI_PMU 20
	2610	+#define RES4364_1x1_RADIO_PU 21
	2611	+#define RES4364_SR_CLK_STABLE 22
	2612	+#define RES4364_SR_SAVE_RESTORE 23
	2613	+#define RES4364_SR_PHY_PWRSW 24
	2614	+#define RES4364_SR_VDDM_PWRSW 25
	2615	+#define RES4364_SR_SUBCORE_PWRSW 26
	2616	+#define RES4364_SR_SLEEP 27
	2617	+#define RES4364_HT_START 28
	2618	+#define RES4364_HT_AVAIL 29
	2619	+#define RES4364_MACPHY_CLKAVAIL 30
2881	2620
	2621	+/* 4349 GPIO */
	2622	+#define CC4349_PIN_GPIO_00 (0)
	2623	+#define CC4349_PIN_GPIO_01 (1)
	2624	+#define CC4349_PIN_GPIO_02 (2)
	2625	+#define CC4349_PIN_GPIO_03 (3)
	2626	+#define CC4349_PIN_GPIO_04 (4)
	2627	+#define CC4349_PIN_GPIO_05 (5)
	2628	+#define CC4349_PIN_GPIO_06 (6)
	2629	+#define CC4349_PIN_GPIO_07 (7)
	2630	+#define CC4349_PIN_GPIO_08 (8)
	2631	+#define CC4349_PIN_GPIO_09 (9)
	2632	+#define CC4349_PIN_GPIO_10 (10)
	2633	+#define CC4349_PIN_GPIO_11 (11)
	2634	+#define CC4349_PIN_GPIO_12 (12)
	2635	+#define CC4349_PIN_GPIO_13 (13)
	2636	+#define CC4349_PIN_GPIO_14 (14)
	2637	+#define CC4349_PIN_GPIO_15 (15)
	2638	+#define CC4349_PIN_GPIO_16 (16)
	2639	+#define CC4349_PIN_GPIO_17 (17)
	2640	+#define CC4349_PIN_GPIO_18 (18)
	2641	+#define CC4349_PIN_GPIO_19 (19)
2882	2642
	2643	+/* Mask used to decide whether HOSTWAKE MUX to be performed or not */
	2644	+#define MUXENAB4349_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */
	2645	+#define MUXENAB4349_HOSTWAKE_SHIFT 4
	2646	+#define MUXENAB4349_GETIX(val, name) \
	2647	+ ((((val) & MUXENAB4349_ ## name ## _MASK) >> MUXENAB4349_ ## name ## _SHIFT) - 1)
	2648	+
	2649	+#define CR4_4364_RAM_BASE (0x160000)
	2650	+
	2651	+/* SR binary offset is at 8K */
	2652	+#define CC_SR1_4364_SR_CORE0_ASM_ADDR (0x10)
	2653	+#define CC_SR1_4364_SR_CORE1_ASM_ADDR (0x10)
	2654	+
	2655	+#define CC_SR0_4364_SR_ENG_EN_MASK 0x1
	2656	+#define CC_SR0_4364_SR_ENG_EN_SHIFT 0
	2657	+#define CC_SR0_4364_SR_ENG_CLK_EN (1 << 1)
	2658	+#define CC_SR0_4364_SR_RSRC_TRIGGER (0xC << 2)
	2659	+#define CC_SR0_4364_SR_WD_MEM_MIN_DIV (0x3 << 6)
	2660	+#define CC_SR0_4364_SR_MEM_STBY_ALLOW_MSK (1 << 16)
	2661	+#define CC_SR0_4364_SR_MEM_STBY_ALLOW_SHIFT 16
	2662	+#define CC_SR0_4364_SR_ENABLE_ILP (1 << 17)
	2663	+#define CC_SR0_4364_SR_ENABLE_ALP (1 << 18)
	2664	+#define CC_SR0_4364_SR_ENABLE_HT (1 << 19)
	2665	+#define CC_SR0_4364_SR_INVERT_CLK (1 << 11)
	2666	+#define CC_SR0_4364_SR_ALLOW_PIC (3 << 20)
	2667	+#define CC_SR0_4364_SR_PMU_MEM_DISABLE (1 << 30)
	2668	+
	2669	+#define PMU_4364_CC1_ENABLE_BBPLL_PWR_DWN (0x1 << 4)
	2670	+#define PMU_4364_CC1_BBPLL_ARESET_LQ_TIME (0x1 << 8)
	2671	+#define PMU_4364_CC1_BBPLL_ARESET_HT_UPTIME (0x1 << 10)
	2672	+#define PMU_4364_CC1_BBPLL_DRESET_LQ_UPTIME (0x1 << 12)
	2673	+#define PMU_4364_CC1_BBPLL_DRESET_HT_UPTIME (0x4 << 16)
	2674	+#define PMU_4364_CC1_SUBCORE_PWRSW_UP_DELAY (0x8 << 20)
	2675	+#define PMU_4364_CC1_SUBCORE_PWRSW_RESET_CNT (0x4 << 24)
	2676	+
	2677	+#define PMU_4364_CC2_PHY_PWRSW_RESET_CNT (0x2 << 0)
	2678	+#define PMU_4364_CC2_PHY_PWRSW_RESET_MASK (0x7)
	2679	+#define PMU_4364_CC2_SEL_CHIPC_IF_FOR_SR (1 << 21)
	2680	+
	2681	+#define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_MASK (1 << 23)
	2682	+#define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_MASK (1 << 24)
	2683	+#define PMU_4364_CC3_CBUCK1P2_PU_SR_VDDM_REQ_ON (1 << 25)
	2684	+#define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_OFF (0)
	2685	+#define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_OFF (0)
	2686	+
	2687	+#define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2_MASK (1 << 26)
	2688	+#define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_MASK (1 << 4)
	2689	+#define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2 (1 << 26)
	2690	+#define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_OFF (0)
	2691	+
	2692	+#define PMU_4364_CC6_MDI_RESET_MASK (1 << 16)
	2693	+#define PMU_4364_CC6_USE_CLK_REQ_MASK (1 << 18)
	2694	+#define PMU_4364_CC6_HIGHER_CLK_REQ_ALP_MASK (1 << 20)
	2695	+#define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL_MASK (1 << 21)
	2696	+#define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL_MASK (1 << 22)
	2697	+#define PMU_4364_CC6_MDI_RESET (1 << 16)
	2698	+#define PMU_4364_CC6_USE_CLK_REQ (1 << 18)
	2699	+
	2700	+#define PMU_4364_CC6_HIGHER_CLK_REQ_ALP (1 << 20)
	2701	+#define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL (1 << 21)
	2702	+#define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL (1 << 22)
	2703	+
	2704	+#define PMU_4364_VREG0_DISABLE_BT_PULL_DOWN (1 << 2)
	2705	+#define PMU_4364_VREG1_DISABLE_WL_PULL_DOWN (1 << 2)
	2706	+
	2707	+/* Indices of PMU voltage regulator registers */
	2708	+#define PMU_VREG_0 (0u)
	2709	+#define PMU_VREG_1 (1u)
	2710	+#define PMU_VREG_2 (2u)
	2711	+#define PMU_VREG_3 (3u)
	2712	+#define PMU_VREG_4 (4u)
	2713	+#define PMU_VREG_5 (5u)
	2714	+#define PMU_VREG_6 (6u)
	2715	+#define PMU_VREG_7 (7u)
	2716	+#define PMU_VREG_8 (8u)
	2717	+#define PMU_VREG_9 (9u)
	2718	+#define PMU_VREG_10 (10u)
	2719	+#define PMU_VREG_11 (11u)
	2720	+#define PMU_VREG_12 (12u)
	2721	+#define PMU_VREG_13 (13u)
	2722	+#define PMU_VREG_14 (14u)
	2723	+#define PMU_VREG_15 (15u)
	2724	+#define PMU_VREG_16 (16u)
	2725	+
	2726	+/* 43012 Chipcommon ChipStatus bits */
	2727	+#define CST43012_FLL_LOCK (1 << 13)
	2728	+/* 43012 resources - End */
	2729	+
	2730	+/* 43012 related Cbuck modes */
	2731	+#define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03
	2732	+#define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490
	2733	+#define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03
	2734	+#define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410
	2735	+
	2736	+/* 43012 related dynamic cbuck mode mask */
	2737	+#define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFC07
	2738	+#define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFFFF
	2739	+
	2740	+/* 4369 related VREG masks */
	2741	+#define PMU_4369_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u)
	2742	+#define PMU_4369_VREG_5_MISCLDO_POWER_UP_SHIFT 11u
	2743	+#define PMU_4369_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u)
	2744	+#define PMU_4369_VREG_5_LPLDO_POWER_UP_SHIFT 27u
	2745	+#define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28)
	2746	+#define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT 28u
	2747	+
	2748	+#define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u)
	2749	+#define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT 3u
	2750	+
	2751	+#define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u)
	2752	+#define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_SHIFT 27u
	2753	+#define PMU_4369_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u)
	2754	+#define PMU_4369_VREG_7_WL_PMU_LP_MODE_SHIFT 28u
	2755	+#define PMU_4369_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u)
	2756	+#define PMU_4369_VREG_7_WL_PMU_LV_MODE_SHIFT 29u
	2757	+
	2758	+#define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0)
	2759	+#define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u
	2760	+
	2761	+#define PMU_4369_VREG13_RSRC_EN_ASR_MASK4_MASK BCM_MASK32(10, 9)
	2762	+#define PMU_4369_VREG13_RSRC_EN_ASR_MASK4_SHIFT 9u
	2763	+
	2764	+#define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u)
	2765	+#define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT 23u
	2766	+
	2767	+#define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0)
	2768	+#define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u
	2769	+#define PMU_4369_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15)
	2770	+#define PMU_4369_VREG16_RSRC0_ABUCK_MODE_SHIFT 15u
	2771	+#define PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18)
	2772	+#define PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT 18u
	2773	+
	2774	+/* 4364 related VREG masks */
	2775	+#define PMU_4364_VREG3_DISABLE_WPT_REG_ON_PULL_DOWN (1 << 11)
	2776	+
	2777	+#define PMU_4364_VREG4_MEMLPLDO_PU_ON (1 << 31)
	2778	+#define PMU_4364_VREG4_LPLPDO_ADJ (3 << 16)
	2779	+#define PMU_4364_VREG4_LPLPDO_ADJ_MASK (3 << 16)
	2780	+#define PMU_4364_VREG5_MAC_CLK_1x1_AUTO (0x1 << 18)
	2781	+#define PMU_4364_VREG5_SR_AUTO (0x1 << 20)
	2782	+#define PMU_4364_VREG5_BT_PWM_MASK (0x1 << 21)
	2783	+#define PMU_4364_VREG5_BT_AUTO (0x1 << 22)
	2784	+#define PMU_4364_VREG5_WL2CLB_DVFS_EN_MASK (0x1 << 23)
	2785	+#define PMU_4364_VREG5_BT_PWMK (0)
	2786	+#define PMU_4364_VREG5_WL2CLB_DVFS_EN (0)
	2787	+
	2788	+#define PMU_4364_VREG6_BBPLL_AUTO (0x1 << 17)
	2789	+#define PMU_4364_VREG6_MINI_PMU_PWM (0x1 << 18)
	2790	+#define PMU_4364_VREG6_LNLDO_AUTO (0x1 << 21)
	2791	+#define PMU_4364_VREG6_PCIE_PWRDN_0_AUTO (0x1 << 23)
	2792	+#define PMU_4364_VREG6_PCIE_PWRDN_1_AUTO (0x1 << 25)
	2793	+#define PMU_4364_VREG6_MAC_CLK_3x3_PWM (0x1 << 27)
	2794	+#define PMU_4364_VREG6_ENABLE_FINE_CTRL (0x1 << 30)
	2795	+
	2796	+#define PMU_4364_PLL0_DISABLE_CHANNEL6 (0x1 << 18)
	2797	+
	2798	+#define CC_GCI1_REG (0x1)
	2799	+#define CC_GCI1_4364_IND_STATE_FOR_GPIO9_11 (0x0ccccccc)
	2800	+#define CC2_4364_SDIO_AOS_WAKEUP_MASK (1 << 24)
	2801	+#define CC2_4364_SDIO_AOS_WAKEUP_SHIFT (24)
	2802	+
	2803	+#define CC6_4364_PCIE_CLKREQ_WAKEUP_MASK (1 << 4)
	2804	+#define CC6_4364_PCIE_CLKREQ_WAKEUP_SHIFT (4)
	2805	+#define CC6_4364_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6)
	2806	+#define CC6_4364_PMU_WAKEUP_ALPAVAIL_SHIFT (6)
	2807	+
	2808	+#define CST4364_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
	2809	+#define CST4364_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
	2810	+#define CST4364_SPROM_PRESENT 0x00000010
	2811	+
	2812	+#define PMU_4364_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF
	2813	+#define PMU_4364_MACCORE_1_RES_REQ_MASK 0x7FFB3647
	2814	+
	2815	+#define PMU_4364_RSDB_MODE (0)
	2816	+#define PMU_4364_1x1_MODE (1)
	2817	+#define PMU_4364_3x3_MODE (2)
	2818	+
	2819	+#define PMU_4364_MAX_MASK_1x1 (0x7FFF3E47)
	2820	+#define PMU_4364_MAX_MASK_RSDB (0x7FFFFFFF)
	2821	+#define PMU_4364_MAX_MASK_3x3 (0x3FCFFFFF)
	2822	+
	2823	+#define PMU_4364_SAVE_RESTORE_UPDNTIME_1x1 (0xC000C)
	2824	+#define PMU_4364_SAVE_RESTORE_UPDNTIME_3x3 (0xF000F)
	2825	+
	2826	+#define FORCE_CLK_ON 1
	2827	+#define FORCE_CLK_OFF 0
	2828	+
	2829	+#define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0)
	2830	+#define PMU1_PLL0_SWITCH_MACCLOCK_160MHZ (1)
	2831	+#define TSF_CLK_FRAC_L_4364_120MHZ 0x8889
	2832	+#define TSF_CLK_FRAC_H_4364_120MHZ 0x8
	2833	+#define TSF_CLK_FRAC_L_4364_160MHZ 0x6666
	2834	+#define TSF_CLK_FRAC_H_4364_160MHZ 0x6
	2835	+#define PMU1_PLL0_PC1_M2DIV_VALUE_120MHZ 8
	2836	+#define PMU1_PLL0_PC1_M2DIV_VALUE_160MHZ 6
	2837	+
	2838	+/* 4347/4369 Related */
	2839	+
	2840	+/*
	2841	+ * PMU VREG Definitions:
	2842	+ * http://confluence.broadcom.com/display/WLAN/BCM4347+PMU+Vreg+Control+Register
	2843	+ * http://confluence.broadcom.com/display/WLAN/BCM4369+PMU+Vreg+Control+Register
	2844	+ */
	2845	+/* PMU VREG4 */
	2846	+#define PMU_28NM_VREG4_WL_LDO_CNTL_EN (0x1 << 10)
	2847	+
	2848	+/* PMU VREG6 */
	2849	+#define PMU_28NM_VREG6_BTLDO3P3_PU (0x1 << 12)
	2850	+
	2851	+/* PMU resources */
	2852	+#define RES4347_MEMLPLDO_PU 0
	2853	+#define RES4347_AAON 1
	2854	+#define RES4347_PMU_SLEEP 2
	2855	+#define RES4347_RESERVED_3 3
	2856	+#define RES4347_LDO3P3_PU 4
	2857	+#define RES4347_FAST_LPO_AVAIL 5
	2858	+#define RES4347_XTAL_PU 6
	2859	+#define RES4347_XTAL_STABLE 7
	2860	+#define RES4347_PWRSW_DIG 8
	2861	+#define RES4347_SR_DIG 9
	2862	+#define RES4347_SLEEP_DIG 10
	2863	+#define RES4347_PWRSW_AUX 11
	2864	+#define RES4347_SR_AUX 12
	2865	+#define RES4347_SLEEP_AUX 13
	2866	+#define RES4347_PWRSW_MAIN 14
	2867	+#define RES4347_SR_MAIN 15
	2868	+#define RES4347_SLEEP_MAIN 16
	2869	+#define RES4347_CORE_RDY_DIG 17
	2870	+#define RES4347_CORE_RDY_AUX 18
	2871	+#define RES4347_ALP_AVAIL 19
	2872	+#define RES4347_RADIO_AUX_PU 20
	2873	+#define RES4347_MINIPMU_AUX_PU 21
	2874	+#define RES4347_CORE_RDY_MAIN 22
	2875	+#define RES4347_RADIO_MAIN_PU 23
	2876	+#define RES4347_MINIPMU_MAIN_PU 24
	2877	+#define RES4347_PCIE_EP_PU 25
	2878	+#define RES4347_COLD_START_WAIT 26
	2879	+#define RES4347_ARMHTAVAIL 27
	2880	+#define RES4347_HT_AVAIL 28
	2881	+#define RES4347_MACPHY_AUX_CLK_AVAIL 29
	2882	+#define RES4347_MACPHY_MAIN_CLK_AVAIL 30
	2883	+#define RES4347_RESERVED_31 31
	2884	+
	2885	+/* 4369 PMU Resources */
	2886	+#define RES4369_DUMMY 0
	2887	+#define RES4369_ABUCK 1
	2888	+#define RES4369_PMU_SLEEP 2
	2889	+#define RES4369_MISCLDO 3
	2890	+#define RES4369_LDO3P3 4
	2891	+#define RES4369_FAST_LPO_AVAIL 5
	2892	+#define RES4369_XTAL_PU 6
	2893	+#define RES4369_XTAL_STABLE 7
	2894	+#define RES4369_PWRSW_DIG 8
	2895	+#define RES4369_SR_DIG 9
	2896	+#define RES4369_SLEEP_DIG 10
	2897	+#define RES4369_PWRSW_AUX 11
	2898	+#define RES4369_SR_AUX 12
	2899	+#define RES4369_SLEEP_AUX 13
	2900	+#define RES4369_PWRSW_MAIN 14
	2901	+#define RES4369_SR_MAIN 15
	2902	+#define RES4369_SLEEP_MAIN 16
	2903	+#define RES4369_DIG_CORE_RDY 17
	2904	+#define RES4369_CORE_RDY_AUX 18
	2905	+#define RES4369_ALP_AVAIL 19
	2906	+#define RES4369_RADIO_AUX_PU 20
	2907	+#define RES4369_MINIPMU_AUX_PU 21
	2908	+#define RES4369_CORE_RDY_MAIN 22
	2909	+#define RES4369_RADIO_MAIN_PU 23
	2910	+#define RES4369_MINIPMU_MAIN_PU 24
	2911	+#define RES4369_PCIE_EP_PU 25
	2912	+#define RES4369_COLD_START_WAIT 26
	2913	+#define RES4369_ARMHTAVAIL 27
	2914	+#define RES4369_HT_AVAIL 28
	2915	+#define RES4369_MACPHY_AUX_CLK_AVAIL 29
	2916	+#define RES4369_MACPHY_MAIN_CLK_AVAIL 30
	2917	+
	2918	+/* chip status */
	2919	+#define CST4347_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
	2920	+#define CST4347_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
	2921	+#define CST4347_JTAG_STRAP_ENABLED(cs) (((cs) & (1 << 20)) != 0) /* JTAG strap st */
	2922	+#define CST4347_SPROM_PRESENT 0x00000010
	2923	+
	2924	+/* GCI chip status */
	2925	+#define GCI_CS_4347_FLL1MHZ_LOCK_MASK (1 << 1)
	2926	+
	2927	+/* GCI chip control registers */
	2928	+#define GCI_CC7_AAON_BYPASS_PWRSW_SEL 13
	2929	+#define GCI_CC7_AAON_BYPASS_PWRSW_SEQ_ON 14
	2930	+
	2931	+/* PMU chip control registers */
	2932	+#define CC2_4347_VASIP_MEMLPLDO_VDDB_OFF_MASK (1 << 11)
	2933	+#define CC2_4347_VASIP_MEMLPLDO_VDDB_OFF_SHIFT 11
	2934	+#define CC2_4347_MAIN_MEMLPLDO_VDDB_OFF_MASK (1 << 12)
	2935	+#define CC2_4347_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12
	2936	+#define CC2_4347_AUX_MEMLPLDO_VDDB_OFF_MASK (1 << 13)
	2937	+#define CC2_4347_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13
	2938	+#define CC2_4347_VASIP_VDDRET_ON_MASK (1 << 14)
	2939	+#define CC2_4347_VASIP_VDDRET_ON_SHIFT 14
	2940	+#define CC2_4347_MAIN_VDDRET_ON_MASK (1 << 15)
	2941	+#define CC2_4347_MAIN_VDDRET_ON_SHIFT 15
	2942	+#define CC2_4347_AUX_VDDRET_ON_MASK (1 << 16)
	2943	+#define CC2_4347_AUX_VDDRET_ON_SHIFT 16
	2944	+#define CC2_4347_GCI2WAKE_MASK (1 << 31)
	2945	+#define CC2_4347_GCI2WAKE_SHIFT 31
	2946	+
	2947	+#define CC2_4347_SDIO_AOS_WAKEUP_MASK (1 << 24)
	2948	+#define CC2_4347_SDIO_AOS_WAKEUP_SHIFT 24
	2949	+
	2950	+#define CC4_4347_LHL_TIMER_SELECT (1 << 0)
	2951	+
	2952	+#define CC6_4347_PWROK_WDT_EN_IN_MASK (1 << 6)
	2953	+#define CC6_4347_PWROK_WDT_EN_IN_SHIFT 6
	2954	+
	2955	+#define CC6_4347_SDIO_AOS_CHIP_WAKEUP_MASK (1 << 24)
	2956	+#define CC6_4347_SDIO_AOS_CHIP_WAKEUP_SHIFT 24
	2957	+
	2958	+#define PCIE_GPIO1_GPIO_PIN CC_GCI_GPIO_0
	2959	+#define PCIE_PERST_GPIO_PIN CC_GCI_GPIO_1
	2960	+#define PCIE_CLKREQ_GPIO_PIN CC_GCI_GPIO_2
	2961	+
	2962	+#define VREG5_4347_MEMLPLDO_ADJ_MASK 0xF0000000
	2963	+#define VREG5_4347_MEMLPLDO_ADJ_SHIFT 28
	2964	+#define VREG5_4347_LPLDO_ADJ_MASK 0x00F00000
	2965	+#define VREG5_4347_LPLDO_ADJ_SHIFT 20
	2966	+
	2967	+/* lpldo/memlpldo voltage */
	2968	+#define PMU_VREG5_LPLDO_VOLT_0_88 0xf /* 0.88v */
	2969	+#define PMU_VREG5_LPLDO_VOLT_0_86 0xe /* 0.86v */
	2970	+#define PMU_VREG5_LPLDO_VOLT_0_84 0xd /* 0.84v */
	2971	+#define PMU_VREG5_LPLDO_VOLT_0_82 0xc /* 0.82v */
	2972	+#define PMU_VREG5_LPLDO_VOLT_0_80 0xb /* 0.80v */
	2973	+#define PMU_VREG5_LPLDO_VOLT_0_78 0xa /* 0.78v */
	2974	+#define PMU_VREG5_LPLDO_VOLT_0_76 0x9 /* 0.76v */
	2975	+#define PMU_VREG5_LPLDO_VOLT_0_74 0x8 /* 0.74v */
	2976	+#define PMU_VREG5_LPLDO_VOLT_0_72 0x7 /* 0.72v */
	2977	+#define PMU_VREG5_LPLDO_VOLT_1_10 0x6 /* 1.10v */
	2978	+#define PMU_VREG5_LPLDO_VOLT_1_00 0x5 /* 1.00v */
	2979	+#define PMU_VREG5_LPLDO_VOLT_0_98 0x4 /* 0.98v */
	2980	+#define PMU_VREG5_LPLDO_VOLT_0_96 0x3 /* 0.96v */
	2981	+#define PMU_VREG5_LPLDO_VOLT_0_94 0x2 /* 0.94v */
	2982	+#define PMU_VREG5_LPLDO_VOLT_0_92 0x1 /* 0.92v */
	2983	+#define PMU_VREG5_LPLDO_VOLT_0_90 0x0 /* 0.90v */
	2984	+
	2985	+/* Save/Restore engine */
	2986	+
	2987	+#define BM_ADDR_TO_SR_ADDR(bmaddr) ((bmaddr) >> 9)
	2988	+
	2989	+/* Txfifo is 512KB for main core and 128KB for aux core
	2990	+ * We use first 12kB (0x3000) in BMC buffer for template in main core and
	2991	+ * 6.5kB (0x1A00) in aux core, followed by ASM code
	2992	+ */
	2993	+#define SR_ASM_ADDR_MAIN_4347 (0x18)
	2994	+#define SR_ASM_ADDR_AUX_4347 (0xd)
	2995	+#define SR_ASM_ADDR_DIG_4347 (0x0)
	2996	+
	2997	+#define SR_ASM_ADDR_MAIN_4369 BM_ADDR_TO_SR_ADDR(0xC00)
	2998	+#define SR_ASM_ADDR_AUX_4369 BM_ADDR_TO_SR_ADDR(0xC00)
	2999	+#define SR_ASM_ADDR_DIG_4369 (0x0)
	3000	+
	3001	+/* 512 bytes block */
	3002	+#define SR_ASM_ADDR_BLK_SIZE_SHIFT 9
	3003	+
	3004	+/* SR Control0 bits */
	3005	+#define SR0_SR_ENG_EN_MASK 0x1
	3006	+#define SR0_SR_ENG_EN_SHIFT 0
	3007	+#define SR0_SR_ENG_CLK_EN (1 << 1)
	3008	+#define SR0_RSRC_TRIGGER (0xC << 2)
	3009	+#define SR0_WD_MEM_MIN_DIV (0x3 << 6)
	3010	+#define SR0_INVERT_SR_CLK (1 << 11)
	3011	+#define SR0_MEM_STBY_ALLOW (1 << 16)
	3012	+#define SR0_ENABLE_SR_ILP (1 << 17)
	3013	+#define SR0_ENABLE_SR_ALP (1 << 18)
	3014	+#define SR0_ENABLE_SR_HT (1 << 19)
	3015	+#define SR0_ALLOW_PIC (3 << 20)
	3016	+#define SR0_ENB_PMU_MEM_DISABLE (1 << 30)
	3017	+
	3018	+/* SR Control0 bits for 4369 */
	3019	+#define SR0_4369_SR_ENG_EN_MASK 0x1
	3020	+#define SR0_4369_SR_ENG_EN_SHIFT 0
	3021	+#define SR0_4369_SR_ENG_CLK_EN (1 << 1)
	3022	+#define SR0_4369_RSRC_TRIGGER (0xC << 2)
	3023	+#define SR0_4369_WD_MEM_MIN_DIV (0x2 << 6)
	3024	+#define SR0_4369_INVERT_SR_CLK (1 << 11)
	3025	+#define SR0_4369_MEM_STBY_ALLOW (1 << 16)
	3026	+#define SR0_4369_ENABLE_SR_ILP (1 << 17)
	3027	+#define SR0_4369_ENABLE_SR_ALP (1 << 18)
	3028	+#define SR0_4369_ENABLE_SR_HT (1 << 19)
	3029	+#define SR0_4369_ALLOW_PIC (3 << 20)
	3030	+#define SR0_4369_ENB_PMU_MEM_DISABLE (1 << 30)
	3031	+/* =========== LHL regs =========== */
	3032	+/* 4369 LHL register settings */
	3033	+#define LHL4369_UP_CNT 0
	3034	+#define LHL4369_DN_CNT 2
	3035	+#define LHL4369_PWRSW_EN_DWN_CNT (LHL4369_DN_CNT + 2)
	3036	+#define LHL4369_ISO_EN_DWN_CNT (LHL4369_PWRSW_EN_DWN_CNT + 3)
	3037	+#define LHL4369_SLB_EN_DWN_CNT (LHL4369_ISO_EN_DWN_CNT + 1)
	3038	+#define LHL4369_ASR_CLK4M_DIS_DWN_CNT (LHL4369_DN_CNT)
	3039	+#define LHL4369_ASR_LPPFM_MODE_DWN_CNT (LHL4369_DN_CNT)
	3040	+#define LHL4369_ASR_MODE_SEL_DWN_CNT (LHL4369_DN_CNT)
	3041	+#define LHL4369_ASR_MANUAL_MODE_DWN_CNT (LHL4369_DN_CNT)
	3042	+#define LHL4369_ASR_ADJ_DWN_CNT (LHL4369_DN_CNT)
	3043	+#define LHL4369_ASR_OVERI_DIS_DWN_CNT (LHL4369_DN_CNT)
	3044	+#define LHL4369_ASR_TRIM_ADJ_DWN_CNT (LHL4369_DN_CNT)
	3045	+#define LHL4369_VDDC_SW_DIS_DWN_CNT (LHL4369_SLB_EN_DWN_CNT + 1)
	3046	+#define LHL4369_VMUX_ASR_SEL_DWN_CNT (LHL4369_VDDC_SW_DIS_DWN_CNT + 1)
	3047	+#define LHL4369_CSR_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3048	+#define LHL4369_CSR_MODE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3049	+#define LHL4369_CSR_OVERI_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3050	+#define LHL4369_HPBG_CHOP_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3051	+#define LHL4369_SRBG_REF_SEL_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3052	+#define LHL4369_PFM_PWR_SLICE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3053	+#define LHL4369_CSR_TRIM_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3054	+#define LHL4369_CSR_VOLTAGE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1)
	3055	+#define LHL4369_HPBG_PU_EN_DWN_CNT (LHL4369_CSR_MODE_DWN_CNT + 1)
	3056	+
	3057	+#define LHL4369_HPBG_PU_EN_UP_CNT (LHL4369_UP_CNT + 1)
	3058	+#define LHL4369_CSR_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3059	+#define LHL4369_CSR_MODE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3060	+#define LHL4369_CSR_OVERI_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3061	+#define LHL4369_HPBG_CHOP_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3062	+#define LHL4369_SRBG_REF_SEL_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3063	+#define LHL4369_PFM_PWR_SLICE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3064	+#define LHL4369_CSR_TRIM_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3065	+#define LHL4369_CSR_VOLTAGE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1)
	3066	+#define LHL4369_VMUX_ASR_SEL_UP_CNT (LHL4369_CSR_MODE_UP_CNT + 1)
	3067	+#define LHL4369_VDDC_SW_DIS_UP_CNT (LHL4369_VMUX_ASR_SEL_UP_CNT + 1)
	3068	+#define LHL4369_SLB_EN_UP_CNT (LHL4369_VDDC_SW_DIS_UP_CNT + 8)
	3069	+#define LHL4369_ISO_EN_UP_CNT (LHL4369_SLB_EN_UP_CNT + 1)
	3070	+#define LHL4369_PWRSW_EN_UP_CNT (LHL4369_ISO_EN_UP_CNT + 3)
	3071	+#define LHL4369_ASR_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3072	+#define LHL4369_ASR_CLK4M_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3073	+#define LHL4369_ASR_LPPFM_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3074	+#define LHL4369_ASR_MODE_SEL_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3075	+#define LHL4369_ASR_MANUAL_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3076	+#define LHL4369_ASR_OVERI_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3077	+#define LHL4369_ASR_TRIM_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1)
	3078	+
	3079	+/* MacResourceReqTimer0/1 */
	3080	+#define MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT 24
	3081	+#define MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT 26
	3082	+#define MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT 27
	3083	+#define MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT 28
	3084	+#define MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT 29
	3085	+
	3086	+/* for pmu rev32 and higher */
	3087	+#define PMU32_MAC_MAIN_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) \| \
	3088	+ (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) \| \
	3089	+ (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) \| \
	3090	+ (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) \| \
	3091	+ (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
	3092	+
	3093	+#define PMU32_MAC_AUX_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) \| \
	3094	+ (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) \| \
	3095	+ (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) \| \
	3096	+ (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) \| \
	3097	+ (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT))
	3098	+
	3099	+/* 4369 related: 4369 parameters
	3100	+ * http://www.sj.broadcom.com/projects/BCM4369/gallery_backend.RC6.0/design/backplane/pmu_params.xls
	3101	+ */
	3102	+#define RES4369_DUMMY 0
	3103	+#define RES4369_ABUCK 1
	3104	+#define RES4369_PMU_SLEEP 2
	3105	+#define RES4369_MISCLDO_PU 3
	3106	+#define RES4369_LDO3P3_PU 4
	3107	+#define RES4369_FAST_LPO_AVAIL 5
	3108	+#define RES4369_XTAL_PU 6
	3109	+#define RES4369_XTAL_STABLE 7
	3110	+#define RES4369_PWRSW_DIG 8
	3111	+#define RES4369_SR_DIG 9
	3112	+#define RES4369_SLEEP_DIG 10
	3113	+#define RES4369_PWRSW_AUX 11
	3114	+#define RES4369_SR_AUX 12
	3115	+#define RES4369_SLEEP_AUX 13
	3116	+#define RES4369_PWRSW_MAIN 14
	3117	+#define RES4369_SR_MAIN 15
	3118	+#define RES4369_SLEEP_MAIN 16
	3119	+#define RES4369_DIG_CORE_RDY 17
	3120	+#define RES4369_CORE_RDY_AUX 18
	3121	+#define RES4369_ALP_AVAIL 19
	3122	+#define RES4369_RADIO_AUX_PU 20
	3123	+#define RES4369_MINIPMU_AUX_PU 21
	3124	+#define RES4369_CORE_RDY_MAIN 22
	3125	+#define RES4369_RADIO_MAIN_PU 23
	3126	+#define RES4369_MINIPMU_MAIN_PU 24
	3127	+#define RES4369_PCIE_EP_PU 25
	3128	+#define RES4369_COLD_START_WAIT 26
	3129	+#define RES4369_ARMHTAVAIL 27
	3130	+#define RES4369_HT_AVAIL 28
	3131	+#define RES4369_MACPHY_AUX_CLK_AVAIL 29
	3132	+#define RES4369_MACPHY_MAIN_CLK_AVAIL 30
	3133	+#define RES4369_RESERVED_31 31
	3134	+
	3135	+#define CST4369_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */
	3136	+#define CST4369_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */
	3137	+#define CST4369_SPROM_PRESENT 0x00000010
	3138	+
	3139	+#define PMU_4369_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF
	3140	+#define PMU_4369_MACCORE_1_RES_REQ_MASK 0x7FFB3647
2883	3141
2884	3142	/* 43430 PMU resources based on pmu_params.xls */
2885	3143	#define RES43430_LPLDO_PU 0
..	..	@@ -2930,10 +3188,28 @@
2930	3188	#define CST43430_TRIM_EN 0x00800000
2931	3189	#define CST43430_DIN_PACKAGE_OPTION 0x10000000
2932	3190
2933		-#define PMU_MACCORE_0_RES_REQ_TIMER 0x19000000
	3191	+#define PMU43430_PLL0_PC2_P1DIV_MASK 0x0000000f
	3192	+#define PMU43430_PLL0_PC2_P1DIV_SHIFT 0
	3193	+#define PMU43430_PLL0_PC2_NDIV_INT_MASK 0x0000ff80
	3194	+#define PMU43430_PLL0_PC2_NDIV_INT_SHIFT 7
	3195	+#define PMU43430_PLL0_PC4_MDIV2_MASK 0x0000ff00
	3196	+#define PMU43430_PLL0_PC4_MDIV2_SHIFT 8
	3197	+
	3198	+/* 43430 chip SR definitions */
	3199	+#define SRAM_43430_SR_ASM_ADDR 0x7f800
	3200	+#define CC_SR1_43430_SR_ASM_ADDR ((SRAM_43430_SR_ASM_ADDR - 0x60000) >> 8)
	3201	+
	3202	+/* 43430 PMU Chip Control bits */
	3203	+#define CC2_43430_SDIO_AOS_WAKEUP_MASK (1 << 24)
	3204	+#define CC2_43430_SDIO_AOS_WAKEUP_SHIFT (24)
	3205	+
	3206	+#define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000
2934	3207	#define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F
2935	3208
2936		-#define PMU_MACCORE_1_RES_REQ_TIMER 0x19000000
	3209	+#define PMU43012_MAC_RES_REQ_TIMER 0x1D000000
	3210	+#define PMU43012_MAC_RES_REQ_MASK 0x3FBBF7FF
	3211	+
	3212	+#define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000
2937	3213	#define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F
2938	3214
2939	3215	/* defines to detect active host interface in use */
..	..	@@ -2992,6 +3268,19 @@
2992	3268	#define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */
2993	3269	#define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */
2994	3270
	3271	+/* 55500, Dedicated sapce for TCAM_PATCH and TRX HDR area at RAMSTART */
	3272	+#define CR4_55500_RAM_START (0x3a0000)
	3273	+#define CR4_55500_TCAM_SZ (0x800)
	3274	+#define CR4_55500_TRX_HDR_SZ (0x2b4)
	3275	+/* 55560, Dedicated sapce for TCAM_PATCH and TRX HDR area at RAMSTART */
	3276	+#define CR4_55560_RAM_START (0x370000)
	3277	+#define CR4_55560_TCAM_SZ (0x800)
	3278	+#if defined BCMTRXV4
	3279	+#define CR4_55560_TRX_HDR_SZ (0x2b4)
	3280	+#else
	3281	+#define CR4_55560_TRX_HDR_SZ (0x20)
	3282	+#endif // endif
	3283	+
2995	3284	/* 4335 Chip specific ChipControl2 register bits */
2996	3285	#define CCTRL2_4335_AOSBLOCK (1 << 30)
2997	3286	#define CCTRL2_4335_PMUWAKE (1 << 31)
..	..	@@ -3000,11 +3289,46 @@
3000	3289	#define CR4_4345_LT_C0_RAM_BASE (0x1b0000)
3001	3290	#define CR4_4345_GE_C0_RAM_BASE (0x198000)
3002	3291	#define CR4_4349_RAM_BASE (0x180000)
	3292	+#define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000)
3003	3293	#define CR4_4350_RAM_BASE (0x180000)
3004	3294	#define CR4_4360_RAM_BASE (0x0)
3005	3295	#define CR4_43602_RAM_BASE (0x180000)
3006	3296	#define CA7_4365_RAM_BASE (0x200000)
	3297	+#define CR4_4373_RAM_BASE (0x160000)
	3298	+#define CST4373_JTAG_ENABLE(cs) (((cs) & (1 << 0)) != 0)
	3299	+#define CST4373_CHIPMODE_RSRC_INIT0(cs) (((cs) & (1 << 1)) != 0)
	3300	+#define CST4373_SDIO_PADVDDIO(cs) (((cs) & (1 << 5)) != 0)
	3301	+#define CST4373_USBHUB_BYPASS(cs) (((cs) & (1 << 9)) != 0)
	3302	+#define STRAP4373_CHIPMODE_RSRC_INIT1 0x1
	3303	+#define STRAP4373_VTRIM_EN 0x1
	3304	+#define STRAP4373_SFLASH_PRESENT 0x1
	3305	+#define OTP4373_SFLASH_BYTE_OFFSET 680
	3306	+#define OTP4373_SFLASH_MASK 0x3F
	3307	+#define OTP4373_SFLASH_PRESENT_MASK 0x1
	3308	+#define OTP4373_SFLASH_TYPE_MASK 0x2
	3309	+#define OTP4373_SFLASH_TYPE_SHIFT 0x1
	3310	+#define OTP4373_SFLASH_CLKDIV_MASK 0x3C
	3311	+#define OTP4373_SFLASH_CLKDIV_SHIFT 0x2
	3312	+#define SPROM4373_OTP_SELECT 0x00000010
	3313	+#define SPROM4373_OTP_PRESENT 0x00000020
	3314	+#define CC4373_SFLASH_CLKDIV_MASK 0x1F000000
	3315	+#define CC4373_SFLASH_CLKDIV_SHIFT 25
3007	3316
	3317	+#define CR4_4347_RAM_BASE (0x170000)
	3318	+#define CR4_4362_RAM_BASE (0x170000)
	3319	+#define CR4_4369_RAM_BASE (0x170000)
	3320	+#define CR4_4377_RAM_BASE (0x170000)
	3321	+#define CR4_43751_RAM_BASE (0x170000)
	3322	+#define CA7_4367_RAM_BASE (0x200000)
	3323	+#define CR4_4378_RAM_BASE (0x352000)
	3324	+#ifdef CHIPS_CUSTOMER_HW6
	3325	+#define CA7_4368_RAM_BASE (0x200000)
	3326	+#endif /* CHIPS_CUSTOMER_HW6 */
	3327	+/* TODO: Fix 55500 RAM BASE */
	3328	+#define CR4_55500_RAM_BASE (CR4_55500_RAM_START + CR4_55500_TCAM_SZ \
	3329	+ + CR4_55500_TRX_HDR_SZ)
	3330	+#define CR4_55560_RAM_BASE (CR4_55560_RAM_START + CR4_55560_TCAM_SZ \
	3331	+ + CR4_55560_TRX_HDR_SZ)
3008	3332
3009	3333	/* 4335 chip OTP present & OTP select bits. */
3010	3334	#define SPROM4335_OTP_SELECT 0x00000010
..	..	@@ -3025,7 +3349,6 @@
3025	3349	#define CC4335_SROM_OTP_SFLASH_TYPE 0x2
3026	3350	#define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C
3027	3351	#define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2
3028		-
3029	3352
3030	3353	/* 4335 chip OTP present & OTP select bits. */
3031	3354	#define SPROM4335_OTP_SELECT 0x00000010
..	..	@@ -3048,6 +3371,163 @@
3048	3371	#define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2
3049	3372
3050	3373	/* 4335 resources--END */
	3374	+
	3375	+/* 43012 PMU resources based on pmu_params.xls - Start */
	3376	+#define RES43012_MEMLPLDO_PU 0
	3377	+#define RES43012_PMU_SLEEP 1
	3378	+#define RES43012_FAST_LPO 2
	3379	+#define RES43012_BTLPO_3P3 3
	3380	+#define RES43012_SR_POK 4
	3381	+#define RES43012_DUMMY_PWRSW 5
	3382	+#define RES43012_DUMMY_LDO3P3 6
	3383	+#define RES43012_DUMMY_BT_LDO3P3 7
	3384	+#define RES43012_DUMMY_RADIO 8
	3385	+#define RES43012_VDDB_VDDRET 9
	3386	+#define RES43012_HV_LDO3P3 10
	3387	+#define RES43012_OTP_PU 11
	3388	+#define RES43012_XTAL_PU 12
	3389	+#define RES43012_SR_CLK_START 13
	3390	+#define RES43012_XTAL_STABLE 14
	3391	+#define RES43012_FCBS 15
	3392	+#define RES43012_CBUCK_MODE 16
	3393	+#define RES43012_CORE_READY 17
	3394	+#define RES43012_ILP_REQ 18
	3395	+#define RES43012_ALP_AVAIL 19
	3396	+#define RES43012_RADIOLDO_1P8 20
	3397	+#define RES43012_MINI_PMU 21
	3398	+#define RES43012_UNUSED 22
	3399	+#define RES43012_SR_SAVE_RESTORE 23
	3400	+#define RES43012_PHY_PWRSW 24
	3401	+#define RES43012_VDDB_CLDO 25
	3402	+#define RES43012_SUBCORE_PWRSW 26
	3403	+#define RES43012_SR_SLEEP 27
	3404	+#define RES43012_HT_START 28
	3405	+#define RES43012_HT_AVAIL 29
	3406	+#define RES43012_MACPHY_CLK_AVAIL 30
	3407	+#define CST43012_SPROM_PRESENT 0x00000010
	3408	+
	3409	+/* SR Control0 bits */
	3410	+#define SR0_43012_SR_ENG_EN_MASK 0x1
	3411	+#define SR0_43012_SR_ENG_EN_SHIFT 0
	3412	+#define SR0_43012_SR_ENG_CLK_EN (1 << 1)
	3413	+#define SR0_43012_SR_RSRC_TRIGGER (0xC << 2)
	3414	+#define SR0_43012_SR_WD_MEM_MIN_DIV (0x3 << 6)
	3415	+#define SR0_43012_SR_MEM_STBY_ALLOW_MSK (1 << 16)
	3416	+#define SR0_43012_SR_MEM_STBY_ALLOW_SHIFT 16
	3417	+#define SR0_43012_SR_ENABLE_ILP (1 << 17)
	3418	+#define SR0_43012_SR_ENABLE_ALP (1 << 18)
	3419	+#define SR0_43012_SR_ENABLE_HT (1 << 19)
	3420	+#define SR0_43012_SR_ALLOW_PIC (3 << 20)
	3421	+#define SR0_43012_SR_PMU_MEM_DISABLE (1 << 30)
	3422	+#define CC_43012_VDDM_PWRSW_EN_MASK (1 << 20)
	3423	+#define CC_43012_VDDM_PWRSW_EN_SHIFT (20)
	3424	+#define CC_43012_SDIO_AOS_WAKEUP_MASK (1 << 24)
	3425	+#define CC_43012_SDIO_AOS_WAKEUP_SHIFT (24)
	3426	+
	3427	+/* 43012 - offset at 5K */
	3428	+#define SR1_43012_SR_INIT_ADDR_MASK 0x3ff
	3429	+#define SR1_43012_SR_ASM_ADDR 0xA
	3430	+
	3431	+/* PLL usage in 43012 */
	3432	+#define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003f
	3433	+#define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0
	3434	+#define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00
	3435	+#define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT 10
	3436	+#define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00
	3437	+#define PMU43012_PLL0_PC3_PDIV_SHIFT 10
	3438	+#define PMU43012_PLL_NDIV_FRAC_BITS 20
	3439	+#define PMU43012_PLL_P_DIV_SCALE_BITS 10
	3440	+
	3441	+#define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003
	3442	+#define CCTL_43012_ARM_OFFCOUNT_SHIFT 0
	3443	+#define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000c
	3444	+#define CCTL_43012_ARM_ONCOUNT_SHIFT 2
	3445	+
	3446	+/* PMU Rev >= 30 */
	3447	+#define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000
	3448	+
	3449	+#define BCM7271_PMU30_ALPCLK_ONEMHZ_ENAB 0x00010000
	3450	+
	3451	+/* 43012 PMU Chip Control Registers */
	3452	+#define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010
	3453	+#define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040
	3454	+#define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800
	3455	+#define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000
	3456	+#define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000
	3457	+#define PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF (1 << 12)
	3458	+
	3459	+#define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000
	3460	+#define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000
	3461	+#define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000
	3462	+#define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000
	3463	+#define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000
	3464	+#define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000
	3465	+#define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000
	3466	+#define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000
	3467	+#define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000
	3468	+#define PMUCCTL04_43012_USE_LOCK 0x20000000
	3469	+#define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000
	3470	+#define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000
	3471	+#define PMUCCTL05_43012_DISABLE_SPM_CLK (1 << 8)
	3472	+#define PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN (1 << 14)
	3473	+#define PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB (1 << 31)
	3474	+#define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0
	3475	+#define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT 6
	3476	+#define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000
	3477	+#define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT 18
	3478	+#define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000
	3479	+#define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 24
	3480	+#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000
	3481	+#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 12
	3482	+#define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038
	3483	+#define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT 3
	3484	+
	3485	+#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_MASK 0x00000FC0
	3486	+#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_SHIFT 6
	3487	+/* during normal operation normal value is reduced for optimized power */
	3488	+#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_VAL 0x1F
	3489	+
	3490	+#define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400
	3491	+
	3492	+#define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001
	3493	+#define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020
	3494	+#define PMUCCTL14_43012_DOT11MAC_PHY_CLK_EN_INITVAL 0x00000080
	3495	+#define PMUCCTL14_43012_DOT11MAC_PHY_CNTL_EN_INITVAL 0x00000200
	3496	+#define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400
	3497	+#define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000
	3498	+#define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000
	3499	+#define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000
	3500	+#define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000
	3501	+
	3502	+#define VREG6_43012_MEMLPLDO_ADJ_MASK 0x0000F000
	3503	+#define VREG6_43012_MEMLPLDO_ADJ_SHIFT 12
	3504	+
	3505	+#define VREG6_43012_LPLDO_ADJ_MASK 0x000000F0
	3506	+#define VREG6_43012_LPLDO_ADJ_SHIFT 4
	3507	+
	3508	+#define VREG7_43012_PWRSW_1P8_PU_MASK 0x00400000
	3509	+#define VREG7_43012_PWRSW_1P8_PU_SHIFT 22
	3510	+
	3511	+/* 4347 PMU Chip Control Registers */
	3512	+#define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000
	3513	+#define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_SHIFT 15
	3514	+#define PMUCCTL03_4347_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F
	3515	+
	3516	+#define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000
	3517	+#define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_SHIFT 21
	3518	+#define PMUCCTL03_4347_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F
	3519	+
	3520	+#define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000
	3521	+#define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 27
	3522	+#define PMUCCTL03_4347_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0
	3523	+
	3524	+#define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0
	3525	+#define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 6
	3526	+#define PMUCCTL00_4347_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5
	3527	+
	3528	+#define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000
	3529	+#define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_SHIFT 15
	3530	+#define PMUCCTL00_4347_XTAL_RES_BYPASS_NORMAL_VAL 0x7
3051	3531
3052	3532	/* 4345 Chip specific ChipStatus register bits */
3053	3533	#define CST4345_SPROM_MASK 0x00000020
..	..	@@ -3170,9 +3650,11 @@
3170	3650
3171	3651	#define MUXENAB4350_UART_MASK (0x0000000f)
3172	3652	#define MUXENAB4350_UART_SHIFT 0
3173		-#define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /*< configure GPIO for SDIO host_wake /
	3653	+#define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /*< configure GPIO for host_wake /
3174	3654	#define MUXENAB4350_HOSTWAKE_SHIFT 4
	3655	+#define MUXENAB4349_UART_MASK (0xf)
3175	3656
	3657	+#define CC4350_GPIO_COUNT 16
3176	3658
3177	3659	/* 4350 GCI function sel values */
3178	3660	#define CC4350_FNSEL_HWDEF (0)
..	..	@@ -3191,7 +3673,6 @@
3191	3673	#define CC4350_FNSEL_PUP (14)
3192	3674	#define CC4350_FNSEL_TRISTATE (15)
3193	3675	#define CC4350C_FNSEL_UART (3)
3194		-
3195	3676
3196	3677	/* 4350 GPIO */
3197	3678	#define CC4350_PIN_GPIO_00 (0)
..	..	@@ -3325,6 +3806,37 @@
3325	3806	#define CC6_4345_PMU_EN_MDIO_MASK (1 << 24)
3326	3807	#define CC6_4345_PMU_EN_MDIO_SHIFT (24)
3327	3808
	3809	+/* 4347 GCI function sel values */
	3810	+#define CC4347_FNSEL_HWDEF (0)
	3811	+#define CC4347_FNSEL_SAMEASPIN (1)
	3812	+#define CC4347_FNSEL_GPIO0 (2)
	3813	+#define CC4347_FNSEL_FUART (3)
	3814	+#define CC4347_FNSEL_GCI0 (4)
	3815	+#define CC4347_FNSEL_GCI1 (5)
	3816	+#define CC4347_FNSEL_DBG_UART (6)
	3817	+#define CC4347_FNSEL_SPI (7)
	3818	+#define CC4347_FNSEL_SPROM (8)
	3819	+#define CC4347_FNSEL_MISC0 (9)
	3820	+#define CC4347_FNSEL_MISC1 (10)
	3821	+#define CC4347_FNSEL_MISC2 (11)
	3822	+#define CC4347_FNSEL_IND (12)
	3823	+#define CC4347_FNSEL_PDN (13)
	3824	+#define CC4347_FNSEL_PUP (14)
	3825	+#define CC4347_FNSEL_TRISTATE (15)
	3826	+
	3827	+/* 4347 GPIO */
	3828	+#define CC4347_PIN_GPIO_02 (2)
	3829	+#define CC4347_PIN_GPIO_03 (3)
	3830	+#define CC4347_PIN_GPIO_04 (4)
	3831	+#define CC4347_PIN_GPIO_05 (5)
	3832	+#define CC4347_PIN_GPIO_06 (6)
	3833	+#define CC4347_PIN_GPIO_07 (7)
	3834	+#define CC4347_PIN_GPIO_08 (8)
	3835	+#define CC4347_PIN_GPIO_09 (9)
	3836	+#define CC4347_PIN_GPIO_10 (10)
	3837	+#define CC4347_PIN_GPIO_11 (11)
	3838	+#define CC4347_PIN_GPIO_12 (12)
	3839	+#define CC4347_PIN_GPIO_13 (13)
3328	3840	/* GCI chipcontrol register indices */
3329	3841	#define CC_GCI_CHIPCTRL_00 (0)
3330	3842	#define CC_GCI_CHIPCTRL_01 (1)
..	..	@@ -3335,18 +3847,52 @@
3335	3847	#define CC_GCI_CHIPCTRL_06 (6)
3336	3848	#define CC_GCI_CHIPCTRL_07 (7)
3337	3849	#define CC_GCI_CHIPCTRL_08 (8)
	3850	+#define CC_GCI_CHIPCTRL_09 (9)
	3851	+#define CC_GCI_CHIPCTRL_10 (10)
	3852	+#define CC_GCI_CHIPCTRL_10 (10)
3338	3853	#define CC_GCI_CHIPCTRL_11 (11)
3339	3854	#define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12)
	3855	+
	3856	+#define CC_GCI_04_SDIO_DRVSTR_SHIFT 15
	3857	+#define CC_GCI_04_SDIO_DRVSTR_MASK (0x0f << CC_GCI_04_SDIO_DRVSTR_SHIFT) /* 0x00078000 */
	3858	+#define CC_GCI_04_SDIO_DRVSTR_OVERRIDE_BIT (1 << 18)
	3859	+#define CC_GCI_04_SDIO_DRVSTR_DEFAULT_MA 14
	3860	+#define CC_GCI_04_SDIO_DRVSTR_MIN_MA 2
	3861	+#define CC_GCI_04_SDIO_DRVSTR_MAX_MA 16
3340	3862
3341	3863	#define CC_GCI_06_JTAG_SEL_SHIFT 4
3342	3864	#define CC_GCI_06_JTAG_SEL_MASK (1 << 4)
3343	3865
3344	3866	#define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8)
3345	3867
	3868	+#define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFF << 8)
	3869	+#define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCC << 8)
	3870	+#define GPIO_CTRL_REG_DISABLE_INTERRUPT (3 << 9)
	3871	+#define GPIO_CTRL_REG_COUNT 40
	3872	+
	3873	+/* GCI chipstatus register indices */
	3874	+#define GCI_CHIPSTATUS_00 (0)
	3875	+#define GCI_CHIPSTATUS_01 (1)
	3876	+#define GCI_CHIPSTATUS_02 (2)
	3877	+#define GCI_CHIPSTATUS_03 (3)
	3878	+#define GCI_CHIPSTATUS_04 (4)
	3879	+#define GCI_CHIPSTATUS_05 (5)
	3880	+#define GCI_CHIPSTATUS_06 (6)
	3881	+#define GCI_CHIPSTATUS_07 (7)
	3882	+#define GCI_CHIPSTATUS_08 (8)
	3883	+#define GCI_CHIPSTATUS_09 (9)
	3884	+#define GCI_CHIPSTATUS_10 (10)
	3885	+#define GCI_CHIPSTATUS_11 (11)
	3886	+#define GCI_CHIPSTATUS_12 (12)
	3887	+#define GCI_CHIPSTATUS_13 (13)
	3888	+
	3889	+/* 43021 GCI chipstatus registers */
	3890	+#define GCI43012_CHIPSTATUS_07_BBPLL_LOCK_MASK (1 << 3)
	3891	+
3346	3892	/* 4345 PMU resources */
3347	3893	#define RES4345_LPLDO_PU 0
3348	3894	#define RES4345_PMU_BG_PU 1
3349		-#define RES4345_PMU_SLEEP 2
	3895	+#define RES4345_PMU_SLEEP 2
3350	3896	#define RES4345_HSICLDO_PU 3
3351	3897	#define RES4345_CBUCK_LPOM_PU 4
3352	3898	#define RES4345_CBUCK_PFM_PU 5
..	..	@@ -3375,6 +3921,44 @@
3375	3921	#define RES4345_HT_START 28
3376	3922	#define RES4345_HT_AVAIL 29
3377	3923	#define RES4345_MACPHY_CLK_AVAIL 30
	3924	+
	3925	+/* 43012 pins
	3926	+ * note: only the values set as default/used are added here.
	3927	+ */
	3928	+#define CC43012_PIN_GPIO_00 (0)
	3929	+#define CC43012_PIN_GPIO_01 (1)
	3930	+#define CC43012_PIN_GPIO_02 (2)
	3931	+#define CC43012_PIN_GPIO_03 (3)
	3932	+#define CC43012_PIN_GPIO_04 (4)
	3933	+#define CC43012_PIN_GPIO_05 (5)
	3934	+#define CC43012_PIN_GPIO_06 (6)
	3935	+#define CC43012_PIN_GPIO_07 (7)
	3936	+#define CC43012_PIN_GPIO_08 (8)
	3937	+#define CC43012_PIN_GPIO_09 (9)
	3938	+#define CC43012_PIN_GPIO_10 (10)
	3939	+#define CC43012_PIN_GPIO_11 (11)
	3940	+#define CC43012_PIN_GPIO_12 (12)
	3941	+#define CC43012_PIN_GPIO_13 (13)
	3942	+#define CC43012_PIN_GPIO_14 (14)
	3943	+#define CC43012_PIN_GPIO_15 (15)
	3944	+
	3945	+/* 43012 GCI function sel values */
	3946	+#define CC43012_FNSEL_HWDEF (0)
	3947	+#define CC43012_FNSEL_SAMEASPIN (1)
	3948	+#define CC43012_FNSEL_GPIO0 (2)
	3949	+#define CC43012_FNSEL_GPIO1 (3)
	3950	+#define CC43012_FNSEL_GCI0 (4)
	3951	+#define CC43012_FNSEL_GCI1 (5)
	3952	+#define CC43012_FNSEL_DBG_UART (6)
	3953	+#define CC43012_FNSEL_I2C (7)
	3954	+#define CC43012_FNSEL_BT_SFLASH (8)
	3955	+#define CC43012_FNSEL_MISC0 (9)
	3956	+#define CC43012_FNSEL_MISC1 (10)
	3957	+#define CC43012_FNSEL_MISC2 (11)
	3958	+#define CC43012_FNSEL_IND (12)
	3959	+#define CC43012_FNSEL_PDN (13)
	3960	+#define CC43012_FNSEL_PUP (14)
	3961	+#define CC43012_FNSEL_TRI (15)
3378	3962
3379	3963	/* 4335 pins
3380	3964	* note: only the values set as default/used are added here.
..	..	@@ -3435,6 +4019,7 @@
3435	4019	#define GCI_CORECTRL_SOM_MASK (7 << 4) /*< SECI Op Mode /
3436	4020	#define GCI_CORECTRL_US_MASK (1 << 7) /*< Update SECI /
3437	4021	#define GCI_CORECTRL_BOS_MASK (1 << 8) /*< Break On Sleep /
	4022	+#define GCI_CORECTRL_FORCEREGCLK_MASK (1 << 18) /* ForceRegClk */
3438	4023
3439	4024	/* 4345 pins
3440	4025	* note: only the values set as default/used are added here.
..	..	@@ -3507,6 +4092,28 @@
3507	4092	#define CC4345_GCI_AVS_CTRL_SHIFT (2)
3508	4093	#define CC4345_GCI_AVS_CTRL_ENAB (1 << 5)
3509	4094
	4095	+/* 43430 Pin */
	4096	+#define CC43430_PIN_GPIO_00 (0)
	4097	+#define CC43430_PIN_GPIO_01 (1)
	4098	+#define CC43430_PIN_GPIO_02 (2)
	4099	+#define CC43430_PIN_GPIO_07 (7)
	4100	+#define CC43430_PIN_GPIO_08 (8)
	4101	+#define CC43430_PIN_GPIO_09 (9)
	4102	+#define CC43430_PIN_GPIO_10 (10)
	4103	+
	4104	+#define CC43430_FNSEL_SDIO_INT (2)
	4105	+#define CC43430_FNSEL_6_FAST_UART (6)
	4106	+#define CC43430_FNSEL_10_FAST_UART (10)
	4107	+
	4108	+#define MUXENAB43430_UART_MASK (0x0000000f)
	4109	+#define MUXENAB43430_UART_SHIFT 0
	4110	+#define MUXENAB43430_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */
	4111	+#define MUXENAB43430_HOSTWAKE_SHIFT 4
	4112	+
	4113	+#define CC43430_FNSEL_SAMEASPIN (1)
	4114	+#define CC43430_RFSWCTRL_EN_MASK (0x7f8)
	4115	+#define CC43430_RFSWCTRL_EN_SHIFT (3)
	4116	+
3510	4117	/* GCI GPIO for function sel GCI-0/GCI-1 */
3511	4118	#define CC_GCI_GPIO_0 (0)
3512	4119	#define CC_GCI_GPIO_1 (1)
..	..	@@ -3525,7 +4132,6 @@
3525	4132	#define CC_GCI_GPIO_14 (14)
3526	4133	#define CC_GCI_GPIO_15 (15)
3527	4134
3528		-
3529	4135	/* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */
3530	4136	#define CC_GCI_GPIO_INVALID 0xFF
3531	4137
..	..	@@ -3535,7 +4141,6 @@
3535	4141	#define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos))
3536	4142	/* Extract nibble from a given position */
3537	4143	#define GCIGETNBL(val, pos) ((val >> pos) & 0xF)
3538		-
3539	4144
3540	4145	/* find the 8 bit mask given the bit position */
3541	4146	#define GCIMASK_8B(pos) (((uint32)0xFF) << pos)
..	..	@@ -3551,7 +4156,6 @@
3551	4156	/* Extract nibble from a given position */
3552	4157	#define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF)
3553	4158
3554		-
3555	4159	/* 4335 GCI Intstatus(Mask)/WakeMask Register bits. */
3556	4160	#define GCI_INTSTATUS_RBI (1 << 0) /*< Rx Break Interrupt /
3557	4161	#define GCI_INTSTATUS_UB (1 << 1) /*< UART Break Interrupt /
..	..	@@ -3563,8 +4167,12 @@
3563	4167	#define GCI_INTSTATUS_SRFAF (1 << 12) /*< SECI Rx FIFO Almost Full /
3564	4168	#define GCI_INTSTATUS_SRFNE (1 << 14) /*< SECI Rx FIFO Not Empty /
3565	4169	#define GCI_INTSTATUS_SRFOF (1 << 15) /*< SECI Rx FIFO Not Empty Timeout /
	4170	+#define GCI_INTSTATUS_EVENT (1 << 21) /* GCI Event Interrupt */
	4171	+#define GCI_INTSTATUS_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */
	4172	+#define GCI_INTSTATUS_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */
3566	4173	#define GCI_INTSTATUS_GPIOINT (1 << 25) /*< GCIGpioInt /
3567	4174	#define GCI_INTSTATUS_GPIOWAKE (1 << 26) /*< GCIGpioWake /
	4175	+#define GCI_INTSTATUS_LHLWLWAKE (1 << 30) /* LHL WL wake */
3568	4176
3569	4177	/* 4335 GCI IntMask Register bits. */
3570	4178	#define GCI_INTMASK_RBI (1 << 0) /*< Rx Break Interrupt /
..	..	@@ -3577,8 +4185,12 @@
3577	4185	#define GCI_INTMASK_SRFAF (1 << 12) /*< SECI Rx FIFO Almost Full /
3578	4186	#define GCI_INTMASK_SRFNE (1 << 14) /*< SECI Rx FIFO Not Empty /
3579	4187	#define GCI_INTMASK_SRFOF (1 << 15) /*< SECI Rx FIFO Not Empty Timeout /
	4188	+#define GCI_INTMASK_EVENT (1 << 21) /* GCI Event Interrupt */
	4189	+#define GCI_INTMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */
	4190	+#define GCI_INTMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */
3580	4191	#define GCI_INTMASK_GPIOINT (1 << 25) /*< GCIGpioInt /
3581	4192	#define GCI_INTMASK_GPIOWAKE (1 << 26) /*< GCIGpioWake /
	4193	+#define GCI_INTMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */
3582	4194
3583	4195	/* 4335 GCI WakeMask Register bits. */
3584	4196	#define GCI_WAKEMASK_RBI (1 << 0) /*< Rx Break Interrupt /
..	..	@@ -3591,8 +4203,12 @@
3591	4203	#define GCI_WAKEMASK_SRFAF (1 << 12) /*< SECI Rx FIFO Almost Full /
3592	4204	#define GCI_WAKEMASK_SRFNE (1 << 14) /*< SECI Rx FIFO Not Empty /
3593	4205	#define GCI_WAKEMASK_SRFOF (1 << 15) /*< SECI Rx FIFO Not Empty Timeout /
	4206	+#define GCI_WAKEMASK_EVENT (1 << 21) /* GCI Event Interrupt */
	4207	+#define GCI_WAKEMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */
	4208	+#define GCI_WAKEMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */
3594	4209	#define GCI_WAKEMASK_GPIOINT (1 << 25) /*< GCIGpioInt /
3595	4210	#define GCI_WAKEMASK_GPIOWAKE (1 << 26) /*< GCIGpioWake /
	4211	+#define GCI_WAKEMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */
3596	4212
3597	4213	#define GCI_WAKE_ON_GCI_GPIO1 1
3598	4214	#define GCI_WAKE_ON_GCI_GPIO2 2
..	..	@@ -3603,6 +4219,131 @@
3603	4219	#define GCI_WAKE_ON_GCI_GPIO7 7
3604	4220	#define GCI_WAKE_ON_GCI_GPIO8 8
3605	4221	#define GCI_WAKE_ON_GCI_SECI_IN 9
	4222	+
	4223	+#define PMU_EXT_WAKE_MASK_0_SDIO (1 << 2)
	4224	+
	4225	+/* =========== LHL regs =========== */
	4226	+#define LHL_PWRSEQCTL_SLEEP_EN (1 << 0)
	4227	+#define LHL_PWRSEQCTL_PMU_SLEEP_MODE (1 << 1)
	4228	+#define LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN (1 << 2)
	4229	+#define LHL_PWRSEQCTL_PMU_TOP_ISO_EN (1 << 3)
	4230	+#define LHL_PWRSEQCTL_PMU_TOP_SLB_EN (1 << 4)
	4231	+#define LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN (1 << 5)
	4232	+#define LHL_PWRSEQCTL_PMU_CLDO_PD (1 << 6)
	4233	+#define LHL_PWRSEQCTL_PMU_LPLDO_PD (1 << 7)
	4234	+#define LHL_PWRSEQCTL_PMU_RSRC6_EN (1 << 8)
	4235	+
	4236	+#define PMU_SLEEP_MODE_0 (LHL_PWRSEQCTL_SLEEP_EN \|\
	4237	+ LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN)
	4238	+
	4239	+#define PMU_SLEEP_MODE_1 (LHL_PWRSEQCTL_SLEEP_EN \|\
	4240	+ LHL_PWRSEQCTL_PMU_SLEEP_MODE \|\
	4241	+ LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN \|\
	4242	+ LHL_PWRSEQCTL_PMU_TOP_ISO_EN \|\
	4243	+ LHL_PWRSEQCTL_PMU_TOP_SLB_EN \|\
	4244	+ LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN \|\
	4245	+ LHL_PWRSEQCTL_PMU_CLDO_PD \|\
	4246	+ LHL_PWRSEQCTL_PMU_RSRC6_EN)
	4247	+
	4248	+#define PMU_SLEEP_MODE_2 (LHL_PWRSEQCTL_SLEEP_EN \|\
	4249	+ LHL_PWRSEQCTL_PMU_SLEEP_MODE \|\
	4250	+ LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN \|\
	4251	+ LHL_PWRSEQCTL_PMU_TOP_ISO_EN \|\
	4252	+ LHL_PWRSEQCTL_PMU_TOP_SLB_EN \|\
	4253	+ LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN \|\
	4254	+ LHL_PWRSEQCTL_PMU_CLDO_PD \|\
	4255	+ LHL_PWRSEQCTL_PMU_LPLDO_PD \|\
	4256	+ LHL_PWRSEQCTL_PMU_RSRC6_EN)
	4257	+
	4258	+#define LHL_PWRSEQ_CTL (0x000000ff)
	4259	+
	4260	+/* LHL Top Level Power Up Control Register (lhl_top_pwrup_ctl_adr, Offset 0xE78)
	4261	+* Top Level Counter values for isolation, retention, Power Switch control
	4262	+*/
	4263	+#define LHL_PWRUP_ISOLATION_CNT (0x6 << 8)
	4264	+#define LHL_PWRUP_RETENTION_CNT (0x5 << 16)
	4265	+#define LHL_PWRUP_PWRSW_CNT (0x7 << 24)
	4266	+/* Mask is taken only for isolation 8:13 , Retention 16:21 ,
	4267	+* Power Switch control 24:29
	4268	+*/
	4269	+#define LHL_PWRUP_CTL_MASK (0x3F3F3F00)
	4270	+#define LHL_PWRUP_CTL (LHL_PWRUP_ISOLATION_CNT \|\
	4271	+ LHL_PWRUP_RETENTION_CNT \|\
	4272	+ LHL_PWRUP_PWRSW_CNT)
	4273	+
	4274	+#define LHL_PWRUP_ISOLATION_CNT_4347 (0x7 << 8)
	4275	+#define LHL_PWRUP_RETENTION_CNT_4347 (0x5 << 16)
	4276	+#define LHL_PWRUP_PWRSW_CNT_4347 (0x7 << 24)
	4277	+
	4278	+#define LHL_PWRUP_CTL_4347 (LHL_PWRUP_ISOLATION_CNT_4347 \|\
	4279	+ LHL_PWRUP_RETENTION_CNT_4347 \|\
	4280	+ LHL_PWRUP_PWRSW_CNT_4347)
	4281	+
	4282	+#define LHL_PWRUP2_CLDO_DN_CNT (0x0)
	4283	+#define LHL_PWRUP2_LPLDO_DN_CNT (0x0 << 8)
	4284	+#define LHL_PWRUP2_RSRC6_DN_CN (0x4 << 16)
	4285	+#define LHL_PWRUP2_RSRC7_DN_CN (0x0 << 24)
	4286	+#define LHL_PWRUP2_CTL_MASK (0x3F3F3F3F)
	4287	+#define LHL_PWRUP2_CTL (LHL_PWRUP2_CLDO_DN_CNT \|\
	4288	+ LHL_PWRUP2_LPLDO_DN_CNT \|\
	4289	+ LHL_PWRUP2_RSRC6_DN_CN \|\
	4290	+ LHL_PWRUP2_RSRC7_DN_CN)
	4291	+
	4292	+/* LHL Top Level Power Down Control Register (lhl_top_pwrdn_ctl_adr, Offset 0xE74) */
	4293	+#define LHL_PWRDN_SLEEP_CNT (0x4)
	4294	+#define LHL_PWRDN_CTL_MASK (0x3F)
	4295	+
	4296	+/* LHL Top Level Power Down Control 2 Register (lhl_top_pwrdn2_ctl_adr, Offset 0xE80) */
	4297	+#define LHL_PWRDN2_CLDO_DN_CNT (0x4)
	4298	+#define LHL_PWRDN2_LPLDO_DN_CNT (0x4 << 8)
	4299	+#define LHL_PWRDN2_RSRC6_DN_CN (0x3 << 16)
	4300	+#define LHL_PWRDN2_RSRC7_DN_CN (0x0 << 24)
	4301	+#define LHL_PWRDN2_CTL (LHL_PWRDN2_CLDO_DN_CNT \|\
	4302	+ LHL_PWRDN2_LPLDO_DN_CNT \|\
	4303	+ LHL_PWRDN2_RSRC6_DN_CN \|\
	4304	+ LHL_PWRDN2_RSRC7_DN_CN)
	4305	+#define LHL_PWRDN2_CTL_MASK (0x3F3F3F3F)
	4306	+
	4307	+#define LHL_FAST_WRITE_EN (1 << 14)
	4308	+
	4309	+/* WL ARM Timer0 Interrupt Mask (lhl_wl_armtim0_intrp_adr) */
	4310	+#define LHL_WL_ARMTIM0_INTRP_EN 0x00000001
	4311	+#define LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER 0x00000002
	4312	+
	4313	+/* WL MAC Timer0 Interrupt Mask (lhl_wl_mactim0_intrp_adr) */
	4314	+#define LHL_WL_MACTIM0_INTRP_EN 0x00000001
	4315	+#define LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER 0x00000002
	4316	+
	4317	+/* LHL Wakeup Status (lhl_wkup_status_adr) */
	4318	+#define LHL_WKUP_STATUS_WR_PENDING_ARMTIM0 0x00100000
	4319	+
	4320	+/* WL ARM Timer0 Interrupt Status (lhl_wl_armtim0_st_adr) */
	4321	+#define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001
	4322	+
	4323	+#define LHL_PS_MODE_0 0
	4324	+#define LHL_PS_MODE_1 1
	4325	+
	4326	+/* GCI EventIntMask Register SW bits */
	4327	+#define GCI_MAILBOXDATA_TOWLAN (1 << 0)
	4328	+#define GCI_MAILBOXDATA_TOBT (1 << 1)
	4329	+#define GCI_MAILBOXDATA_TONFC (1 << 2)
	4330	+#define GCI_MAILBOXDATA_TOGPS (1 << 3)
	4331	+#define GCI_MAILBOXDATA_TOLTE (1 << 4)
	4332	+#define GCI_MAILBOXACK_TOWLAN (1 << 8)
	4333	+#define GCI_MAILBOXACK_TOBT (1 << 9)
	4334	+#define GCI_MAILBOXACK_TONFC (1 << 10)
	4335	+#define GCI_MAILBOXACK_TOGPS (1 << 11)
	4336	+#define GCI_MAILBOXACK_TOLTE (1 << 12)
	4337	+#define GCI_WAKE_TOWLAN (1 << 16)
	4338	+#define GCI_WAKE_TOBT (1 << 17)
	4339	+#define GCI_WAKE_TONFC (1 << 18)
	4340	+#define GCI_WAKE_TOGPS (1 << 19)
	4341	+#define GCI_WAKE_TOLTE (1 << 20)
	4342	+#define GCI_SWREADY (1 << 24)
	4343	+
	4344	+/* 4349 Group (4349, 4355, 4359) GCI SECI_OUT TX Status Regiser bits */
	4345	+#define GCI_SECIOUT_TXSTATUS_TXHALT (1 << 0)
	4346	+#define GCI_SECIOUT_TXSTATUS_TI (1 << 16)
3606	4347
3607	4348	/* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic
3608	4349	* for now only UART for bootloader.
..	..	@@ -3615,6 +4356,10 @@
3615	4356	#define MUXENAB4335_GETIX(val, name) \
3616	4357	((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1)
3617	4358
	4359	+/* 43012 MUX options */
	4360	+#define MUXENAB43012_HOSTWAKE_MASK (0x00000001)
	4361	+#define MUXENAB43012_GETIX(val, name) (val - 1)
	4362	+
3618	4363	/*
3619	4364	* Maximum delay for the PMU state transition in us.
3620	4365	* This is an upper bound intended for spinwaits etc.
..	..	@@ -3624,6 +4369,72 @@
3624	4369	/* PMU resource up transition time in ILP cycles */
3625	4370	#define PMURES_UP_TRANSITION 2
3626	4371
	4372	+/* 53573 PMU Resource */
	4373	+#define RES53573_REGULATOR_PU 0
	4374	+#define RES53573_XTALLDO_PU 1
	4375	+#define RES53573_XTAL_PU 2
	4376	+#define RES53573_MINI_PMU 3
	4377	+#define RES53573_RADIO_PU 4
	4378	+#define RES53573_ILP_REQ 5
	4379	+#define RES53573_ALP_AVAIL 6
	4380	+#define RES53573_CPUPLL_LDO_PU 7
	4381	+#define RES53573_CPU_PLL_PU 8
	4382	+#define RES53573_WLAN_BB_PLL_PU 9
	4383	+#define RES53573_MISCPLL_LDO_PU 10
	4384	+#define RES53573_MISCPLL_PU 11
	4385	+#define RES53573_AUDIOPLL_PU 12
	4386	+#define RES53573_PCIEPLL_LDO_PU 13
	4387	+#define RES53573_PCIEPLL_PU 14
	4388	+#define RES53573_DDRPLL_LDO_PU 15
	4389	+#define RES53573_DDRPLL_PU 16
	4390	+#define RES53573_HT_AVAIL 17
	4391	+#define RES53573_MACPHY_CLK_AVAIL 18
	4392	+#define RES53573_OTP_PU 19
	4393	+#define RES53573_RSVD20 20
	4394	+
	4395	+/* 53573 Chip status registers */
	4396	+#define CST53573_LOCK_CPUPLL 0x00000001
	4397	+#define CST53573_LOCK_MISCPLL 0x00000002
	4398	+#define CST53573_LOCK_DDRPLL 0x00000004
	4399	+#define CST53573_LOCK_PCIEPLL 0x00000008
	4400	+#define CST53573_EPHY_ENERGY_DET 0x00001f00
	4401	+#define CST53573_RAW_ENERGY 0x0003e000
	4402	+#define CST53573_BBPLL_LOCKED_O 0x00040000
	4403	+#define CST53573_SERDES_PIPE_PLLLOCK 0x00080000
	4404	+#define CST53573_STRAP_PCIE_EP_MODE 0x00100000
	4405	+#define CST53573_EPHY_PLL_LOCK 0x00200000
	4406	+#define CST53573_AUDIO_PLL_LOCKED_O 0x00400000
	4407	+#define CST53573_PCIE_LINK_IN_L11 0x01000000
	4408	+#define CST53573_PCIE_LINK_IN_L12 0x02000000
	4409	+#define CST53573_DIN_PACKAGEOPTION 0xf0000000
	4410	+
	4411	+/* 53573 Chip control registers macro definitions */
	4412	+#define PMU_53573_CHIPCTL1 1
	4413	+#define PMU_53573_CC1_HT_CLK_REQ_CTRL_MASK 0x00000010
	4414	+#define PMU_53573_CC1_HT_CLK_REQ_CTRL 0x00000010
	4415	+
	4416	+#define PMU_53573_CHIPCTL3 3
	4417	+#define PMU_53573_CC3_ENABLE_CLOSED_LOOP_MASK 0x00000010
	4418	+#define PMU_53573_CC3_ENABLE_CLOSED_LOOP 0x00000000
	4419	+#define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN_MASK 0x00000002
	4420	+#define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN 0x00000002
	4421	+
	4422	+#define CST53573_CHIPMODE_PCIE(cs) FALSE
	4423	+
	4424	+/* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */
	4425	+#define SECI_STAT_BI (1 << 0) /* Break Interrupt */
	4426	+#define SECI_STAT_SPE (1 << 1) /* Parity Error */
	4427	+#define SECI_STAT_SFE (1 << 2) /* Parity Error */
	4428	+#define SECI_STAT_SDU (1 << 3) /* Data Updated */
	4429	+#define SECI_STAT_SADU (1 << 4) /* Auxiliary Data Updated */
	4430	+#define SECI_STAT_SAS (1 << 6) /* AUX State */
	4431	+#define SECI_STAT_SAS2 (1 << 7) /* AUX2 State */
	4432	+#define SECI_STAT_SRITI (1 << 8) /* Idle Timer Interrupt */
	4433	+#define SECI_STAT_STFF (1 << 9) /* Tx FIFO Full */
	4434	+#define SECI_STAT_STFAE (1 << 10) /* Tx FIFO Almost Empty */
	4435	+#define SECI_STAT_SRFE (1 << 11) /* Rx FIFO Empty */
	4436	+#define SECI_STAT_SRFAF (1 << 12) /* Rx FIFO Almost Full */
	4437	+#define SECI_STAT_SFCE (1 << 13) /* Flow Control Event */
3627	4438
3628	4439	/* SECI configuration */
3629	4440	#define SECI_MODE_UART 0x0
..	..	@@ -3640,12 +4451,14 @@
3640	4451	#define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */
3641	4452	#define SECI_UPD_SECI (1 << 7)
3642	4453
	4454	+#define SECI_AUX_TX_START (1 << 31)
3643	4455	#define SECI_SLIP_ESC_CHAR 0xDB
3644	4456	#define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR
3645	4457	#define SECI_SIGNOFF_1 0
3646	4458	#define SECI_REFRESH_REQ 0xDA
3647	4459
3648	4460	/* seci clk_ctl_st bits */
	4461	+#define CLKCTL_STS_HT_AVAIL_REQ (1 << 4)
3649	4462	#define CLKCTL_STS_SECI_CLK_REQ (1 << 8)
3650	4463	#define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24)
3651	4464
..	..	@@ -3730,7 +4543,6 @@
3730	4543	#define LTECX_MUX_MODE_WCI2 0x0
3731	4544	#define LTECX_MUX_MODE_GPIO 0x1
3732	4545
3733		-
3734	4546	/* LTECX GPIO Information Index */
3735	4547	#define LTECX_NVRAM_FSYNC_IDX 0
3736	4548	#define LTECX_NVRAM_LTERX_IDX 1
..	..	@@ -3800,6 +4612,48 @@
3800	4612	#define GCI_GPIO_STS_FAST_EDGE_BIT 3
3801	4613	#define GCI_GPIO_STS_CLEAR 0xF
3802	4614
	4615	+#define GCI_GPIO_STS_EDGE_TRIG_BIT 0
	4616	+#define GCI_GPIO_STS_NEG_EDGE_TRIG_BIT 1
	4617	+#define GCI_GPIO_STS_DUAL_EDGE_TRIG_BIT 2
	4618	+#define GCI_GPIO_STS_WL_DIN_SELECT 6
	4619	+
3803	4620	#define GCI_GPIO_STS_VALUE (1 << GCI_GPIO_STS_VALUE_BIT)
3804	4621
	4622	+/* SR Power Control */
	4623	+#define SRPWR_DMN0_PCIE (0) /* PCIE */
	4624	+#define SRPWR_DMN0_PCIE_SHIFT (SRPWR_DMN0_PCIE) /* PCIE */
	4625	+#define SRPWR_DMN0_PCIE_MASK (1 << SRPWR_DMN0_PCIE_SHIFT) /* PCIE */
	4626	+#define SRPWR_DMN1_ARMBPSD (1) /* ARM/BP/SDIO */
	4627	+#define SRPWR_DMN1_ARMBPSD_SHIFT (SRPWR_DMN1_ARMBPSD) /* ARM/BP/SDIO */
	4628	+#define SRPWR_DMN1_ARMBPSD_MASK (1 << SRPWR_DMN1_ARMBPSD_SHIFT) /* ARM/BP/SDIO */
	4629	+#define SRPWR_DMN2_MACAUX (2) /* MAC/Phy Aux */
	4630	+#define SRPWR_DMN2_MACAUX_SHIFT (SRPWR_DMN2_MACAUX) /* MAC/Phy Aux */
	4631	+#define SRPWR_DMN2_MACAUX_MASK (1 << SRPWR_DMN2_MACAUX_SHIFT) /* MAC/Phy Aux */
	4632	+#define SRPWR_DMN3_MACMAIN (3) /* MAC/Phy Main */
	4633	+#define SRPWR_DMN3_MACMAIN_SHIFT (SRPWR_DMN3_MACMAIN) /* MAC/Phy Main */
	4634	+#define SRPWR_DMN3_MACMAIN_MASK (1 << SRPWR_DMN3_MACMAIN_SHIFT) /* MAC/Phy Main */
	4635	+
	4636	+#define SRPWR_DMN4_MACSCAN (4) /* MAC/Phy Scan */
	4637	+#define SRPWR_DMN4_MACSCAN_SHIFT (SRPWR_DMN4_MACSCAN) /* MAC/Phy Scan */
	4638	+#define SRPWR_DMN4_MACSCAN_MASK (1 << SRPWR_DMN4_MACSCAN_SHIFT) /* MAC/Phy Scan */
	4639	+
	4640	+/* all power domain mask */
	4641	+#define SRPWR_DMN_ALL_MASK(sih) si_srpwr_domain_all_mask(sih)
	4642	+
	4643	+#define SRPWR_REQON_SHIFT (8) /* PowerOnRequest[11:8] */
	4644	+#define SRPWR_REQON_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_REQON_SHIFT)
	4645	+
	4646	+#define SRPWR_STATUS_SHIFT (16) /* ExtPwrStatus[19:16], RO */
	4647	+#define SRPWR_STATUS_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_STATUS_SHIFT)
	4648	+
	4649	+#define SRPWR_DMN_ID_SHIFT (28) /* PowerDomain[31:28], RO */
	4650	+#define SRPWR_DMN_ID_MASK (0xF)
	4651	+
	4652	+/* PMU Precision Usec Timer */
	4653	+#define PMU_PREC_USEC_TIMER_ENABLE 0x1
	4654	+
	4655	+/* FISCtrlStatus */
	4656	+#define PMU_CLEAR_FIS_DONE_SHIFT 1u
	4657	+#define PMU_CLEAR_FIS_DONE_MASK (1u << PMU_CLEAR_FIS_DONE_SHIFT)
	4658	+
3805	4659	#endif /* _SBCHIPC_H */