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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/pcicfg.h
....@@ -1,15 +1,16 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * pcicfg.h: PCI configuration constants and structures.
43  *
5
- * Copyright (C) 1999-2019, Broadcom Corporation
6
- * 
4
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
5
+ *
6
+ * Copyright (C) 1999-2017, Broadcom Corporation
7
+ *
78  *      Unless you and Broadcom execute a separate written software license
89  * agreement governing use of this software, this software is licensed to you
910  * under the terms of the GNU General Public License version 2 (the "GPL"),
1011  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1112  * following added to such license:
12
- * 
13
+ *
1314  *      As a special exception, the copyright holders of this software give you
1415  * permission to link this software with independent modules, and to copy and
1516  * distribute the resulting executable under terms of your choice, provided that
....@@ -17,7 +18,7 @@
1718  * the license of that module.  An independent module is a module which is not
1819  * derived from this software.  The special exception does not apply to any
1920  * modifications of the software.
20
- * 
21
+ *
2122  *      Notwithstanding the above, under no circumstances may you combine this
2223  * software in any way with any other Broadcom software provided under a license
2324  * other than the GPL, without Broadcom's express prior written consent.
....@@ -25,12 +26,11 @@
2526  *
2627  * <<Broadcom-WL-IPTag/Open:>>
2728  *
28
- * $Id: pcicfg.h 514727 2014-11-12 03:02:48Z $
29
+ * $Id: pcicfg.h 690133 2017-03-14 21:02:02Z $
2930  */
3031 
3132 #ifndef	_h_pcicfg_
3233 #define	_h_pcicfg_
33
-
3434 
3535 /* pci config status reg has a bit to indicate that capability ptr is present */
3636 
....@@ -53,6 +53,11 @@
5353 #define	PCI_CFG_HDR		0xe
5454 #define	PCI_CFG_BIST		0xf
5555 #define	PCI_CFG_BAR0		0x10
56
+/*
57
+* TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be
58
+* 0x18 as per the PCIe full dongle spec. Need to modify the values below
59
+* correctly at a later point of time
60
+*/
5661 #define	PCI_CFG_BAR1		0x14
5762 #define	PCI_CFG_BAR2		0x18
5863 #define	PCI_CFG_BAR3		0x1c
....@@ -68,13 +73,14 @@
6873 #define	PCI_CFG_MINGNT		0x3e
6974 #define	PCI_CFG_MAXLAT		0x3f
7075 #define	PCI_CFG_DEVCTRL		0xd8
71
-
76
+#define PCI_CFG_TLCNTRL_5	0x814
7277 
7378 /* PCI CAPABILITY DEFINES */
7479 #define PCI_CAP_POWERMGMTCAP_ID		0x01
7580 #define PCI_CAP_MSICAP_ID		0x05
7681 #define PCI_CAP_VENDSPEC_ID		0x09
7782 #define PCI_CAP_PCIECAP_ID		0x10
83
+#define PCI_CAP_MSIXCAP_ID		0x11
7884 
7985 /* Data structure to define the Message Signalled Interrupt facility
8086  * Valid for PCI and PCIE configurations
....@@ -132,11 +138,13 @@
132138 
133139 /* PCIE Extended configuration */
134140 #define PCIE_ADV_CORR_ERR_MASK	0x114
141
+#define PCIE_ADV_CORR_ERR_MASK_OFFSET	0x14
135142 #define CORR_ERR_RE	(1 << 0) /* Receiver  */
136
-#define CORR_ERR_BT 	(1 << 6) /* Bad TLP  */
143
+#define CORR_ERR_BT	(1 << 6) /* Bad TLP  */
137144 #define CORR_ERR_BD	(1 << 7) /* Bad DLLP */
138145 #define CORR_ERR_RR	(1 << 8) /* REPLAY_NUM rollover */
139146 #define CORR_ERR_RT	(1 << 12) /* Reply timer timeout */
147
+#define CORR_ERR_AE	(1 << 13) /* Adviosry Non-Fital Error Mask */
140148 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
141149 			 CORR_ERR_RR | CORR_ERR_RT)
142150 
....@@ -150,6 +158,9 @@
150158 /* PCIE Root Capability Register bits (Host mode only) */
151159 #define	PCIE_RC_CRS_VISIBILITY		0x0001
152160 
161
+/* PCIe PMCSR Register bits */
162
+#define PCIE_PMCSR_PMESTAT		0x8000
163
+
153164 /* Header to define the PCIE specific capabilities in the extended config space */
154165 typedef struct _pcie_enhanced_caphdr {
155166 	uint16	capID;
....@@ -157,10 +168,11 @@
157168 	uint16	next_ptr : 12;
158169 } pcie_enhanced_caphdr;
159170 
160
-
171
+#define PCIE_CFG_PMCSR		0x4C
161172 #define	PCI_BAR0_WIN		0x80	/* backplane addres space accessed by BAR0 */
162173 #define	PCI_BAR1_WIN		0x84	/* backplane addres space accessed by BAR1 */
163174 #define	PCI_SPROM_CONTROL	0x88	/* sprom property control */
175
+#define	PCIE_CFG_SUBSYSTEM_CONTROL	0x88	/* used as subsystem control in PCIE devices */
164176 #define	PCI_BAR1_CONTROL	0x8c	/* BAR1 region burst control */
165177 #define	PCI_INT_STATUS		0x90	/* PCI and other cores interrupts */
166178 #define	PCI_INT_MASK		0x94	/* mask of PCI and other cores interrupts */
....@@ -170,9 +182,19 @@
170182 #define	PCI_CLK_CTL_ST		0xa8	/* pci config space clock control/status (>=rev14) */
171183 #define	PCI_BAR0_WIN2		0xac	/* backplane addres space accessed by second 4KB of BAR0 */
172184 #define	PCI_GPIO_IN		0xb0	/* pci config space gpio input (>=rev3) */
185
+#define	PCIE_CFG_DEVICE_CAPABILITY	0xb0	/* used as device capability in PCIE devices */
173186 #define	PCI_GPIO_OUT		0xb4	/* pci config space gpio output (>=rev3) */
187
+#define PCIE_CFG_DEVICE_CONTROL 0xb4    /* 0xb4 is used as device control in PCIE devices */
188
+#define PCIE_DC_AER_CORR_EN		(1u << 0u)
189
+#define PCIE_DC_AER_NON_FATAL_EN	(1u << 1u)
190
+#define PCIE_DC_AER_FATAL_EN		(1u << 2u)
191
+#define PCIE_DC_AER_UNSUP_EN		(1u << 3u)
192
+
193
+#define PCI_BAR0_WIN2_OFFSET		0x1000u
194
+#define PCIE2_BAR0_CORE2_WIN2_OFFSET	0x5000u
195
+
174196 #define	PCI_GPIO_OUTEN		0xb8	/* pci config space gpio output enable (>=rev3) */
175
-#define	PCI_L1SS_CTRL2		0x24c	/* The L1 PM Substates Control register */
197
+#define	PCI_PM_L1SS_CTRL2	0x24c	/* The L1 PM Substates Control register */
176198 
177199 /* Private Registers */
178200 #define	PCI_STAT_CTRL		0xa80
....@@ -187,11 +209,90 @@
187209 #define	PCI_L2_EVENTCNT		0xaa4
188210 #define	PCI_L2_STATETMR		0xaa8
189211 
212
+#define	PCI_LINK_STATUS		0x4dc
213
+#define	PCI_LINK_SPEED_MASK	(15u << 0u)
214
+#define	PCI_LINK_SPEED_SHIFT	(0)
215
+#define PCIE_LNK_SPEED_GEN1		0x1
216
+#define PCIE_LNK_SPEED_GEN2		0x2
217
+#define PCIE_LNK_SPEED_GEN3		0x3
218
+
219
+#define	PCI_PL_SPARE	0x1808	/* Config to Increase external clkreq deasserted minimum time */
220
+#define	PCI_CONFIG_EXT_CLK_MIN_TIME_MASK	(1u << 31u)
221
+#define	PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT	(31)
222
+
223
+#define PCI_ADV_ERR_CAP			0x100
224
+#define	PCI_UC_ERR_STATUS		0x104
225
+#define	PCI_UNCORR_ERR_MASK		0x108
226
+#define PCI_UCORR_ERR_SEVR		0x10c
227
+#define	PCI_CORR_ERR_STATUS		0x110
228
+#define	PCI_CORR_ERR_MASK		0x114
229
+#define	PCI_ERR_CAP_CTRL		0x118
230
+#define	PCI_TLP_HDR_LOG1		0x11c
231
+#define	PCI_TLP_HDR_LOG2		0x120
232
+#define	PCI_TLP_HDR_LOG3		0x124
233
+#define	PCI_TLP_HDR_LOG4		0x128
234
+#define	PCI_TL_CTRL_5			0x814
235
+#define	PCI_TL_HDR_FC_ST		0x980
236
+#define	PCI_TL_TGT_CRDT_ST		0x990
237
+#define	PCI_TL_SMLOGIC_ST		0x998
238
+#define	PCI_DL_ATTN_VEC			0x1040
239
+#define	PCI_DL_STATUS			0x1048
240
+
241
+#define	PCI_PHY_CTL_0			0x1800
242
+#define	PCI_SLOW_PMCLK_EXT_RLOCK	(1 << 7)
243
+
244
+#define	PCI_LINK_STATE_DEBUG	0x1c24
245
+#define PCI_RECOVERY_HIST		0x1ce4
246
+#define PCI_PHY_LTSSM_HIST_0	0x1cec
247
+#define PCI_PHY_LTSSM_HIST_1	0x1cf0
248
+#define PCI_PHY_LTSSM_HIST_2	0x1cf4
249
+#define PCI_PHY_LTSSM_HIST_3	0x1cf8
250
+#define PCI_PHY_DBG_CLKREG_0	0x1e10
251
+#define PCI_PHY_DBG_CLKREG_1	0x1e14
252
+#define PCI_PHY_DBG_CLKREG_2	0x1e18
253
+#define PCI_PHY_DBG_CLKREG_3	0x1e1c
254
+
255
+/* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */
256
+#define PCIE_BAR1COHERENTACCEN_BIT	8
257
+#define PCIE_BAR2COHERENTACCEN_BIT	9
258
+#define PCIE_SSRESET_STATUS_BIT		13
259
+#define PCIE_SSRESET_DISABLE_BIT	14
260
+#define PCIE_SSRESET_DIS_ENUM_RST_BIT		15
261
+
262
+#define PCIE_BARCOHERENTACCEN_MASK	0x300
263
+
264
+/* Bit settings for PCI_UC_ERR_STATUS register */
265
+#define PCI_UC_ERR_URES			(1 << 20)	/* Unsupported Request Error Status */
266
+#define PCI_UC_ERR_ECRCS		(1 << 19)	/* ECRC Error Status */
267
+#define PCI_UC_ERR_MTLPS		(1 << 18)	/* Malformed TLP Status */
268
+#define PCI_UC_ERR_ROS			(1 << 17)	/* Receiver Overflow Status */
269
+#define PCI_UC_ERR_UCS			(1 << 16)	/* Unexpected Completion Status */
270
+#define PCI_UC_ERR_CAS			(1 << 15)	/* Completer Abort Status */
271
+#define PCI_UC_ERR_CTS			(1 << 14)	/* Completer Timeout Status */
272
+#define PCI_UC_ERR_FCPES		(1 << 13)	/* Flow Control Protocol Error Status */
273
+#define PCI_UC_ERR_PTLPS		(1 << 12)	/* Poisoned TLP Status */
274
+#define PCI_UC_ERR_DLPES		(1 << 4)	/* Data Link Protocol Error Status */
275
+
276
+#define PCI_DL_STATUS_PHY_LINKUP    (1 << 13) /* Status of LINK */
277
+
190278 #define	PCI_PMCR_REFUP		0x1814	/* Trefup time */
279
+#define PCI_PMCR_TREFUP_LO_MASK		0x3f
280
+#define PCI_PMCR_TREFUP_LO_SHIFT	24
281
+#define PCI_PMCR_TREFUP_LO_BITS		6
282
+#define PCI_PMCR_TREFUP_HI_MASK		0xf
283
+#define PCI_PMCR_TREFUP_HI_SHIFT	5
284
+#define PCI_PMCR_TREFUP_HI_BITS		4
285
+#define PCI_PMCR_TREFUP_MAX			0x400
286
+#define PCI_PMCR_TREFUP_MAX_SCALE	0x2000
287
+
191288 #define	PCI_PMCR_REFUP_EXT	0x1818	/* Trefup extend Max */
289
+#define PCI_PMCR_TREFUP_EXT_SHIFT	22
290
+#define PCI_PMCR_TREFUP_EXT_SCALE	3
291
+#define PCI_PMCR_TREFUP_EXT_ON		1
292
+#define PCI_PMCR_TREFUP_EXT_OFF		0
293
+
192294 #define PCI_TPOWER_SCALE_MASK 0x3
193295 #define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */
194
-
195296 
196297 #define	PCI_BAR0_SHADOW_OFFSET	(2 * 1024)	/* bar0 + 2K accesses sprom shadow (in pci core) */
197298 #define	PCI_BAR0_SPROM_OFFSET	(4 * 1024)	/* bar0 + 4K accesses external sprom */
....@@ -208,6 +309,16 @@
208309 #define PCIE2_BAR0_WIN2		0x70 /* backplane addres space accessed by second 4KB of BAR0 */
209310 #define PCIE2_BAR0_CORE2_WIN	0x74 /* backplane addres space accessed by second 4KB of BAR0 */
210311 #define PCIE2_BAR0_CORE2_WIN2	0x78 /* backplane addres space accessed by second 4KB of BAR0 */
312
+#define PCIE2_BAR0_WINSZ	0x8000
313
+
314
+#define PCI_BAR0_WIN2_OFFSET		0x1000u
315
+#define PCI_CORE_ENUM_OFFSET		0x2000u
316
+#define PCI_CC_CORE_ENUM_OFFSET		0x3000u
317
+#define PCI_SEC_BAR0_WIN_OFFSET		0x4000u
318
+#define PCI_SEC_BAR0_WRAP_OFFSET	0x5000u
319
+#define PCI_CORE_ENUM2_OFFSET		0x6000u
320
+#define PCI_CC_CORE_ENUM2_OFFSET	0x7000u
321
+#define PCI_LAST_OFFSET			0x8000u
211322 
212323 #define PCI_BAR0_WINSZ		(16 * 1024)	/* bar0 window size Match with corerev 13 */
213324 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
....@@ -216,6 +327,37 @@
216327 #define PCI_16KBB0_WINSZ	(16 * 1024)	/* bar0 window size */
217328 #define PCI_SECOND_BAR0_OFFSET	(16 * 1024)	/* secondary  bar 0 window */
218329 
330
+/* On AI chips we have a second window to map DMP regs are mapped: */
331
+#define	PCI_16KB0_WIN2_OFFSET	(4 * 1024)	/* bar0 + 4K is "Window 2" */
332
+
333
+/* PCI_INT_STATUS */
334
+#define	PCI_SBIM_STATUS_SERR	0x4	/* backplane SBErr interrupt status */
335
+
336
+/* PCI_INT_MASK */
337
+#define	PCI_SBIM_SHIFT		8	/* backplane core interrupt mask bits offset */
338
+#define	PCI_SBIM_MASK		0xff00	/* backplane core interrupt mask */
339
+#define	PCI_SBIM_MASK_SERR	0x4	/* backplane SBErr interrupt mask */
340
+#define	PCI_CTO_INT_SHIFT	16	/* backplane SBErr interrupt mask */
341
+#define	PCI_CTO_INT_MASK	(1 << PCI_CTO_INT_SHIFT)	/* backplane SBErr interrupt mask */
342
+
343
+/* PCI_SPROM_CONTROL */
344
+#define SPROM_SZ_MSK		0x02	/* SPROM Size Mask */
345
+#define SPROM_LOCKED		0x08	/* SPROM Locked */
346
+#define	SPROM_BLANK		0x04	/* indicating a blank SPROM */
347
+#define SPROM_WRITEEN		0x10	/* SPROM write enable */
348
+#define SPROM_BOOTROM_WE	0x20	/* external bootrom write enable */
349
+#define SPROM_BACKPLANE_EN	0x40	/* Enable indirect backplane access */
350
+#define SPROM_OTPIN_USE		0x80	/* device OTP In use */
351
+#define SPROM_CFG_TO_SB_RST	0x400	/* backplane reset */
352
+
353
+/* Bits in PCI command and status regs */
354
+#define PCI_CMD_IO		0x00000001	/* I/O enable */
355
+#define PCI_CMD_MEMORY		0x00000002	/* Memory enable */
356
+#define PCI_CMD_MASTER		0x00000004	/* Master enable */
357
+#define PCI_CMD_SPECIAL		0x00000008	/* Special cycles enable */
358
+#define PCI_CMD_INVALIDATE	0x00000010	/* Invalidate? */
359
+#define PCI_CMD_VGA_PAL		0x00000040	/* VGA Palate */
360
+#define PCI_STAT_TA		0x08000000	/* target abort status */
219361 
220362 /* Header types */
221363 #define	PCI_HEADER_MULTI	0x80