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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/bcmsdpcm.h
....@@ -1,16 +1,17 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Broadcom SDIO/PCMCIA
43  * Software-specific definitions shared between device and host side
54  *
6
- * Copyright (C) 1999-2019, Broadcom Corporation
7
- * 
5
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
6
+ *
7
+ * Copyright (C) 1999-2017, Broadcom Corporation
8
+ *
89  *      Unless you and Broadcom execute a separate written software license
910  * agreement governing use of this software, this software is licensed to you
1011  * under the terms of the GNU General Public License version 2 (the "GPL"),
1112  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1213  * following added to such license:
13
- * 
14
+ *
1415  *      As a special exception, the copyright holders of this software give you
1516  * permission to link this software with independent modules, and to copy and
1617  * distribute the resulting executable under terms of your choice, provided that
....@@ -18,7 +19,7 @@
1819  * the license of that module.  An independent module is a module which is not
1920  * derived from this software.  The special exception does not apply to any
2021  * modifications of the software.
21
- * 
22
+ *
2223  *      Notwithstanding the above, under no circumstances may you combine this
2324  * software in any way with any other Broadcom software provided under a license
2425  * other than the GPL, without Broadcom's express prior written consent.
....@@ -26,7 +27,7 @@
2627  *
2728  * <<Broadcom-WL-IPTag/Open:>>
2829  *
29
- * $Id: bcmsdpcm.h 514727 2014-11-12 03:02:48Z $
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+ * $Id$
3031  */
3132 
3233 #ifndef	_bcmsdpcm_h_
....@@ -52,6 +53,16 @@
5253 #define SMB_MASK	0x0000000f	/* To SB Mailbox Mask */
5354 
5455 /* tosbmailboxdata */
56
+
57
+#ifdef DS_PROT
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+/* Bit msgs for custom deep sleep protocol */
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+#define SMB_DATA_D3INFORM	0x100	/* host announcing D3 entry */
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+#define SMB_DATA_DSACK		0x200	/* host acking a deepsleep request */
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+#define SMB_DATA_DSNACK		0x400	/* host nacking a deepsleep request */
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+#endif /* DS_PROT */
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+/* force a trap */
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+#define SMB_DATA_TRAP		0x800	/* host forcing trap */
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+
5566 #define SMB_DATA_VERSION_MASK	0x00ff0000	/* host protocol version (sent with F2 enable) */
5667 #define SMB_DATA_VERSION_SHIFT	16		/* host protocol version (sent with F2 enable) */
5768 
....@@ -60,16 +71,16 @@
6071  */
6172 
6273 /* intstatus bits */
74
+#define I_HMB_INT_ACK	I_HMB_SW0	/* To Host Mailbox Dev Interrupt ACK */
6375 #define I_HMB_FC_STATE	I_HMB_SW0	/* To Host Mailbox Flow Control State */
6476 #define I_HMB_FC_CHANGE	I_HMB_SW1	/* To Host Mailbox Flow Control State Changed */
6577 #define I_HMB_FRAME_IND	I_HMB_SW2	/* To Host Mailbox Frame Indication */
6678 #define I_HMB_HOST_INT	I_HMB_SW3	/* To Host Mailbox Miscellaneous Interrupt */
6779 
68
-#define I_TOHOSTMAIL    (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT)
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+#define I_TOHOSTMAIL    (I_HMB_INT_ACK | I_HMB_FRAME_IND | I_HMB_HOST_INT)
6981 
7082 /* tohostmailbox bits corresponding to intstatus bits */
71
-#define HMB_FC_ON	(1 << 0)	/* To Host Mailbox Flow Control State */
72
-#define HMB_FC_CHANGE	(1 << 1)	/* To Host Mailbox Flow Control State Changed */
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+#define HMB_INT_ACK	(1 << 0)	/* To Host Mailbox Dev Interrupt ACK */
7384 #define HMB_FRAME_IND	(1 << 2)	/* To Host Mailbox Frame Indication */
7485 #define HMB_HOST_INT	(1 << 3)	/* To Host Mailbox Miscellaneous Interrupt */
7586 #define HMB_MASK	0x0000000f	/* To Host Mailbox Mask */
....@@ -80,6 +91,15 @@
8091 #define HMB_DATA_FC		0x04	/* per prio flowcontrol update flag to host */
8192 #define HMB_DATA_FWREADY	0x08	/* firmware is ready for protocol activity */
8293 #define HMB_DATA_FWHALT		0x10	/* firmware has halted operation */
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+
95
+#ifdef DS_PROT
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+/* Bit msgs for custom deep sleep protocol */
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+#define HMB_DATA_DSREQ		0x100	/* firmware requesting deepsleep entry */
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+#define HMB_DATA_DSEXIT		0x200	/* firmware announcing deepsleep exit */
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+#define HMB_DATA_D3ACK		0x400	/* firmware acking a D3 notice from host */
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+#define HMB_DATA_D3EXIT		0x800	/* firmware announcing D3 exit */
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+#define HMB_DATA_DSPROT_MASK	0xf00
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+#endif /* DS_PROT */
83103 
84104 #define HMB_DATA_FCDATA_MASK	0xff000000	/* per prio flowcontrol data */
85105 #define HMB_DATA_FCDATA_SHIFT	24		/* per prio flowcontrol data */
....@@ -114,7 +134,7 @@
114134 
115135 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
116136 #define SDPCM_DOFFSET_OFFSET		3		/* Data Offset */
117
-#define SDPCM_DOFFSET_VALUE(p) 		(((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
137
+#define SDPCM_DOFFSET_VALUE(p)		(((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
118138 #define SDPCM_DOFFSET_MASK		0xff000000
119139 #define SDPCM_DOFFSET_SHIFT		24
120140 
....@@ -265,6 +285,7 @@
265285 #define SDPCM_SHARED_IN_BRPT       0x0800
266286 #define SDPCM_SHARED_SET_BRPT      0x1000
267287 #define SDPCM_SHARED_PENDING_BRPT  0x2000
288
+#define SDPCM_SHARED_FATAL_LOGBUF_VALID	0x100000
268289 
269290 typedef struct {
270291 	uint32	flags;
....@@ -275,8 +296,12 @@
275296 	uint32	console_addr;		/* Address of hnd_cons_t */
276297 	uint32  msgtrace_addr;
277298 	uint32  fwid;
299
+	uint32  device_fatal_logbuf_start;
300
+	uint32	debug_info_addr;	/* Address of debug_info area */
278301 } sdpcm_shared_t;
279302 
280
-extern sdpcm_shared_t sdpcm_shared;
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+/* Device F/W provides the following access function:
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+ * sdpcm_shared_t *hnd_get_sdpcm_shared(void);
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+ */
281306 
282307 #endif	/* _bcmsdpcm_h_ */