add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/bcmpcispi.h
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@@ -1,15 +1,16 @@
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-/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Broadcom PCI-SPI Host Controller Register Definitions
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  *
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- * Copyright (C) 1999-2019, Broadcom Corporation
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- * 
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+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
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+ *
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+ * Copyright (C) 1999-2017, Broadcom Corporation
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+ *
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  *      Unless you and Broadcom execute a separate written software license
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  * agreement governing use of this software, this software is licensed to you
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  * under the terms of the GNU General Public License version 2 (the "GPL"),
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  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
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  * following added to such license:
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- * 
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+ *
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  *      As a special exception, the copyright holders of this software give you
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  * permission to link this software with independent modules, and to copy and
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  * distribute the resulting executable under terms of your choice, provided that
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@@ -17,7 +18,7 @@
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  * the license of that module.  An independent module is a module which is not
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  * derived from this software.  The special exception does not apply to any
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  * modifications of the software.
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- * 
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+ *
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  *      Notwithstanding the above, under no circumstances may you combine this
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  * software in any way with any other Broadcom software provided under a license
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  * other than the GPL, without Broadcom's express prior written consent.
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@@ -36,7 +37,6 @@
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 #define	_XSTR(line)	_PADLINE(line)
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 #define	PAD		_XSTR(__LINE__)
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 #endif	/* PAD */
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-
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 typedef volatile struct {
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 	uint32 spih_ctrl;		/* 0x00 SPI Control Register */
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@@ -147,14 +147,12 @@
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 #define PCI_SYS_ERR_INT_EN	(1 << 4)	/* System Error Interrupt Enable */
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 #define PCI_SOFTWARE_RESET	(1U << 31)	/* Software reset of the PCI Core. */
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-
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 /* PCI Core ISR Register bit definitions */
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 #define PCI_INT_PROP_ST		(1 << 0)	/* Interrupt Propagation Status */
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 #define PCI_WB_ERR_INT_ST	(1 << 1)	/* Wishbone Error Interrupt Status */
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 #define PCI_PCI_ERR_INT_ST	(1 << 2)	/* PCI Error Interrupt Status */
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 #define PCI_PAR_ERR_INT_ST	(1 << 3)	/* Parity Error Interrupt Status */
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 #define PCI_SYS_ERR_INT_ST	(1 << 4)	/* System Error Interrupt Status */
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-
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 /* Registers on the Wishbone bus */
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 #define SPIH_CTLR_INTR		(1 << 0)	/* SPI Host Controller Core Interrupt */