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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/net/wireless/marvell/mwifiex/sdio.c
....@@ -1,10 +1,10 @@
11 /*
2
- * Marvell Wireless LAN device driver: SDIO specific handling
2
+ * NXP Wireless LAN device driver: SDIO specific handling
33  *
4
- * Copyright (C) 2011-2014, Marvell International Ltd.
4
+ * Copyright 2011-2020 NXP
55  *
6
- * This software file (the "File") is distributed by Marvell International
7
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
6
+ * This software file (the "File") is distributed by NXP
7
+ * under the terms of the GNU General Public License Version 2, June 1991
88  * (the "License").  You may use, redistribute and/or modify this File in
99  * accordance with the terms and conditions of the License, a copy of which
1010  * is available by writing to the Free Software Foundation, Inc.,
....@@ -34,6 +34,433 @@
3434 static void mwifiex_sdio_work(struct work_struct *work);
3535 
3636 static struct mwifiex_if_ops sdio_ops;
37
+
38
+static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
39
+	.start_rd_port = 1,
40
+	.start_wr_port = 1,
41
+	.base_0_reg = 0x0040,
42
+	.base_1_reg = 0x0041,
43
+	.poll_reg = 0x30,
44
+	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
45
+	.host_int_rsr_reg = 0x1,
46
+	.host_int_mask_reg = 0x02,
47
+	.host_int_status_reg = 0x03,
48
+	.status_reg_0 = 0x60,
49
+	.status_reg_1 = 0x61,
50
+	.sdio_int_mask = 0x3f,
51
+	.data_port_mask = 0x0000fffe,
52
+	.io_port_0_reg = 0x78,
53
+	.io_port_1_reg = 0x79,
54
+	.io_port_2_reg = 0x7A,
55
+	.max_mp_regs = 64,
56
+	.rd_bitmap_l = 0x04,
57
+	.rd_bitmap_u = 0x05,
58
+	.wr_bitmap_l = 0x06,
59
+	.wr_bitmap_u = 0x07,
60
+	.rd_len_p0_l = 0x08,
61
+	.rd_len_p0_u = 0x09,
62
+	.card_misc_cfg_reg = 0x6c,
63
+	.func1_dump_reg_start = 0x0,
64
+	.func1_dump_reg_end = 0x9,
65
+	.func1_scratch_reg = 0x60,
66
+	.func1_spec_reg_num = 5,
67
+	.func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
68
+};
69
+
70
+static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
71
+	.start_rd_port = 0,
72
+	.start_wr_port = 0,
73
+	.base_0_reg = 0x60,
74
+	.base_1_reg = 0x61,
75
+	.poll_reg = 0x50,
76
+	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
77
+			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
78
+	.host_int_rsr_reg = 0x1,
79
+	.host_int_status_reg = 0x03,
80
+	.host_int_mask_reg = 0x02,
81
+	.status_reg_0 = 0xc0,
82
+	.status_reg_1 = 0xc1,
83
+	.sdio_int_mask = 0xff,
84
+	.data_port_mask = 0xffffffff,
85
+	.io_port_0_reg = 0xD8,
86
+	.io_port_1_reg = 0xD9,
87
+	.io_port_2_reg = 0xDA,
88
+	.max_mp_regs = 184,
89
+	.rd_bitmap_l = 0x04,
90
+	.rd_bitmap_u = 0x05,
91
+	.rd_bitmap_1l = 0x06,
92
+	.rd_bitmap_1u = 0x07,
93
+	.wr_bitmap_l = 0x08,
94
+	.wr_bitmap_u = 0x09,
95
+	.wr_bitmap_1l = 0x0a,
96
+	.wr_bitmap_1u = 0x0b,
97
+	.rd_len_p0_l = 0x0c,
98
+	.rd_len_p0_u = 0x0d,
99
+	.card_misc_cfg_reg = 0xcc,
100
+	.card_cfg_2_1_reg = 0xcd,
101
+	.cmd_rd_len_0 = 0xb4,
102
+	.cmd_rd_len_1 = 0xb5,
103
+	.cmd_rd_len_2 = 0xb6,
104
+	.cmd_rd_len_3 = 0xb7,
105
+	.cmd_cfg_0 = 0xb8,
106
+	.cmd_cfg_1 = 0xb9,
107
+	.cmd_cfg_2 = 0xba,
108
+	.cmd_cfg_3 = 0xbb,
109
+	.fw_dump_host_ready = 0xee,
110
+	.fw_dump_ctrl = 0xe2,
111
+	.fw_dump_start = 0xe3,
112
+	.fw_dump_end = 0xea,
113
+	.func1_dump_reg_start = 0x0,
114
+	.func1_dump_reg_end = 0xb,
115
+	.func1_scratch_reg = 0xc0,
116
+	.func1_spec_reg_num = 8,
117
+	.func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
118
+				 0x59, 0x5c, 0x5d},
119
+};
120
+
121
+static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8977 = {
122
+	.start_rd_port = 0,
123
+	.start_wr_port = 0,
124
+	.base_0_reg = 0xF8,
125
+	.base_1_reg = 0xF9,
126
+	.poll_reg = 0x5C,
127
+	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
128
+		CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
129
+	.host_int_rsr_reg = 0x4,
130
+	.host_int_status_reg = 0x0C,
131
+	.host_int_mask_reg = 0x08,
132
+	.status_reg_0 = 0xE8,
133
+	.status_reg_1 = 0xE9,
134
+	.sdio_int_mask = 0xff,
135
+	.data_port_mask = 0xffffffff,
136
+	.io_port_0_reg = 0xE4,
137
+	.io_port_1_reg = 0xE5,
138
+	.io_port_2_reg = 0xE6,
139
+	.max_mp_regs = 196,
140
+	.rd_bitmap_l = 0x10,
141
+	.rd_bitmap_u = 0x11,
142
+	.rd_bitmap_1l = 0x12,
143
+	.rd_bitmap_1u = 0x13,
144
+	.wr_bitmap_l = 0x14,
145
+	.wr_bitmap_u = 0x15,
146
+	.wr_bitmap_1l = 0x16,
147
+	.wr_bitmap_1u = 0x17,
148
+	.rd_len_p0_l = 0x18,
149
+	.rd_len_p0_u = 0x19,
150
+	.card_misc_cfg_reg = 0xd8,
151
+	.card_cfg_2_1_reg = 0xd9,
152
+	.cmd_rd_len_0 = 0xc0,
153
+	.cmd_rd_len_1 = 0xc1,
154
+	.cmd_rd_len_2 = 0xc2,
155
+	.cmd_rd_len_3 = 0xc3,
156
+	.cmd_cfg_0 = 0xc4,
157
+	.cmd_cfg_1 = 0xc5,
158
+	.cmd_cfg_2 = 0xc6,
159
+	.cmd_cfg_3 = 0xc7,
160
+	.fw_dump_host_ready = 0xcc,
161
+	.fw_dump_ctrl = 0xf0,
162
+	.fw_dump_start = 0xf1,
163
+	.fw_dump_end = 0xf8,
164
+	.func1_dump_reg_start = 0x10,
165
+	.func1_dump_reg_end = 0x17,
166
+	.func1_scratch_reg = 0xe8,
167
+	.func1_spec_reg_num = 13,
168
+	.func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D,
169
+				 0x60, 0x61, 0x62, 0x64,
170
+				 0x65, 0x66, 0x68, 0x69,
171
+				 0x6a},
172
+};
173
+
174
+static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = {
175
+	.start_rd_port = 0,
176
+	.start_wr_port = 0,
177
+	.base_0_reg = 0xF8,
178
+	.base_1_reg = 0xF9,
179
+	.poll_reg = 0x5C,
180
+	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
181
+			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
182
+	.host_int_rsr_reg = 0x4,
183
+	.host_int_status_reg = 0x0C,
184
+	.host_int_mask_reg = 0x08,
185
+	.status_reg_0 = 0xE8,
186
+	.status_reg_1 = 0xE9,
187
+	.sdio_int_mask = 0xff,
188
+	.data_port_mask = 0xffffffff,
189
+	.io_port_0_reg = 0xE4,
190
+	.io_port_1_reg = 0xE5,
191
+	.io_port_2_reg = 0xE6,
192
+	.max_mp_regs = 196,
193
+	.rd_bitmap_l = 0x10,
194
+	.rd_bitmap_u = 0x11,
195
+	.rd_bitmap_1l = 0x12,
196
+	.rd_bitmap_1u = 0x13,
197
+	.wr_bitmap_l = 0x14,
198
+	.wr_bitmap_u = 0x15,
199
+	.wr_bitmap_1l = 0x16,
200
+	.wr_bitmap_1u = 0x17,
201
+	.rd_len_p0_l = 0x18,
202
+	.rd_len_p0_u = 0x19,
203
+	.card_misc_cfg_reg = 0xd8,
204
+	.card_cfg_2_1_reg = 0xd9,
205
+	.cmd_rd_len_0 = 0xc0,
206
+	.cmd_rd_len_1 = 0xc1,
207
+	.cmd_rd_len_2 = 0xc2,
208
+	.cmd_rd_len_3 = 0xc3,
209
+	.cmd_cfg_0 = 0xc4,
210
+	.cmd_cfg_1 = 0xc5,
211
+	.cmd_cfg_2 = 0xc6,
212
+	.cmd_cfg_3 = 0xc7,
213
+	.fw_dump_host_ready = 0xcc,
214
+	.fw_dump_ctrl = 0xf0,
215
+	.fw_dump_start = 0xf1,
216
+	.fw_dump_end = 0xf8,
217
+	.func1_dump_reg_start = 0x10,
218
+	.func1_dump_reg_end = 0x17,
219
+	.func1_scratch_reg = 0xe8,
220
+	.func1_spec_reg_num = 13,
221
+	.func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D,
222
+				 0x60, 0x61, 0x62, 0x64,
223
+				 0x65, 0x66, 0x68, 0x69,
224
+				 0x6a},
225
+};
226
+
227
+static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
228
+	.start_rd_port = 0,
229
+	.start_wr_port = 0,
230
+	.base_0_reg = 0x6C,
231
+	.base_1_reg = 0x6D,
232
+	.poll_reg = 0x5C,
233
+	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
234
+			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
235
+	.host_int_rsr_reg = 0x4,
236
+	.host_int_status_reg = 0x0C,
237
+	.host_int_mask_reg = 0x08,
238
+	.status_reg_0 = 0x90,
239
+	.status_reg_1 = 0x91,
240
+	.sdio_int_mask = 0xff,
241
+	.data_port_mask = 0xffffffff,
242
+	.io_port_0_reg = 0xE4,
243
+	.io_port_1_reg = 0xE5,
244
+	.io_port_2_reg = 0xE6,
245
+	.max_mp_regs = 196,
246
+	.rd_bitmap_l = 0x10,
247
+	.rd_bitmap_u = 0x11,
248
+	.rd_bitmap_1l = 0x12,
249
+	.rd_bitmap_1u = 0x13,
250
+	.wr_bitmap_l = 0x14,
251
+	.wr_bitmap_u = 0x15,
252
+	.wr_bitmap_1l = 0x16,
253
+	.wr_bitmap_1u = 0x17,
254
+	.rd_len_p0_l = 0x18,
255
+	.rd_len_p0_u = 0x19,
256
+	.card_misc_cfg_reg = 0xd8,
257
+	.card_cfg_2_1_reg = 0xd9,
258
+	.cmd_rd_len_0 = 0xc0,
259
+	.cmd_rd_len_1 = 0xc1,
260
+	.cmd_rd_len_2 = 0xc2,
261
+	.cmd_rd_len_3 = 0xc3,
262
+	.cmd_cfg_0 = 0xc4,
263
+	.cmd_cfg_1 = 0xc5,
264
+	.cmd_cfg_2 = 0xc6,
265
+	.cmd_cfg_3 = 0xc7,
266
+	.func1_dump_reg_start = 0x10,
267
+	.func1_dump_reg_end = 0x17,
268
+	.func1_scratch_reg = 0x90,
269
+	.func1_spec_reg_num = 13,
270
+	.func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
271
+				 0x61, 0x62, 0x64, 0x65, 0x66,
272
+				 0x68, 0x69, 0x6a},
273
+};
274
+
275
+static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8987 = {
276
+	.start_rd_port = 0,
277
+	.start_wr_port = 0,
278
+	.base_0_reg = 0xF8,
279
+	.base_1_reg = 0xF9,
280
+	.poll_reg = 0x5C,
281
+	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
282
+			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
283
+	.host_int_rsr_reg = 0x4,
284
+	.host_int_status_reg = 0x0C,
285
+	.host_int_mask_reg = 0x08,
286
+	.status_reg_0 = 0xE8,
287
+	.status_reg_1 = 0xE9,
288
+	.sdio_int_mask = 0xff,
289
+	.data_port_mask = 0xffffffff,
290
+	.io_port_0_reg = 0xE4,
291
+	.io_port_1_reg = 0xE5,
292
+	.io_port_2_reg = 0xE6,
293
+	.max_mp_regs = 196,
294
+	.rd_bitmap_l = 0x10,
295
+	.rd_bitmap_u = 0x11,
296
+	.rd_bitmap_1l = 0x12,
297
+	.rd_bitmap_1u = 0x13,
298
+	.wr_bitmap_l = 0x14,
299
+	.wr_bitmap_u = 0x15,
300
+	.wr_bitmap_1l = 0x16,
301
+	.wr_bitmap_1u = 0x17,
302
+	.rd_len_p0_l = 0x18,
303
+	.rd_len_p0_u = 0x19,
304
+	.card_misc_cfg_reg = 0xd8,
305
+	.card_cfg_2_1_reg = 0xd9,
306
+	.cmd_rd_len_0 = 0xc0,
307
+	.cmd_rd_len_1 = 0xc1,
308
+	.cmd_rd_len_2 = 0xc2,
309
+	.cmd_rd_len_3 = 0xc3,
310
+	.cmd_cfg_0 = 0xc4,
311
+	.cmd_cfg_1 = 0xc5,
312
+	.cmd_cfg_2 = 0xc6,
313
+	.cmd_cfg_3 = 0xc7,
314
+	.fw_dump_host_ready = 0xcc,
315
+	.fw_dump_ctrl = 0xf9,
316
+	.fw_dump_start = 0xf1,
317
+	.fw_dump_end = 0xf8,
318
+	.func1_dump_reg_start = 0x10,
319
+	.func1_dump_reg_end = 0x17,
320
+	.func1_scratch_reg = 0xE8,
321
+	.func1_spec_reg_num = 13,
322
+	.func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
323
+				 0x61, 0x62, 0x64, 0x65, 0x66,
324
+				 0x68, 0x69, 0x6a},
325
+};
326
+
327
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
328
+	.firmware = SD8786_DEFAULT_FW_NAME,
329
+	.reg = &mwifiex_reg_sd87xx,
330
+	.max_ports = 16,
331
+	.mp_agg_pkt_limit = 8,
332
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
333
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
334
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
335
+	.supports_sdio_new_mode = false,
336
+	.has_control_mask = true,
337
+	.can_dump_fw = false,
338
+	.can_auto_tdls = false,
339
+	.can_ext_scan = false,
340
+};
341
+
342
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
343
+	.firmware = SD8787_DEFAULT_FW_NAME,
344
+	.reg = &mwifiex_reg_sd87xx,
345
+	.max_ports = 16,
346
+	.mp_agg_pkt_limit = 8,
347
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
348
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
349
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
350
+	.supports_sdio_new_mode = false,
351
+	.has_control_mask = true,
352
+	.can_dump_fw = false,
353
+	.can_auto_tdls = false,
354
+	.can_ext_scan = true,
355
+};
356
+
357
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
358
+	.firmware = SD8797_DEFAULT_FW_NAME,
359
+	.reg = &mwifiex_reg_sd87xx,
360
+	.max_ports = 16,
361
+	.mp_agg_pkt_limit = 8,
362
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
363
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
364
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
365
+	.supports_sdio_new_mode = false,
366
+	.has_control_mask = true,
367
+	.can_dump_fw = false,
368
+	.can_auto_tdls = false,
369
+	.can_ext_scan = true,
370
+};
371
+
372
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
373
+	.firmware = SD8897_DEFAULT_FW_NAME,
374
+	.reg = &mwifiex_reg_sd8897,
375
+	.max_ports = 32,
376
+	.mp_agg_pkt_limit = 16,
377
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
378
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
379
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
380
+	.supports_sdio_new_mode = true,
381
+	.has_control_mask = false,
382
+	.can_dump_fw = true,
383
+	.can_auto_tdls = false,
384
+	.can_ext_scan = true,
385
+};
386
+
387
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8977 = {
388
+	.firmware = SD8977_DEFAULT_FW_NAME,
389
+	.reg = &mwifiex_reg_sd8977,
390
+	.max_ports = 32,
391
+	.mp_agg_pkt_limit = 16,
392
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
393
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
394
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
395
+	.supports_sdio_new_mode = true,
396
+	.has_control_mask = false,
397
+	.can_dump_fw = true,
398
+	.fw_dump_enh = true,
399
+	.can_auto_tdls = false,
400
+	.can_ext_scan = true,
401
+};
402
+
403
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = {
404
+	.firmware = SD8997_DEFAULT_FW_NAME,
405
+	.reg = &mwifiex_reg_sd8997,
406
+	.max_ports = 32,
407
+	.mp_agg_pkt_limit = 16,
408
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
409
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
410
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
411
+	.supports_sdio_new_mode = true,
412
+	.has_control_mask = false,
413
+	.can_dump_fw = true,
414
+	.fw_dump_enh = true,
415
+	.can_auto_tdls = false,
416
+	.can_ext_scan = true,
417
+};
418
+
419
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
420
+	.firmware = SD8887_DEFAULT_FW_NAME,
421
+	.reg = &mwifiex_reg_sd8887,
422
+	.max_ports = 32,
423
+	.mp_agg_pkt_limit = 16,
424
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
425
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
426
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
427
+	.supports_sdio_new_mode = true,
428
+	.has_control_mask = false,
429
+	.can_dump_fw = false,
430
+	.can_auto_tdls = true,
431
+	.can_ext_scan = true,
432
+};
433
+
434
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8987 = {
435
+	.firmware = SD8987_DEFAULT_FW_NAME,
436
+	.reg = &mwifiex_reg_sd8987,
437
+	.max_ports = 32,
438
+	.mp_agg_pkt_limit = 16,
439
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
440
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
441
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
442
+	.supports_sdio_new_mode = true,
443
+	.has_control_mask = false,
444
+	.can_dump_fw = true,
445
+	.fw_dump_enh = true,
446
+	.can_auto_tdls = true,
447
+	.can_ext_scan = true,
448
+};
449
+
450
+static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
451
+	.firmware = SD8801_DEFAULT_FW_NAME,
452
+	.reg = &mwifiex_reg_sd87xx,
453
+	.max_ports = 16,
454
+	.mp_agg_pkt_limit = 8,
455
+	.supports_sdio_new_mode = false,
456
+	.has_control_mask = true,
457
+	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
458
+	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
459
+	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
460
+	.can_dump_fw = false,
461
+	.can_auto_tdls = false,
462
+	.can_ext_scan = true,
463
+};
37464 
38465 static struct memory_type_mapping generic_mem_type_map[] = {
39466 	{"DUMP", NULL, 0, 0xDD},
....@@ -444,6 +871,9 @@
444871 		return 0;
445872 	}
446873 
874
+	if (!adapter->is_up)
875
+		return -EBUSY;
876
+
447877 	mwifiex_enable_wake(adapter);
448878 
449879 	/* Enable the Host Sleep */
....@@ -477,37 +907,25 @@
477907 		schedule_work(&card->work);
478908 }
479909 
480
-/* Device ID for SD8786 */
481
-#define SDIO_DEVICE_ID_MARVELL_8786   (0x9116)
482
-/* Device ID for SD8787 */
483
-#define SDIO_DEVICE_ID_MARVELL_8787   (0x9119)
484
-/* Device ID for SD8797 */
485
-#define SDIO_DEVICE_ID_MARVELL_8797   (0x9129)
486
-/* Device ID for SD8897 */
487
-#define SDIO_DEVICE_ID_MARVELL_8897   (0x912d)
488
-/* Device ID for SD8887 */
489
-#define SDIO_DEVICE_ID_MARVELL_8887   (0x9135)
490
-/* Device ID for SD8801 */
491
-#define SDIO_DEVICE_ID_MARVELL_8801   (0x9139)
492
-/* Device ID for SD8997 */
493
-#define SDIO_DEVICE_ID_MARVELL_8997   (0x9141)
494
-
495
-
496910 /* WLAN IDs */
497911 static const struct sdio_device_id mwifiex_ids[] = {
498
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8786),
912
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8786_WLAN),
499913 		.driver_data = (unsigned long) &mwifiex_sdio_sd8786},
500
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8787),
914
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8787_WLAN),
501915 		.driver_data = (unsigned long) &mwifiex_sdio_sd8787},
502
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8797),
916
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8797_WLAN),
503917 		.driver_data = (unsigned long) &mwifiex_sdio_sd8797},
504
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8897),
918
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8897_WLAN),
505919 		.driver_data = (unsigned long) &mwifiex_sdio_sd8897},
506
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8887),
920
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8887_WLAN),
507921 		.driver_data = (unsigned long)&mwifiex_sdio_sd8887},
508
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8801),
922
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8801_WLAN),
509923 		.driver_data = (unsigned long)&mwifiex_sdio_sd8801},
510
-	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8997),
924
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8977_WLAN),
925
+		.driver_data = (unsigned long)&mwifiex_sdio_sd8977},
926
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8987_WLAN),
927
+		.driver_data = (unsigned long)&mwifiex_sdio_sd8987},
928
+	{SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8997_WLAN),
511929 		.driver_data = (unsigned long)&mwifiex_sdio_sd8997},
512930 	{},
513931 };
....@@ -2214,22 +2632,30 @@
22142632 	struct sdio_func *func = card->func;
22152633 	int ret;
22162634 
2635
+	/* Prepare the adapter for the reset. */
22172636 	mwifiex_shutdown_sw(adapter);
2218
-
2219
-	/* power cycle the adapter */
2220
-	sdio_claim_host(func);
2221
-	mmc_hw_reset(func->card->host);
2222
-	sdio_release_host(func);
2223
-
2224
-	/* Previous save_adapter won't be valid after this. We will cancel
2225
-	 * pending work requests.
2226
-	 */
22272637 	clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
22282638 	clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
22292639 
2230
-	ret = mwifiex_reinit_sw(adapter);
2231
-	if (ret)
2232
-		dev_err(&func->dev, "reinit failed: %d\n", ret);
2640
+	/* Run a HW reset of the SDIO interface. */
2641
+	sdio_claim_host(func);
2642
+	ret = mmc_hw_reset(func->card->host);
2643
+	sdio_release_host(func);
2644
+
2645
+	switch (ret) {
2646
+	case 1:
2647
+		dev_dbg(&func->dev, "SDIO HW reset asynchronous\n");
2648
+		complete_all(adapter->fw_done);
2649
+		break;
2650
+	case 0:
2651
+		ret = mwifiex_reinit_sw(adapter);
2652
+		if (ret)
2653
+			dev_err(&func->dev, "reinit failed: %d\n", ret);
2654
+		break;
2655
+	default:
2656
+		dev_err(&func->dev, "SDIO HW reset failed: %d\n", ret);
2657
+		break;
2658
+	}
22332659 }
22342660 
22352661 /* This function read/write firmware */
....@@ -2728,4 +3154,6 @@
27283154 MODULE_FIRMWARE(SD8797_DEFAULT_FW_NAME);
27293155 MODULE_FIRMWARE(SD8897_DEFAULT_FW_NAME);
27303156 MODULE_FIRMWARE(SD8887_DEFAULT_FW_NAME);
3157
+MODULE_FIRMWARE(SD8977_DEFAULT_FW_NAME);
3158
+MODULE_FIRMWARE(SD8987_DEFAULT_FW_NAME);
27313159 MODULE_FIRMWARE(SD8997_DEFAULT_FW_NAME);