add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/net/ethernet/sfc/io.h
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@@ -1,11 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /****************************************************************************
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  * Driver for Solarflare network controllers and boards
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  * Copyright 2005-2006 Fen Systems Ltd.
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  * Copyright 2006-2013 Solarflare Communications Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation, incorporated herein by reference.
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  */
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 #ifndef EFX_IO_H
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@@ -78,6 +75,11 @@
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 #endif
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 #endif
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+static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg)
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+{
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+	return efx->reg_base + reg;
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+}
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+
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 #ifdef EFX_USE_QWORD_IO
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 static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
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 				  unsigned int reg)
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@@ -120,7 +122,6 @@
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 	_efx_writed(efx, value->u32[2], reg + 8);
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 	_efx_writed(efx, value->u32[3], reg + 12);
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 #endif
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-	mmiowb();
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 	spin_unlock_irqrestore(&efx->biu_lock, flags);
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 }
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@@ -142,7 +143,6 @@
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 	__raw_writel((__force u32)value->u32[0], membase + addr);
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 	__raw_writel((__force u32)value->u32[1], membase + addr + 4);
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 #endif
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-	mmiowb();
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 	spin_unlock_irqrestore(&efx->biu_lock, flags);
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 }
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@@ -222,8 +222,11 @@
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 	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
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 }
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-/* default VI stride (step between per-VI registers) is 8K */
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-#define EFX_DEFAULT_VI_STRIDE 0x2000
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+/* default VI stride (step between per-VI registers) is 8K on EF10 and
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+ * 64K on EF100
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+ */
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+#define EFX_DEFAULT_VI_STRIDE		0x2000
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+#define EF100_DEFAULT_VI_STRIDE		0x10000
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 /* Calculate offset to page-mapped register */
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 static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,
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@@ -270,7 +273,9 @@
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 #define efx_writed_page(efx, value, reg, page)				\
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 	_efx_writed_page(efx, value,					\
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 			 reg +						\
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-			 BUILD_BUG_ON_ZERO((reg) != 0x400 &&		\
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+			 BUILD_BUG_ON_ZERO((reg) != 0x180 &&		\
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+					   (reg) != 0x200 &&		\
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+					   (reg) != 0x400 &&		\
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 					   (reg) != 0x420 &&		\
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 					   (reg) != 0x830 &&		\
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 					   (reg) != 0x83c &&		\