add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/net/ethernet/intel/ice/ice_sched.h
..
..
@@ -8,11 +8,41 @@
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 #define ICE_QGRP_LAYER_OFFSET	2
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 #define ICE_VSI_LAYER_OFFSET	4
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+#define ICE_SCHED_INVAL_LAYER_NUM	0xFF
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+/* Burst size is a 12 bits register that is configured while creating the RL
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+ * profile(s). MSB is a granularity bit and tells the granularity type
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+ * 0 - LSB bits are in 64 bytes granularity
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+ * 1 - LSB bits are in 1K bytes granularity
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+ */
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+#define ICE_64_BYTE_GRANULARITY			0
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+#define ICE_KBYTE_GRANULARITY			BIT(11)
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+#define ICE_MIN_BURST_SIZE_ALLOWED		64 /* In Bytes */
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+#define ICE_MAX_BURST_SIZE_ALLOWED \
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+	((BIT(11) - 1) * 1024) /* In Bytes */
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+#define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
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+	((BIT(11) - 1) * 64) /* In Bytes */
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+#define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY	ICE_MAX_BURST_SIZE_ALLOWED
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+
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+#define ICE_RL_PROF_FREQUENCY 446000000
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+#define ICE_RL_PROF_ACCURACY_BYTES 128
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+#define ICE_RL_PROF_MULTIPLIER 10000
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+#define ICE_RL_PROF_TS_MULTIPLIER 32
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+#define ICE_RL_PROF_FRACTION 512
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+
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+/* BW rate limit profile parameters list entry along
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+ * with bandwidth maintained per layer in port info
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+ */
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+struct ice_aqc_rl_profile_info {
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+	struct ice_aqc_rl_profile_elem profile;
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+	struct list_head list_entry;
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+	u32 bw;			/* requested */
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+	u16 prof_id_ref;	/* profile ID to node association ref count */
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+};
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41
 
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 struct ice_sched_agg_vsi_info {
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 	struct list_head list_entry;
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 	DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
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-	u16 vsi_id;
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+	u16 vsi_handle;
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 };
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47
 
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 struct ice_sched_agg_info {
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@@ -24,9 +54,16 @@
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 };
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55
 
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 /* FW AQ command calls */
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+enum ice_status
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+ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
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+			 struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
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+			 u16 *elems_ret, struct ice_sq_cd *cd);
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 enum ice_status ice_sched_init_port(struct ice_port_info *pi);
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 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);
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+void ice_sched_clear_port(struct ice_port_info *pi);
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 void ice_sched_cleanup_all(struct ice_hw *hw);
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+void ice_sched_clear_agg(struct ice_hw *hw);
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+
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 struct ice_sched_node *
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 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
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 enum ice_status
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@@ -35,9 +72,19 @@
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 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
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 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
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 struct ice_sched_node *
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-ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_id, u8 tc,
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+ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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 			   u8 owner);
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 enum ice_status
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-ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_id, u8 tc, u16 maxqs,
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+ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
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 		  u8 owner, bool enable);
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+enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
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+enum ice_status
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+ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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+		 u16 q_handle, enum ice_rl_type rl_type, u32 bw);
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+enum ice_status
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+ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
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+		      u16 q_handle, enum ice_rl_type rl_type);
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+enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
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+enum ice_status
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+ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
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 #endif /* _ICE_SCHED_H_ */