~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,7 +5,7 @@
5	5	#define _ICE_ADMINQ_CMD_H_
6	6
7	7	/* This header file defines the Admin Queue commands, error codes and
8		- * descriptor format. It is shared between Firmware and Software.
	8	+ * descriptor format. It is shared between Firmware and Software.
9	9	*/
10	10
11	11	#define ICE_MAX_VSI 768
..	..	@@ -33,11 +33,22 @@
33	33	u8 api_patch;
34	34	};
35	35
	36	+/* Send driver version (indirect 0x0002) */
	37	+struct ice_aqc_driver_ver {
	38	+ u8 major_ver;
	39	+ u8 minor_ver;
	40	+ u8 build_ver;
	41	+ u8 subbuild_ver;
	42	+ u8 reserved[4];
	43	+ __le32 addr_high;
	44	+ __le32 addr_low;
	45	+};
	46	+
36	47	/* Queue Shutdown (direct 0x0003) */
37	48	struct ice_aqc_q_shutdown {
	49	+ u8 driver_unloading;
38	50	#define ICE_AQC_DRIVER_UNLOADING BIT(0)
39		- __le32 driver_unloading;
40		- u8 reserved[12];
	51	+ u8 reserved[15];
41	52	};
42	53
43	54	/* Request resource ownership (direct 0x0008)
..	..	@@ -62,7 +73,7 @@
62	73	#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
63	74	#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
64	75	#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
65		- /* For SDP: pin id of the SDP */
	76	+ /* For SDP: pin ID of the SDP */
66	77	__le32 res_number;
67	78	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
68	79	__le16 status;
..	..	@@ -87,12 +98,24 @@
87	98	/* Device/Function buffer entry, repeated per reported capability */
88	99	struct ice_aqc_list_caps_elem {
89	100	__le16 cap;
	101	+#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
	102	+#define ICE_AQC_CAPS_SRIOV 0x0012
	103	+#define ICE_AQC_CAPS_VF 0x0013
90	104	#define ICE_AQC_CAPS_VSI 0x0017
	105	+#define ICE_AQC_CAPS_DCB 0x0018
91	106	#define ICE_AQC_CAPS_RSS 0x0040
92	107	#define ICE_AQC_CAPS_RXQS 0x0041
93	108	#define ICE_AQC_CAPS_TXQS 0x0042
94	109	#define ICE_AQC_CAPS_MSIX 0x0043
	110	+#define ICE_AQC_CAPS_FD 0x0045
95	111	#define ICE_AQC_CAPS_MAX_MTU 0x0047
	112	+#define ICE_AQC_CAPS_NVM_VER 0x0048
	113	+#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
	114	+#define ICE_AQC_CAPS_OROM_VER 0x004A
	115	+#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
	116	+#define ICE_AQC_CAPS_NET_VER 0x004C
	117	+#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
	118	+#define ICE_AQC_CAPS_NVM_MGMT 0x0080
96	119
97	120	u8 major_ver;
98	121	u8 minor_ver;
..	..	@@ -117,11 +140,9 @@
117	140	#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
118	141	#define ICE_AQC_MAN_MAC_READ_S 4
119	142	#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
120		- u8 lport_num;
121		- u8 lport_num_valid;
122		-#define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0)
	143	+ u8 rsvd[2];
123	144	u8 num_addr; /* Used in response */
124		- u8 reserved[3];
	145	+ u8 rsvd1[3];
125	146	__le32 addr_high;
126	147	__le32 addr_low;
127	148	};
..	..	@@ -137,18 +158,16 @@
137	158
138	159	/* Manage MAC address, write command - direct (0x0108) */
139	160	struct ice_aqc_manage_mac_write {
140		- u8 port_num;
	161	+ u8 rsvd;
141	162	u8 flags;
142	163	#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
143	164	#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
144	165	#define ICE_AQC_MAN_MAC_WR_S 6
145		-#define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
	166	+#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
146	167	#define ICE_AQC_MAN_MAC_UPDATE_LAA 0
147		-#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
148		- /* High 16 bits of MAC address in big endian order */
149		- __be16 sah;
150		- /* Low 32 bits of MAC address in big endian order */
151		- __be32 sal;
	168	+#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
	169	+ /* byte stream in network order */
	170	+ u8 mac_addr[ETH_ALEN];
152	171	__le32 addr_high;
153	172	__le32 addr_low;
154	173	};
..	..	@@ -203,13 +222,6 @@
203	222	#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
204	223	};
205	224
206		-/* The response buffer is as follows. Note that the length of the
207		- * elements array varies with the length of the command response.
208		- */
209		-struct ice_aqc_get_sw_cfg_resp {
210		- struct ice_aqc_get_sw_cfg_resp_elem elements[1];
211		-};
212		-
213	225	/* These resource type defines are used for all switch resource
214	226	* commands where a resource type is required, such as:
215	227	* Get Resource Allocation command (indirect 0x0204)
..	..	@@ -219,6 +231,21 @@
219	231	*/
220	232	#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
221	233	#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
	234	+#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
	235	+#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
	236	+#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
	237	+#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
	238	+#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
	239	+#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
	240	+#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
	241	+
	242	+#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
	243	+#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
	244	+
	245	+#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
	246	+
	247	+#define ICE_AQC_RES_TYPE_S 0
	248	+#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
222	249
223	250	/* Allocate Resources command (indirect 0x0208)
224	251	* Free Resources command (indirect 0x0209)
..	..	@@ -247,7 +274,7 @@
247	274	#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
248	275	(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
249	276	__le16 num_elems;
250		- struct ice_aqc_res_elem elem[1];
	277	+ struct ice_aqc_res_elem elem[];
251	278	};
252	279
253	280	/* Add VSI (indirect 0x0210)
..	..	@@ -443,6 +470,8 @@
443	470	u8 reserved[24];
444	471	};
445	472
	473	+#define ICE_MAX_NUM_RECIPES 64
	474	+
446	475	/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
447	476	*/
448	477	struct ice_aqc_sw_rules {
..	..	@@ -458,7 +487,7 @@
458	487	};
459	488
460	489	/* Add/Update/Get/Remove lookup Rx/Tx command/response entry
461		- * This structures describes the lookup rules and associated actions. "index"
	490	+ * This structures describes the lookup rules and associated actions. "index"
462	491	* is returned as part of a response to a successful Add command, and can be
463	492	* used to identify the rule for Update/Get/Remove commands.
464	493	*/
..	..	@@ -519,7 +548,7 @@
519	548	#define ICE_SINGLE_ACT_OTHER_ACTS 0x3
520	549	#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
521	550	#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
522		- (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
	551	+ (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
523	552
524	553	/* Bit 17:18 - Defines other actions */
525	554	/* Other action = 0 - Mirror VSI */
..	..	@@ -539,8 +568,8 @@
539	568	* lookup-type
540	569	*/
541	570	__le16 hdr_len;
542		- u8 hdr[1];
543		-} __packed;
	571	+ u8 hdr[];
	572	+};
544	573
545	574	/* Add/Update/Remove large action command/response entry
546	575	* "index" is returned as part of a response to a successful Add command, and
..	..	@@ -549,7 +578,6 @@
549	578	struct ice_sw_rule_lg_act {
550	579	__le16 index; /* Index in large action table */
551	580	__le16 size;
552		- __le32 act[1]; /* array of size for actions */
553	581	/* Max number of large actions */
554	582	#define ICE_MAX_LG_ACT 4
555	583	/* Bit 0:1 - Action type */
..	..	@@ -600,6 +628,7 @@
600	628	#define ICE_LG_ACT_STAT_COUNT 0x7
601	629	#define ICE_LG_ACT_STAT_COUNT_S 3
602	630	#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
	631	+ __le32 act[]; /* array of size for actions */
603	632	};
604	633
605	634	/* Add/Update/Remove VSI list command/response entry
..	..	@@ -609,7 +638,7 @@
609	638	struct ice_sw_rule_vsi_list {
610	639	__le16 index; /* Index of VSI/Prune list */
611	640	__le16 number_vsi;
612		- __le16 vsi[1]; /* Array of number_vsi VSI numbers */
	641	+ __le16 vsi[]; /* Array of number_vsi VSI numbers */
613	642	};
614	643
615	644	/* Query VSI list command/response entry */
..	..	@@ -652,30 +681,15 @@
652	681
653	682	/* Update TSE (indirect 0x0403)
654	683	* Get TSE (indirect 0x0404)
655		- */
656		-struct ice_aqc_get_cfg_elem {
657		- __le16 num_elem_req; /* Used by commands */
658		- __le16 num_elem_resp; /* Used by responses */
659		- __le32 reserved;
660		- __le32 addr_high;
661		- __le32 addr_low;
662		-};
663		-
664		-/* This is the buffer for:
	684	+ * Add TSE (indirect 0x0401)
	685	+ * Delete TSE (indirect 0x040F)
	686	+ * Move TSE (indirect 0x0408)
665	687	* Suspend Nodes (indirect 0x0409)
666	688	* Resume Nodes (indirect 0x040A)
667	689	*/
668		-struct ice_aqc_suspend_resume_elem {
669		- __le32 teid[1];
670		-};
671		-
672		-/* Add TSE (indirect 0x0401)
673		- * Delete TSE (indirect 0x040F)
674		- * Move TSE (indirect 0x0408)
675		- */
676		-struct ice_aqc_add_move_delete_elem {
677		- __le16 num_grps_req;
678		- __le16 num_grps_updated;
	690	+struct ice_aqc_sched_elem_cmd {
	691	+ __le16 num_elem_req; /* Used by commands */
	692	+ __le16 num_elem_resp; /* Used by responses */
679	693	__le32 reserved;
680	694	__le32 addr_high;
681	695	__le32 addr_low;
..	..	@@ -731,7 +745,7 @@
731	745
732	746	struct ice_aqc_add_elem {
733	747	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
734		- struct ice_aqc_txsched_elem_data generic[1];
	748	+ struct ice_aqc_txsched_elem_data generic[];
735	749	};
736	750
737	751	struct ice_aqc_get_topo_elem {
..	..	@@ -742,7 +756,67 @@
742	756
743	757	struct ice_aqc_delete_elem {
744	758	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
745		- __le32 teid[1];
	759	+ __le32 teid[];
	760	+};
	761	+
	762	+/* Query Port ETS (indirect 0x040E)
	763	+ *
	764	+ * This indirect command is used to query port TC node configuration.
	765	+ */
	766	+struct ice_aqc_query_port_ets {
	767	+ __le32 port_teid;
	768	+ __le32 reserved;
	769	+ __le32 addr_high;
	770	+ __le32 addr_low;
	771	+};
	772	+
	773	+struct ice_aqc_port_ets_elem {
	774	+ u8 tc_valid_bits;
	775	+ u8 reserved[3];
	776	+ /* 3 bits for UP per TC 0-7, 4th byte reserved */
	777	+ __le32 up2tc;
	778	+ u8 tc_bw_share[8];
	779	+ __le32 port_eir_prof_id;
	780	+ __le32 port_cir_prof_id;
	781	+ /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
	782	+ __le32 tc_node_prio;
	783	+#define ICE_TC_NODE_PRIO_S 0x4
	784	+ u8 reserved1[4];
	785	+ __le32 tc_node_teid[8]; /* Used for response, reserved in command */
	786	+};
	787	+
	788	+/* Rate limiting profile for
	789	+ * Add RL profile (indirect 0x0410)
	790	+ * Query RL profile (indirect 0x0411)
	791	+ * Remove RL profile (indirect 0x0415)
	792	+ * These indirect commands acts on single or multiple
	793	+ * RL profiles with specified data.
	794	+ */
	795	+struct ice_aqc_rl_profile {
	796	+ __le16 num_profiles;
	797	+ __le16 num_processed; /* Only for response. Reserved in Command. */
	798	+ u8 reserved[4];
	799	+ __le32 addr_high;
	800	+ __le32 addr_low;
	801	+};
	802	+
	803	+struct ice_aqc_rl_profile_elem {
	804	+ u8 level;
	805	+ u8 flags;
	806	+#define ICE_AQC_RL_PROFILE_TYPE_S 0x0
	807	+#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
	808	+#define ICE_AQC_RL_PROFILE_TYPE_CIR 0
	809	+#define ICE_AQC_RL_PROFILE_TYPE_EIR 1
	810	+#define ICE_AQC_RL_PROFILE_TYPE_SRL 2
	811	+/* The following flag is used for Query RL Profile Data */
	812	+#define ICE_AQC_RL_PROFILE_INVAL_S 0x7
	813	+#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
	814	+
	815	+ __le16 profile_id;
	816	+ __le16 max_burst_size;
	817	+ __le16 rl_multiply;
	818	+ __le16 wake_up_calc;
	819	+ __le16 rl_encode;
746	820	};
747	821
748	822	/* Query Scheduler Resource Allocation (indirect 0x0412)
..	..	@@ -771,9 +845,8 @@
771	845	u8 chunk_size;
772	846	__le16 max_device_nodes;
773	847	__le16 max_pf_nodes;
774		- u8 rsvd0[2];
775		- __le16 max_shared_rate_lmtr;
776		- __le16 max_children;
	848	+ u8 rsvd0[4];
	849	+ __le16 max_sibl_grp_sz;
777	850	__le16 max_cir_rl_profiles;
778	851	__le16 max_eir_rl_profiles;
779	852	__le16 max_srl_profiles;
..	..	@@ -797,11 +870,11 @@
797	870	* 01b - Report topology capabilities
798	871	* 10b - Report SW configured
799	872	*/
800		-#define ICE_AQC_REPORT_MODE_S 1
801		-#define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
802		-#define ICE_AQC_REPORT_NVM_CAP 0
803		-#define ICE_AQC_REPORT_TOPO_CAP BIT(1)
804		-#define ICE_AQC_REPORT_SW_CFG BIT(2)
	873	+#define ICE_AQC_REPORT_MODE_S 1
	874	+#define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
	875	+#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
	876	+#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
	877	+#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
805	878	__le32 reserved1;
806	879	__le32 addr_high;
807	880	__le32 addr_low;
..	..	@@ -846,11 +919,46 @@
846	919	#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
847	920	#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
848	921	#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
	922	+#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
	923	+#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
	924	+#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
	925	+#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
	926	+#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
	927	+#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
	928	+#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
	929	+#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
	930	+#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
	931	+#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
	932	+#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
	933	+#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
	934	+#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
	935	+#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
	936	+#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
	937	+#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
	938	+#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
	939	+#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
	940	+#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
	941	+#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
	942	+#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
	943	+#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
	944	+#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
	945	+#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
	946	+#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
	947	+#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
	948	+#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
	949	+#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
849	950	#define ICE_PHY_TYPE_LOW_MAX_INDEX 63
	951	+/* The second set of defines is for phy_type_high. */
	952	+#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
	953	+#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
	954	+#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
	955	+#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
	956	+#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
	957	+#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
850	958
851	959	struct ice_aqc_get_phy_caps_data {
852	960	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
853		- __le64 reserved;
	961	+ __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
854	962	u8 caps;
855	963	#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
856	964	#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
..	..	@@ -858,8 +966,13 @@
858	966	#define ICE_AQC_PHY_EN_LINK BIT(3)
859	967	#define ICE_AQC_PHY_AN_MODE BIT(4)
860	968	#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
861		- u8 low_power_ctrl;
	969	+#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
	970	+#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
	971	+ u8 low_power_ctrl_an;
862	972	#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
	973	+#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
	974	+#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
	975	+#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
863	976	__le16 eee_cap;
864	977	#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
865	978	#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
..	..	@@ -870,6 +983,7 @@
870	983	#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
871	984	__le16 eeer_value;
872	985	u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
	986	+ u8 phy_fw_ver[8];
873	987	u8 link_fec_options;
874	988	#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
875	989	#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
..	..	@@ -878,11 +992,15 @@
878	992	#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
879	993	#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
880	994	#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
	995	+#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
	996	+ u8 module_compliance_enforcement;
	997	+#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
881	998	u8 extended_compliance_code;
882	999	#define ICE_MODULE_TYPE_TOTAL_BYTE 3
883	1000	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
884	1001	#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
885	1002	#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
	1003	+#define ICE_AQC_MOD_TYPE_IDENT 1
886	1004	#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
887	1005	#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
888	1006	#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
..	..	@@ -892,13 +1010,14 @@
892	1010	#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
893	1011	#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
894	1012	u8 qualified_module_count;
	1013	+ u8 rsvd2[7]; /* Bytes 47:41 reserved */
895	1014	#define ICE_AQC_QUAL_MOD_COUNT_MAX 16
896	1015	struct {
897	1016	u8 v_oui[3];
898		- u8 rsvd1;
	1017	+ u8 rsvd3;
899	1018	u8 v_part[16];
900	1019	__le32 v_rev;
901		- __le64 rsvd8;
	1020	+ __le64 rsvd4;
902	1021	} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
903	1022	};
904	1023
..	..	@@ -915,18 +1034,40 @@
915	1034	/* Set PHY config command data structure */
916	1035	struct ice_aqc_set_phy_cfg_data {
917	1036	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
918		- __le64 rsvd0;
	1037	+ __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
919	1038	u8 caps;
920		-#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
921		-#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
922		-#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
923		-#define ICE_AQ_PHY_ENA_LINK BIT(3)
924		-#define ICE_AQ_PHY_ENA_ATOMIC_LINK BIT(5)
925		- u8 low_power_ctrl;
	1039	+#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
	1040	+#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
	1041	+#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
	1042	+#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
	1043	+#define ICE_AQ_PHY_ENA_LINK BIT(3)
	1044	+#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
	1045	+#define ICE_AQ_PHY_ENA_LESM BIT(6)
	1046	+#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
	1047	+ u8 low_power_ctrl_an;
926	1048	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
927	1049	__le16 eeer_value;
928	1050	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
929		- u8 rsvd1;
	1051	+ u8 module_compliance_enforcement;
	1052	+};
	1053	+
	1054	+/* Set MAC Config command data structure (direct 0x0603) */
	1055	+struct ice_aqc_set_mac_cfg {
	1056	+ __le16 max_frame_size;
	1057	+ u8 params;
	1058	+#define ICE_AQ_SET_MAC_PACE_S 3
	1059	+#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
	1060	+#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
	1061	+#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
	1062	+#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
	1063	+ u8 tx_tmr_priority;
	1064	+ __le16 tx_tmr_value;
	1065	+ __le16 fc_refresh_threshold;
	1066	+ u8 drop_opts;
	1067	+#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
	1068	+#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
	1069	+#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
	1070	+ u8 reserved[7];
930	1071	};
931	1072
932	1073	/* Restart AN command data structure (direct 0x0605)
..	..	@@ -963,6 +1104,10 @@
963	1104	#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
964	1105	#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
965	1106	#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
	1107	+#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
	1108	+#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
	1109	+#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
	1110	+#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
966	1111	u8 reserved1;
967	1112	u8 link_info;
968	1113	#define ICE_AQ_LINK_UP BIT(0) /* Link Status */
..	..	@@ -985,7 +1130,7 @@
985	1130	u8 ext_info;
986	1131	#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
987	1132	#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
988		- /* Port TX Suspended */
	1133	+ /* Port Tx Suspended */
989	1134	#define ICE_AQ_LINK_TX_S 2
990	1135	#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
991	1136	#define ICE_AQ_LINK_TX_ACTIVE 0
..	..	@@ -997,6 +1142,7 @@
997	1142	#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
998	1143	#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
999	1144	#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
	1145	+#define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1000	1146	/* Pacing Config */
1001	1147	#define ICE_AQ_CFG_PACING_S 3
1002	1148	#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
..	..	@@ -1013,6 +1159,7 @@
1013	1159	#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1014	1160	#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1015	1161	__le16 link_speed;
	1162	+#define ICE_AQ_LINK_SPEED_M 0x7FF
1016	1163	#define ICE_AQ_LINK_SPEED_10MB BIT(0)
1017	1164	#define ICE_AQ_LINK_SPEED_100MB BIT(1)
1018	1165	#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
..	..	@@ -1022,10 +1169,12 @@
1022	1169	#define ICE_AQ_LINK_SPEED_20GB BIT(6)
1023	1170	#define ICE_AQ_LINK_SPEED_25GB BIT(7)
1024	1171	#define ICE_AQ_LINK_SPEED_40GB BIT(8)
	1172	+#define ICE_AQ_LINK_SPEED_50GB BIT(9)
	1173	+#define ICE_AQ_LINK_SPEED_100GB BIT(10)
1025	1174	#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1026	1175	__le32 reserved3; /* Aligns next field to 8-byte boundary */
1027	1176	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1028		- __le64 reserved4;
	1177	+ __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1029	1178	};
1030	1179
1031	1180	/* Set event mask command (direct 0x0613) */
..	..	@@ -1045,11 +1194,108 @@
1045	1194	u8 reserved1[6];
1046	1195	};
1047	1196
	1197	+/* Set MAC Loopback command (direct 0x0620) */
	1198	+struct ice_aqc_set_mac_lb {
	1199	+ u8 lb_mode;
	1200	+#define ICE_AQ_MAC_LB_EN BIT(0)
	1201	+#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
	1202	+ u8 reserved[15];
	1203	+};
	1204	+
	1205	+struct ice_aqc_link_topo_addr {
	1206	+ u8 lport_num;
	1207	+ u8 lport_num_valid;
	1208	+#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
	1209	+ u8 node_type_ctx;
	1210	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
	1211	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
	1212	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
	1213	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
	1214	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
	1215	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
	1216	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
	1217	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
	1218	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
	1219	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
	1220	+#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
	1221	+#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
	1222	+#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
	1223	+ (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
	1224	+#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
	1225	+#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
	1226	+#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
	1227	+#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
	1228	+#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
	1229	+#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
	1230	+ u8 index;
	1231	+ __le16 handle;
	1232	+#define ICE_AQC_LINK_TOPO_HANDLE_S 0
	1233	+#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
	1234	+/* Used to decode the handle field */
	1235	+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
	1236	+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
	1237	+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
	1238	+#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
	1239	+/* In case of a Mezzanine type */
	1240	+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
	1241	+ (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
	1242	+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
	1243	+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
	1244	+/* In case of a LOM type */
	1245	+#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
	1246	+ (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
	1247	+};
	1248	+
	1249	+/* Get Link Topology Handle (direct, 0x06E0) */
	1250	+struct ice_aqc_get_link_topo {
	1251	+ struct ice_aqc_link_topo_addr addr;
	1252	+ u8 node_part_num;
	1253	+ u8 rsvd[9];
	1254	+};
	1255	+
	1256	+/* Set Port Identification LED (direct, 0x06E9) */
	1257	+struct ice_aqc_set_port_id_led {
	1258	+ u8 lport_num;
	1259	+ u8 lport_num_valid;
	1260	+ u8 ident_mode;
	1261	+#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
	1262	+#define ICE_AQC_PORT_IDENT_LED_ORIG 0
	1263	+ u8 rsvd[13];
	1264	+};
	1265	+
	1266	+/* Read/Write SFF EEPROM command (indirect 0x06EE) */
	1267	+struct ice_aqc_sff_eeprom {
	1268	+ u8 lport_num;
	1269	+ u8 lport_num_valid;
	1270	+#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
	1271	+ __le16 i2c_bus_addr;
	1272	+#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
	1273	+#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
	1274	+#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
	1275	+#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
	1276	+#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
	1277	+#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
	1278	+#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
	1279	+#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
	1280	+#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
	1281	+#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
	1282	+#define ICE_AQC_SFF_IS_WRITE BIT(15)
	1283	+ __le16 i2c_mem_addr;
	1284	+ __le16 eeprom_page;
	1285	+#define ICE_AQC_SFF_EEPROM_BANK_S 0
	1286	+#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
	1287	+#define ICE_AQC_SFF_EEPROM_PAGE_S 8
	1288	+#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
	1289	+ __le32 addr_high;
	1290	+ __le32 addr_low;
	1291	+};
	1292	+
1048	1293	/* NVM Read command (indirect 0x0701)
1049	1294	* NVM Erase commands (direct 0x0702)
1050	1295	* NVM Update commands (indirect 0x0703)
1051	1296	*/
1052	1297	struct ice_aqc_nvm {
	1298	+#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1053	1299	__le16 offset_low;
1054	1300	u8 offset_high;
1055	1301	u8 cmd_flags;
..	..	@@ -1059,13 +1305,254 @@
1059	1305	#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1060	1306	#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1061	1307	#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
	1308	+#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1062	1309	#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
	1310	+#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
	1311	+#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
	1312	+#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
	1313	+#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
	1314	+#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
	1315	+#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1063	1316	#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1064	1317	__le16 module_typeid;
1065	1318	__le16 length;
1066	1319	#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1067	1320	__le32 addr_high;
1068	1321	__le32 addr_low;
	1322	+};
	1323	+
	1324	+#define ICE_AQC_NVM_START_POINT 0
	1325	+
	1326	+/* NVM Checksum Command (direct, 0x0706) */
	1327	+struct ice_aqc_nvm_checksum {
	1328	+ u8 flags;
	1329	+#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
	1330	+#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
	1331	+ u8 rsvd;
	1332	+ __le16 checksum; /* Used only by response */
	1333	+#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
	1334	+ u8 rsvd2[12];
	1335	+};
	1336	+
	1337	+/* The result of netlist NVM read comes in a TLV format. The actual data
	1338	+ * (netlist header) starts from word offset 1 (byte 2). The FW strips
	1339	+ * out the type field from the TLV header so all the netlist fields
	1340	+ * should adjust their offset value by 1 word (2 bytes) in order to map
	1341	+ * their correct location.
	1342	+ */
	1343	+#define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B
	1344	+#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1
	1345	+#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */
	1346	+#define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2
	1347	+#define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */
	1348	+#define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0)
	1349	+#define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5
	1350	+#define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */
	1351	+
	1352	+/* netlist ID block field offsets (word offsets) */
	1353	+#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
	1354	+#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
	1355	+#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
	1356	+#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
	1357	+#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
	1358	+#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
	1359	+#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
	1360	+#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
	1361	+#define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
	1362	+#define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F
	1363	+
	1364	+/* Used for NVM Set Package Data command - 0x070A */
	1365	+struct ice_aqc_nvm_pkg_data {
	1366	+ u8 reserved[3];
	1367	+ u8 cmd_flags;
	1368	+#define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
	1369	+#define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
	1370	+
	1371	+ u32 reserved1;
	1372	+ __le32 addr_high;
	1373	+ __le32 addr_low;
	1374	+};
	1375	+
	1376	+/* Used for Pass Component Table command - 0x070B */
	1377	+struct ice_aqc_nvm_pass_comp_tbl {
	1378	+ u8 component_response; /* Response only */
	1379	+#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
	1380	+#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
	1381	+#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
	1382	+ u8 component_response_code; /* Response only */
	1383	+#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
	1384	+#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
	1385	+#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
	1386	+#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
	1387	+#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
	1388	+#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
	1389	+#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
	1390	+#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
	1391	+#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
	1392	+#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
	1393	+#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
	1394	+ u8 reserved;
	1395	+ u8 transfer_flag;
	1396	+#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
	1397	+#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
	1398	+#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
	1399	+#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
	1400	+ __le32 reserved1;
	1401	+ __le32 addr_high;
	1402	+ __le32 addr_low;
	1403	+};
	1404	+
	1405	+struct ice_aqc_nvm_comp_tbl {
	1406	+ __le16 comp_class;
	1407	+#define NVM_COMP_CLASS_ALL_FW 0x000A
	1408	+
	1409	+ __le16 comp_id;
	1410	+#define NVM_COMP_ID_OROM 0x5
	1411	+#define NVM_COMP_ID_NVM 0x6
	1412	+#define NVM_COMP_ID_NETLIST 0x8
	1413	+
	1414	+ u8 comp_class_idx;
	1415	+#define FWU_COMP_CLASS_IDX_NOT_USE 0x0
	1416	+
	1417	+ __le32 comp_cmp_stamp;
	1418	+ u8 cvs_type;
	1419	+#define NVM_CVS_TYPE_ASCII 0x1
	1420	+
	1421	+ u8 cvs_len;
	1422	+ u8 cvs[]; /* Component Version String */
	1423	+} __packed;
	1424	+
	1425	+/*
	1426	+ * Send to PF command (indirect 0x0801) ID is only used by PF
	1427	+ *
	1428	+ * Send to VF command (indirect 0x0802) ID is only used by PF
	1429	+ *
	1430	+ */
	1431	+struct ice_aqc_pf_vf_msg {
	1432	+ __le32 id;
	1433	+ u32 reserved;
	1434	+ __le32 addr_high;
	1435	+ __le32 addr_low;
	1436	+};
	1437	+
	1438	+/* Get LLDP MIB (indirect 0x0A00)
	1439	+ * Note: This is also used by the LLDP MIB Change Event (0x0A01)
	1440	+ * as the format is the same.
	1441	+ */
	1442	+struct ice_aqc_lldp_get_mib {
	1443	+ u8 type;
	1444	+#define ICE_AQ_LLDP_MIB_TYPE_S 0
	1445	+#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
	1446	+#define ICE_AQ_LLDP_MIB_LOCAL 0
	1447	+#define ICE_AQ_LLDP_MIB_REMOTE 1
	1448	+#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
	1449	+#define ICE_AQ_LLDP_BRID_TYPE_S 2
	1450	+#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
	1451	+#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
	1452	+#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
	1453	+/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
	1454	+#define ICE_AQ_LLDP_TX_S 0x4
	1455	+#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
	1456	+#define ICE_AQ_LLDP_TX_ACTIVE 0
	1457	+#define ICE_AQ_LLDP_TX_SUSPENDED 1
	1458	+#define ICE_AQ_LLDP_TX_FLUSHED 3
	1459	+/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
	1460	+ * and in the LLDP MIB Change Event (0x0A01). They are valid for the
	1461	+ * Get LLDP MIB (0x0A00) response only.
	1462	+ */
	1463	+ u8 reserved1;
	1464	+ __le16 local_len;
	1465	+ __le16 remote_len;
	1466	+ u8 reserved2[2];
	1467	+ __le32 addr_high;
	1468	+ __le32 addr_low;
	1469	+};
	1470	+
	1471	+/* Configure LLDP MIB Change Event (direct 0x0A01) */
	1472	+/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
	1473	+struct ice_aqc_lldp_set_mib_change {
	1474	+ u8 command;
	1475	+#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
	1476	+#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
	1477	+ u8 reserved[15];
	1478	+};
	1479	+
	1480	+/* Stop LLDP (direct 0x0A05) */
	1481	+struct ice_aqc_lldp_stop {
	1482	+ u8 command;
	1483	+#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
	1484	+#define ICE_AQ_LLDP_AGENT_STOP 0x0
	1485	+#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
	1486	+#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
	1487	+ u8 reserved[15];
	1488	+};
	1489	+
	1490	+/* Start LLDP (direct 0x0A06) */
	1491	+struct ice_aqc_lldp_start {
	1492	+ u8 command;
	1493	+#define ICE_AQ_LLDP_AGENT_START BIT(0)
	1494	+#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
	1495	+ u8 reserved[15];
	1496	+};
	1497	+
	1498	+/* Get CEE DCBX Oper Config (0x0A07)
	1499	+ * The command uses the generic descriptor struct and
	1500	+ * returns the struct below as an indirect response.
	1501	+ */
	1502	+struct ice_aqc_get_cee_dcb_cfg_resp {
	1503	+ u8 oper_num_tc;
	1504	+ u8 oper_prio_tc[4];
	1505	+ u8 oper_tc_bw[8];
	1506	+ u8 oper_pfc_en;
	1507	+ __le16 oper_app_prio;
	1508	+#define ICE_AQC_CEE_APP_FCOE_S 0
	1509	+#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
	1510	+#define ICE_AQC_CEE_APP_ISCSI_S 3
	1511	+#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
	1512	+#define ICE_AQC_CEE_APP_FIP_S 8
	1513	+#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
	1514	+ __le32 tlv_status;
	1515	+#define ICE_AQC_CEE_PG_STATUS_S 0
	1516	+#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
	1517	+#define ICE_AQC_CEE_PFC_STATUS_S 3
	1518	+#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
	1519	+#define ICE_AQC_CEE_FCOE_STATUS_S 8
	1520	+#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
	1521	+#define ICE_AQC_CEE_ISCSI_STATUS_S 11
	1522	+#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
	1523	+#define ICE_AQC_CEE_FIP_STATUS_S 16
	1524	+#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
	1525	+ u8 reserved[12];
	1526	+};
	1527	+
	1528	+/* Set Local LLDP MIB (indirect 0x0A08)
	1529	+ * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
	1530	+ */
	1531	+struct ice_aqc_lldp_set_local_mib {
	1532	+ u8 type;
	1533	+#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
	1534	+#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
	1535	+#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
	1536	+#define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
	1537	+#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
	1538	+ u8 reserved0;
	1539	+ __le16 length;
	1540	+ u8 reserved1[4];
	1541	+ __le32 addr_high;
	1542	+ __le32 addr_low;
	1543	+};
	1544	+
	1545	+/* Stop/Start LLDP Agent (direct 0x0A09)
	1546	+ * Used for stopping/starting specific LLDP agent. e.g. DCBX.
	1547	+ * The same structure is used for the response, with the command field
	1548	+ * being used as the status field.
	1549	+ */
	1550	+struct ice_aqc_lldp_stop_start_specific_agent {
	1551	+ u8 command;
	1552	+#define ICE_AQC_START_STOP_AGENT_M BIT(0)
	1553	+#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
	1554	+#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
	1555	+ u8 reserved[15];
1069	1556	};
1070	1557
1071	1558	/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
..	..	@@ -1081,6 +1568,9 @@
1081	1568
1082	1569	#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1083	1570	#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
	1571	+#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
	1572	+ (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
	1573	+ ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1084	1574
1085	1575	struct ice_aqc_get_set_rss_keys {
1086	1576	u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
..	..	@@ -1088,10 +1578,10 @@
1088	1578	};
1089	1579
1090	1580	/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1091		-struct ice_aqc_get_set_rss_lut {
	1581	+struct ice_aqc_get_set_rss_lut {
1092	1582	#define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1093	1583	#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1094		-#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
	1584	+#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1095	1585	__le16 vsi_id;
1096	1586	#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1097	1587	#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
..	..	@@ -1122,7 +1612,7 @@
1122	1612	__le32 addr_low;
1123	1613	};
1124	1614
1125		-/* Add TX LAN Queues (indirect 0x0C30) */
	1615	+/* Add Tx LAN Queues (indirect 0x0C30) */
1126	1616	struct ice_aqc_add_txqs {
1127	1617	u8 num_qgrps;
1128	1618	u8 reserved[3];
..	..	@@ -1131,7 +1621,7 @@
1131	1621	__le32 addr_low;
1132	1622	};
1133	1623
1134		-/* This is the descriptor of each queue entry for the Add TX LAN Queues
	1624	+/* This is the descriptor of each queue entry for the Add Tx LAN Queues
1135	1625	* command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1136	1626	*/
1137	1627	struct ice_aqc_add_txqs_perq {
..	..	@@ -1143,7 +1633,7 @@
1143	1633	struct ice_aqc_txsched_elem info;
1144	1634	};
1145	1635
1146		-/* The format of the command buffer for Add TX LAN Queues (0x0C30)
	1636	+/* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1147	1637	* is an array of the following structs. Please note that the length of
1148	1638	* each struct ice_aqc_add_tx_qgrp is variable due
1149	1639	* to the variable number of queues in each group!
..	..	@@ -1152,10 +1642,10 @@
1152	1642	__le32 parent_teid;
1153	1643	u8 num_txqs;
1154	1644	u8 rsvd[3];
1155		- struct ice_aqc_add_txqs_perq txqs[1];
	1645	+ struct ice_aqc_add_txqs_perq txqs[];
1156	1646	};
1157	1647
1158		-/* Disable TX LAN Queues (indirect 0x0C31) */
	1648	+/* Disable Tx LAN Queues (indirect 0x0C31) */
1159	1649	struct ice_aqc_dis_txqs {
1160	1650	u8 cmd_type;
1161	1651	#define ICE_AQC_Q_DIS_CMD_S 0
..	..	@@ -1177,7 +1667,7 @@
1177	1667	__le32 addr_low;
1178	1668	};
1179	1669
1180		-/* The buffer for Disable TX LAN Queues (indirect 0x0C31)
	1670	+/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1181	1671	* contains the following structures, arrayed one after the
1182	1672	* other.
1183	1673	* Note: Since the q_id is 16 bits wide, if the
..	..	@@ -1190,17 +1680,144 @@
1190	1680	u8 num_qs;
1191	1681	u8 rsvd;
1192	1682	/* The length of the q_id array varies according to num_qs */
1193		- __le16 q_id[1];
1194		- /* This only applies from F8 onward */
1195	1683	#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1196	1684	#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1197	1685	(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1198	1686	#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1199	1687	(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
	1688	+ __le16 q_id[];
	1689	+} __packed;
	1690	+
	1691	+/* Configure Firmware Logging Command (indirect 0xFF09)
	1692	+ * Logging Information Read Response (indirect 0xFF10)
	1693	+ * Note: The 0xFF10 command has no input parameters.
	1694	+ */
	1695	+struct ice_aqc_fw_logging {
	1696	+ u8 log_ctrl;
	1697	+#define ICE_AQC_FW_LOG_AQ_EN BIT(0)
	1698	+#define ICE_AQC_FW_LOG_UART_EN BIT(1)
	1699	+ u8 rsvd0;
	1700	+ u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
	1701	+#define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
	1702	+#define ICE_AQC_FW_LOG_UART_VALID BIT(1)
	1703	+ u8 rsvd1[5];
	1704	+ __le32 addr_high;
	1705	+ __le32 addr_low;
1200	1706	};
1201	1707
1202		-struct ice_aqc_dis_txq {
1203		- struct ice_aqc_dis_txq_item qgrps[1];
	1708	+enum ice_aqc_fw_logging_mod {
	1709	+ ICE_AQC_FW_LOG_ID_GENERAL = 0,
	1710	+ ICE_AQC_FW_LOG_ID_CTRL,
	1711	+ ICE_AQC_FW_LOG_ID_LINK,
	1712	+ ICE_AQC_FW_LOG_ID_LINK_TOPO,
	1713	+ ICE_AQC_FW_LOG_ID_DNL,
	1714	+ ICE_AQC_FW_LOG_ID_I2C,
	1715	+ ICE_AQC_FW_LOG_ID_SDP,
	1716	+ ICE_AQC_FW_LOG_ID_MDIO,
	1717	+ ICE_AQC_FW_LOG_ID_ADMINQ,
	1718	+ ICE_AQC_FW_LOG_ID_HDMA,
	1719	+ ICE_AQC_FW_LOG_ID_LLDP,
	1720	+ ICE_AQC_FW_LOG_ID_DCBX,
	1721	+ ICE_AQC_FW_LOG_ID_DCB,
	1722	+ ICE_AQC_FW_LOG_ID_NETPROXY,
	1723	+ ICE_AQC_FW_LOG_ID_NVM,
	1724	+ ICE_AQC_FW_LOG_ID_AUTH,
	1725	+ ICE_AQC_FW_LOG_ID_VPD,
	1726	+ ICE_AQC_FW_LOG_ID_IOSF,
	1727	+ ICE_AQC_FW_LOG_ID_PARSER,
	1728	+ ICE_AQC_FW_LOG_ID_SW,
	1729	+ ICE_AQC_FW_LOG_ID_SCHEDULER,
	1730	+ ICE_AQC_FW_LOG_ID_TXQ,
	1731	+ ICE_AQC_FW_LOG_ID_RSVD,
	1732	+ ICE_AQC_FW_LOG_ID_POST,
	1733	+ ICE_AQC_FW_LOG_ID_WATCHDOG,
	1734	+ ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
	1735	+ ICE_AQC_FW_LOG_ID_MNG,
	1736	+ ICE_AQC_FW_LOG_ID_MAX,
	1737	+};
	1738	+
	1739	+/* Defines for both above FW logging command/response buffers */
	1740	+#define ICE_AQC_FW_LOG_ID_S 0
	1741	+#define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
	1742	+
	1743	+#define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
	1744	+#define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
	1745	+
	1746	+#define ICE_AQC_FW_LOG_EN_S 12
	1747	+#define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
	1748	+#define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
	1749	+#define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
	1750	+#define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
	1751	+#define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
	1752	+
	1753	+/* Get/Clear FW Log (indirect 0xFF11) */
	1754	+struct ice_aqc_get_clear_fw_log {
	1755	+ u8 flags;
	1756	+#define ICE_AQC_FW_LOG_CLEAR BIT(0)
	1757	+#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
	1758	+ u8 rsvd1[7];
	1759	+ __le32 addr_high;
	1760	+ __le32 addr_low;
	1761	+};
	1762	+
	1763	+/* Download Package (indirect 0x0C40) */
	1764	+/* Also used for Update Package (indirect 0x0C42) */
	1765	+struct ice_aqc_download_pkg {
	1766	+ u8 flags;
	1767	+#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
	1768	+ u8 reserved[3];
	1769	+ __le32 reserved1;
	1770	+ __le32 addr_high;
	1771	+ __le32 addr_low;
	1772	+};
	1773	+
	1774	+struct ice_aqc_download_pkg_resp {
	1775	+ __le32 error_offset;
	1776	+ __le32 error_info;
	1777	+ __le32 addr_high;
	1778	+ __le32 addr_low;
	1779	+};
	1780	+
	1781	+/* Get Package Info List (indirect 0x0C43) */
	1782	+struct ice_aqc_get_pkg_info_list {
	1783	+ __le32 reserved1;
	1784	+ __le32 reserved2;
	1785	+ __le32 addr_high;
	1786	+ __le32 addr_low;
	1787	+};
	1788	+
	1789	+/* Version format for packages */
	1790	+struct ice_pkg_ver {
	1791	+ u8 major;
	1792	+ u8 minor;
	1793	+ u8 update;
	1794	+ u8 draft;
	1795	+};
	1796	+
	1797	+#define ICE_PKG_NAME_SIZE 32
	1798	+#define ICE_SEG_NAME_SIZE 28
	1799	+
	1800	+struct ice_aqc_get_pkg_info {
	1801	+ struct ice_pkg_ver ver;
	1802	+ char name[ICE_SEG_NAME_SIZE];
	1803	+ __le32 track_id;
	1804	+ u8 is_in_nvm;
	1805	+ u8 is_active;
	1806	+ u8 is_active_at_boot;
	1807	+ u8 is_modified;
	1808	+};
	1809	+
	1810	+/* Get Package Info List response buffer format (0x0C43) */
	1811	+struct ice_aqc_get_pkg_info_resp {
	1812	+ __le32 count;
	1813	+ struct ice_aqc_get_pkg_info pkg_info[];
	1814	+};
	1815	+
	1816	+/* Lan Queue Overflow Event (direct, 0x1001) */
	1817	+struct ice_aqc_event_lan_overflow {
	1818	+ __le32 prtdcb_ruptq;
	1819	+ __le32 qtx_ctl;
	1820	+ u8 reserved[8];
1204	1821	};
1205	1822
1206	1823	/**
..	..	@@ -1209,15 +1826,15 @@
1209	1826	* @opcode: AQ command opcode
1210	1827	* @datalen: length in bytes of indirect/external data buffer
1211	1828	* @retval: return value from firmware
1212		- * @cookie_h: opaque data high-half
1213		- * @cookie_l: opaque data low-half
	1829	+ * @cookie_high: opaque data high-half
	1830	+ * @cookie_low: opaque data low-half
1214	1831	* @params: command-specific parameters
1215	1832	*
1216	1833	* Descriptor format for commands the driver posts on the Admin Transmit Queue
1217		- * (ATQ). The firmware writes back onto the command descriptor and returns
1218		- * the result of the command. Asynchronous events that are not an immediate
	1834	+ * (ATQ). The firmware writes back onto the command descriptor and returns
	1835	+ * the result of the command. Asynchronous events that are not an immediate
1219	1836	* result of the command are written to the Admin Receive Queue (ARQ) using
1220		- * the same descriptor format. Descriptors are in little-endian notation with
	1837	+ * the same descriptor format. Descriptors are in little-endian notation with
1221	1838	* 32-bit words.
1222	1839	*/
1223	1840	struct ice_aq_desc {
..	..	@@ -1231,6 +1848,7 @@
1231	1848	u8 raw[16];
1232	1849	struct ice_aqc_generic generic;
1233	1850	struct ice_aqc_get_ver get_ver;
	1851	+ struct ice_aqc_driver_ver driver_ver;
1234	1852	struct ice_aqc_q_shutdown q_shutdown;
1235	1853	struct ice_aqc_req_res res_owner;
1236	1854	struct ice_aqc_manage_mac_read mac_read;
..	..	@@ -1240,21 +1858,42 @@
1240	1858	struct ice_aqc_get_phy_caps get_phy;
1241	1859	struct ice_aqc_set_phy_cfg set_phy;
1242	1860	struct ice_aqc_restart_an restart_an;
	1861	+ struct ice_aqc_sff_eeprom read_write_sff_param;
	1862	+ struct ice_aqc_set_port_id_led set_port_id_led;
1243	1863	struct ice_aqc_get_sw_cfg get_sw_conf;
1244	1864	struct ice_aqc_sw_rules sw_rules;
1245	1865	struct ice_aqc_get_topo get_topo;
1246		- struct ice_aqc_get_cfg_elem get_update_elem;
	1866	+ struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1247	1867	struct ice_aqc_query_txsched_res query_sched_res;
1248		- struct ice_aqc_add_move_delete_elem add_move_delete_elem;
	1868	+ struct ice_aqc_query_port_ets port_ets;
	1869	+ struct ice_aqc_rl_profile rl_profile;
1249	1870	struct ice_aqc_nvm nvm;
	1871	+ struct ice_aqc_nvm_checksum nvm_checksum;
	1872	+ struct ice_aqc_nvm_pkg_data pkg_data;
	1873	+ struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
	1874	+ struct ice_aqc_pf_vf_msg virt;
	1875	+ struct ice_aqc_lldp_get_mib lldp_get_mib;
	1876	+ struct ice_aqc_lldp_set_mib_change lldp_set_event;
	1877	+ struct ice_aqc_lldp_stop lldp_stop;
	1878	+ struct ice_aqc_lldp_start lldp_start;
	1879	+ struct ice_aqc_lldp_set_local_mib lldp_set_mib;
	1880	+ struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
1250	1881	struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1251	1882	struct ice_aqc_get_set_rss_key get_set_rss_key;
1252	1883	struct ice_aqc_add_txqs add_txqs;
1253	1884	struct ice_aqc_dis_txqs dis_txqs;
1254	1885	struct ice_aqc_add_get_update_free_vsi vsi_cmd;
	1886	+ struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
	1887	+ struct ice_aqc_fw_logging fw_logging;
	1888	+ struct ice_aqc_get_clear_fw_log get_clear_fw_log;
	1889	+ struct ice_aqc_download_pkg download_pkg;
	1890	+ struct ice_aqc_set_mac_lb set_mac_lb;
1255	1891	struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
	1892	+ struct ice_aqc_set_mac_cfg set_mac_cfg;
1256	1893	struct ice_aqc_set_event_mask set_event_mask;
1257	1894	struct ice_aqc_get_link_status get_link_status;
	1895	+ struct ice_aqc_event_lan_overflow lan_overflow;
	1896	+ struct ice_aqc_get_link_topo get_link_topo;
1258	1897	} params;
1259	1898	};
1260	1899
..	..	@@ -1275,17 +1914,28 @@
1275	1914
1276	1915	/* error codes */
1277	1916	enum ice_aq_err {
1278		- ICE_AQ_RC_OK = 0, /* success */
	1917	+ ICE_AQ_RC_OK = 0, /* Success */
	1918	+ ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
	1919	+ ICE_AQ_RC_ENOENT = 2, /* No such element */
1279	1920	ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1280	1921	ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1281		- ICE_AQ_RC_EEXIST = 13, /* object already exists */
	1922	+ ICE_AQ_RC_EEXIST = 13, /* Object already exists */
	1923	+ ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
1282	1924	ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
	1925	+ ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
	1926	+ ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
	1927	+ ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
	1928	+ ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
	1929	+ ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
	1930	+ ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
	1931	+ ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1283	1932	};
1284	1933
1285	1934	/* Admin Queue command opcodes */
1286	1935	enum ice_adminq_opc {
1287	1936	/* AQ commands */
1288	1937	ice_aqc_opc_get_ver = 0x0001,
	1938	+ ice_aqc_opc_driver_ver = 0x0002,
1289	1939	ice_aqc_opc_q_shutdown = 0x0003,
1290	1940
1291	1941	/* resource ownership */
..	..	@@ -1325,20 +1975,49 @@
1325	1975	/* transmit scheduler commands */
1326	1976	ice_aqc_opc_get_dflt_topo = 0x0400,
1327	1977	ice_aqc_opc_add_sched_elems = 0x0401,
	1978	+ ice_aqc_opc_cfg_sched_elems = 0x0403,
	1979	+ ice_aqc_opc_get_sched_elems = 0x0404,
1328	1980	ice_aqc_opc_suspend_sched_elems = 0x0409,
1329	1981	ice_aqc_opc_resume_sched_elems = 0x040A,
	1982	+ ice_aqc_opc_query_port_ets = 0x040E,
1330	1983	ice_aqc_opc_delete_sched_elems = 0x040F,
	1984	+ ice_aqc_opc_add_rl_profiles = 0x0410,
1331	1985	ice_aqc_opc_query_sched_res = 0x0412,
	1986	+ ice_aqc_opc_remove_rl_profiles = 0x0415,
1332	1987
1333	1988	/* PHY commands */
1334	1989	ice_aqc_opc_get_phy_caps = 0x0600,
1335	1990	ice_aqc_opc_set_phy_cfg = 0x0601,
	1991	+ ice_aqc_opc_set_mac_cfg = 0x0603,
1336	1992	ice_aqc_opc_restart_an = 0x0605,
1337	1993	ice_aqc_opc_get_link_status = 0x0607,
1338	1994	ice_aqc_opc_set_event_mask = 0x0613,
	1995	+ ice_aqc_opc_set_mac_lb = 0x0620,
	1996	+ ice_aqc_opc_get_link_topo = 0x06E0,
	1997	+ ice_aqc_opc_set_port_id_led = 0x06E9,
	1998	+ ice_aqc_opc_sff_eeprom = 0x06EE,
1339	1999
1340	2000	/* NVM commands */
1341	2001	ice_aqc_opc_nvm_read = 0x0701,
	2002	+ ice_aqc_opc_nvm_erase = 0x0702,
	2003	+ ice_aqc_opc_nvm_write = 0x0703,
	2004	+ ice_aqc_opc_nvm_checksum = 0x0706,
	2005	+ ice_aqc_opc_nvm_write_activate = 0x0707,
	2006	+ ice_aqc_opc_nvm_update_empr = 0x0709,
	2007	+ ice_aqc_opc_nvm_pkg_data = 0x070A,
	2008	+ ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
	2009	+
	2010	+ /* PF/VF mailbox commands */
	2011	+ ice_mbx_opc_send_msg_to_pf = 0x0801,
	2012	+ ice_mbx_opc_send_msg_to_vf = 0x0802,
	2013	+ /* LLDP commands */
	2014	+ ice_aqc_opc_lldp_get_mib = 0x0A00,
	2015	+ ice_aqc_opc_lldp_set_mib_change = 0x0A01,
	2016	+ ice_aqc_opc_lldp_stop = 0x0A05,
	2017	+ ice_aqc_opc_lldp_start = 0x0A06,
	2018	+ ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
	2019	+ ice_aqc_opc_lldp_set_local_mib = 0x0A08,
	2020	+ ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
1342	2021
1343	2022	/* RSS commands */
1344	2023	ice_aqc_opc_set_rss_key = 0x0B02,
..	..	@@ -1346,9 +2025,21 @@
1346	2025	ice_aqc_opc_get_rss_key = 0x0B04,
1347	2026	ice_aqc_opc_get_rss_lut = 0x0B05,
1348	2027
1349		- /* TX queue handling commands/events */
	2028	+ /* Tx queue handling commands/events */
1350	2029	ice_aqc_opc_add_txqs = 0x0C30,
1351	2030	ice_aqc_opc_dis_txqs = 0x0C31,
	2031	+
	2032	+ /* package commands */
	2033	+ ice_aqc_opc_download_pkg = 0x0C40,
	2034	+ ice_aqc_opc_update_pkg = 0x0C42,
	2035	+ ice_aqc_opc_get_pkg_info_list = 0x0C43,
	2036	+
	2037	+ /* Standalone Commands/Events */
	2038	+ ice_aqc_opc_event_lan_overflow = 0x1001,
	2039	+
	2040	+ /* debug commands */
	2041	+ ice_aqc_opc_fw_logging = 0xFF09,
	2042	+ ice_aqc_opc_fw_logging_info = 0xFF10,
1352	2043	};
1353	2044
1354	2045	#endif /* _ICE_ADMINQ_CMD_H_ */