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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h
....@@ -1,16 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Huawei HiNIC PCI Express Linux driver
34  * Copyright(c) 2017 Huawei Technologies Co., Ltd
4
- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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- * for more details.
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- *
145  */
156 
167 #ifndef HINIC_HW_WQE_H
....@@ -62,19 +53,33 @@
6253 			(((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \
6354 			 & HINIC_CMDQ_WQE_HEADER_##member##_MASK)
6455 
65
-#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT    0
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-#define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT        16
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-#define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT         22
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-#define HINIC_SQ_CTRL_LEN_SHIFT                 29
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+#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT           0
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+#define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT               16
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+#define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT                22
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+#define HINIC_SQ_CTRL_LEN_SHIFT                        29
6960 
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-#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK     0xFF
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-#define HINIC_SQ_CTRL_TASKSECT_LEN_MASK         0x1F
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-#define HINIC_SQ_CTRL_DATA_FORMAT_MASK          0x1
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-#define HINIC_SQ_CTRL_LEN_MASK                  0x3
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+#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK            0xFF
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+#define HINIC_SQ_CTRL_TASKSECT_LEN_MASK                0x1F
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+#define HINIC_SQ_CTRL_DATA_FORMAT_MASK                 0x1
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+#define HINIC_SQ_CTRL_LEN_MASK                         0x3
7465 
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-#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT      13
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+#define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT          2
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+#define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT             10
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+#define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT             11
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+#define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT       12
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+#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT             13
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+#define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT            27
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+#define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT              28
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+#define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT             29
7674 
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-#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK       0x3FFF
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+#define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK           0xFF
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+#define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK              0x1
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+#define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK              0x1
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+#define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK	       0x1
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+#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK              0x3FFF
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+#define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK             0x1
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+#define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK               0x1
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+#define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK              0x7
7883 
7984 #define HINIC_SQ_CTRL_SET(val, member)          \
8085 		(((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \
....@@ -83,6 +88,10 @@
8388 #define HINIC_SQ_CTRL_GET(val, member)          \
8489 		(((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \
8590 		 & HINIC_SQ_CTRL_##member##_MASK)
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+
92
+#define HINIC_SQ_CTRL_CLEAR(val, member)	\
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+		((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \
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+		 << HINIC_SQ_CTRL_##member##_SHIFT)))
8695 
8796 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT     0
8897 #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT    8
....@@ -108,28 +117,28 @@
108117 
109118 /* 8 bits reserved */
110119 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT    8
111
-#define HINIC_SQ_TASK_INFO1_INNER_L4_LEN_SHIFT  16
112
-#define HINIC_SQ_TASK_INFO1_INNER_L3_LEN_SHIFT  24
120
+#define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT   16
121
+#define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT   24
113122 
114123 /* 8 bits reserved */
115124 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK     0xFF
116
-#define HINIC_SQ_TASK_INFO1_INNER_L4_LEN_MASK   0xFF
117
-#define HINIC_SQ_TASK_INFO1_INNER_L3_LEN_MASK   0xFF
125
+#define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK    0xFF
126
+#define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK    0xFF
118127 
119128 #define HINIC_SQ_TASK_INFO1_SET(val, member)    \
120129 		(((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) <<  \
121130 		 HINIC_SQ_TASK_INFO1_##member##_SHIFT)
122131 
123
-#define HINIC_SQ_TASK_INFO2_TUNNEL_L4_LEN_SHIFT 0
124
-#define HINIC_SQ_TASK_INFO2_OUTER_L3_LEN_SHIFT  12
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-#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 19
132
+#define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT  0
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+#define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT   8
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+#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16
126135 /* 1 bit reserved */
127
-#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT  22
136
+#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT  24
128137 /* 8 bits reserved */
129138 
130
-#define HINIC_SQ_TASK_INFO2_TUNNEL_L4_LEN_MASK  0xFFF
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-#define HINIC_SQ_TASK_INFO2_OUTER_L3_LEN_MASK   0x7F
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-#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK  0x3
139
+#define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK   0xFF
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+#define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK    0xFF
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+#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK  0x7
133142 /* 1 bit reserved */
134143 #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK   0x3
135144 /* 8 bits reserved */
....@@ -151,6 +160,10 @@
151160 #define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT        31
152161 
153162 #define HINIC_RQ_CQE_STATUS_RXDONE_MASK         0x1
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+
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+#define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT	0
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+
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+#define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK	0xFFFFU
154167 
155168 #define HINIC_RQ_CQE_STATUS_GET(val, member)    \
156169 		(((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \
....@@ -187,12 +200,66 @@
187200 		 sizeof(struct hinic_sq_task) + \
188201 		 (nr_sges) * sizeof(struct hinic_sq_bufdesc))
189202 
190
-#define HINIC_SCMD_DATA_LEN             16
203
+#define HINIC_SCMD_DATA_LEN                     16
191204 
192
-#define HINIC_MAX_SQ_BUFDESCS           17
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+#define HINIC_MAX_SQ_BUFDESCS                   17
193206 
194
-#define HINIC_SQ_WQE_MAX_SIZE           320
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-#define HINIC_RQ_WQE_SIZE               32
207
+#define HINIC_SQ_WQE_MAX_SIZE                   320
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+#define HINIC_RQ_WQE_SIZE                       32
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+
210
+#define HINIC_MSS_DEFAULT		        0x3E00
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+#define HINIC_MSS_MIN		                0x50
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+
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+#define RQ_CQE_STATUS_NUM_LRO_SHIFT		16
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+#define RQ_CQE_STATUS_NUM_LRO_MASK		0xFFU
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+
216
+#define RQ_CQE_STATUS_GET(val, member)		(((val) >> \
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+			RQ_CQE_STATUS_##member##_SHIFT) & \
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+			RQ_CQE_STATUS_##member##_MASK)
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+
220
+#define HINIC_GET_RX_NUM_LRO(status)	\
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+		RQ_CQE_STATUS_GET(status, NUM_LRO)
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+
223
+#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT		0
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+#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK		0xFFFU
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+#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT		21
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+#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK		0x1U
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+
228
+#define RQ_CQE_OFFOLAD_TYPE_GET(val, member)		(((val) >> \
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+				RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \
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+				RQ_CQE_OFFOLAD_TYPE_##member##_MASK)
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+
232
+#define HINIC_GET_RX_PKT_TYPE(offload_type)	\
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+			RQ_CQE_OFFOLAD_TYPE_GET(offload_type, PKT_TYPE)
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+
235
+#define HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type)	\
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+			RQ_CQE_OFFOLAD_TYPE_GET(offload_type, VLAN_EN)
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+
238
+#define RQ_CQE_SGE_VLAN_MASK				0xFFFFU
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+#define RQ_CQE_SGE_VLAN_SHIFT				0
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+
241
+#define RQ_CQE_SGE_GET(val, member)			(((val) >> \
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+					RQ_CQE_SGE_##member##_SHIFT) & \
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+					RQ_CQE_SGE_##member##_MASK)
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+
245
+#define HINIC_GET_RX_VLAN_TAG(vlan_len)	\
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+		RQ_CQE_SGE_GET(vlan_len, VLAN)
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+
248
+#define HINIC_RSS_TYPE_VALID_SHIFT			23
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+#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT		24
250
+#define HINIC_RSS_TYPE_IPV6_EXT_SHIFT			25
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+#define HINIC_RSS_TYPE_TCP_IPV6_SHIFT			26
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+#define HINIC_RSS_TYPE_IPV6_SHIFT			27
253
+#define HINIC_RSS_TYPE_TCP_IPV4_SHIFT			28
254
+#define HINIC_RSS_TYPE_IPV4_SHIFT			29
255
+#define HINIC_RSS_TYPE_UDP_IPV6_SHIFT			30
256
+#define HINIC_RSS_TYPE_UDP_IPV4_SHIFT			31
257
+
258
+#define HINIC_RSS_TYPE_SET(val, member)                        \
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+		(((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
260
+
261
+#define HINIC_RSS_TYPE_GET(val, member)                        \
262
+		(((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
196263 
197264 enum hinic_l4offload_type {
198265 	HINIC_L4_OFF_DISABLE            = 0,
....@@ -209,6 +276,26 @@
209276 enum hinic_pkt_parsed {
210277 	HINIC_PKT_NOT_PARSED = 0,
211278 	HINIC_PKT_PARSED     = 1,
279
+};
280
+
281
+enum hinic_l3_offload_type {
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+	L3TYPE_UNKNOWN = 0,
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+	IPV6_PKT = 1,
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+	IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
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+	IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
286
+};
287
+
288
+enum hinic_l4_offload_type {
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+	OFFLOAD_DISABLE     = 0,
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+	TCP_OFFLOAD_ENABLE  = 1,
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+	SCTP_OFFLOAD_ENABLE = 2,
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+	UDP_OFFLOAD_ENABLE  = 3,
293
+};
294
+
295
+enum hinic_l4_tunnel_type {
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+	NOT_TUNNEL,
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+	TUNNEL_UDP_NO_CSUM,
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+	TUNNEL_UDP_CSUM,
212299 };
213300 
214301 enum hinic_outer_l3type {
....@@ -327,7 +414,7 @@
327414 	u32     status;
328415 	u32     len;
329416 
330
-	u32     rsvd2;
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+	u32     offload_type;
331418 	u32     rsvd3;
332419 	u32     rsvd4;
333420 	u32     rsvd5;