add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h
..
..
@@ -1,16 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * Huawei HiNIC PCI Express Linux driver
3
4
  * Copyright(c) 2017 Huawei Technologies Co., Ltd
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12
- * for more details.
13
- *
14
5
  */
15
6
 
16
7
 #ifndef HINIC_HW_QP_H
..
..
@@ -47,11 +38,14 @@
47
38
 #define HINIC_SQ_WQEBB_SIZE                     64
48
39
 #define HINIC_RQ_WQEBB_SIZE                     32
49
40
 
50
-#define HINIC_SQ_PAGE_SIZE                      SZ_4K
51
-#define HINIC_RQ_PAGE_SIZE                      SZ_4K
41
+#define HINIC_SQ_PAGE_SIZE                      SZ_256K
42
+#define HINIC_RQ_PAGE_SIZE                      SZ_256K
52
43
 
53
44
 #define HINIC_SQ_DEPTH                          SZ_4K
54
45
 #define HINIC_RQ_DEPTH                          SZ_4K
46
+
47
+#define HINIC_MAX_QUEUE_DEPTH			SZ_4K
48
+#define HINIC_MIN_QUEUE_DEPTH			128
55
49
 
56
50
 /* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
57
51
 #define HINIC_RX_BUF_SZ                         2048
..
..
@@ -87,6 +81,8 @@
87
81
 
88
82
 	struct hinic_wq         *wq;
89
83
 
84
+	u16			qid;
85
+
90
86
 	u32                     irq;
91
87
 	u16                     msix_entry;
92
88
 
..
..
@@ -96,12 +92,15 @@
96
92
 	void __iomem            *db_base;
97
93
 
98
94
 	struct sk_buff          **saved_skb;
95
+	struct hinic_debug_priv	*dbg;
99
96
 };
100
97
 
101
98
 struct hinic_rq {
102
99
 	struct hinic_hwif       *hwif;
103
100
 
104
101
 	struct hinic_wq         *wq;
102
+
103
+	u16			qid;
105
104
 
106
105
 	struct cpumask		affinity_mask;
107
106
 	u32                     irq;
..
..
@@ -116,6 +115,7 @@
116
115
 
117
116
 	u16                     *pi_virt_addr;
118
117
 	dma_addr_t              pi_dma_addr;
118
+	struct hinic_debug_priv	*dbg;
119
119
 };
120
120
 
121
121
 struct hinic_qp {
..
..
@@ -150,6 +150,31 @@
150
150
 
151
151
 int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);
152
152
 
153
+void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);
154
+
155
+void hinic_task_set_outter_l3(struct hinic_sq_task *task,
156
+			      enum hinic_l3_offload_type l3_type,
157
+			      u32 network_len);
158
+
159
+void hinic_task_set_inner_l3(struct hinic_sq_task *task,
160
+			     enum hinic_l3_offload_type l3_type,
161
+			     u32 network_len);
162
+
163
+void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
164
+			      enum hinic_l4_tunnel_type l4_type,
165
+			      u32 tunnel_len);
166
+
167
+void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
168
+			   u32 *queue_info,
169
+			   enum hinic_l4_offload_type l4_offload,
170
+			   u32 l4_len, u32 offset);
171
+
172
+void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
173
+			    u32 *queue_info,
174
+			    enum hinic_l4_offload_type l4_offload,
175
+			    u32 l4_len,
176
+			    u32 offset, u32 ip_ident, u32 mss);
177
+
153
178
 void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
154
179
 			  struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
155
180
 			  int nr_sges);
..
..
@@ -160,6 +185,8 @@
160
185
 struct hinic_sq_wqe *hinic_sq_get_wqe(struct hinic_sq *sq,
161
186
 				      unsigned int wqe_size, u16 *prod_idx);
162
187
 
188
+void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);
189
+
163
190
 void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
164
191
 			struct hinic_sq_wqe *wqe, struct sk_buff *skb,
165
192
 			unsigned int wqe_size);