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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/net/ethernet/huawei/hinic/hinic_hw_if.h
....@@ -1,16 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Huawei HiNIC PCI Express Linux driver
34  * Copyright(c) 2017 Huawei Technologies Co., Ltd
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
8
- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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- * for more details.
13
- *
145  */
156 
167 #ifndef HINIC_HW_IF_H
....@@ -20,6 +11,8 @@
2011 #include <linux/io.h>
2112 #include <linux/types.h>
2213 #include <asm/byteorder.h>
14
+
15
+#define HINIC_PCIE_LINK_DOWN					0xFFFFFFFF
2316 
2417 #define HINIC_DMA_ATTR_ST_SHIFT                                 0
2518 #define HINIC_DMA_ATTR_AT_SHIFT                                 8
....@@ -44,6 +37,7 @@
4437 #define HINIC_FA0_FUNC_IDX_SHIFT                                0
4538 #define HINIC_FA0_PF_IDX_SHIFT                                  10
4639 #define HINIC_FA0_PCI_INTF_IDX_SHIFT                            14
40
+#define HINIC_FA0_VF_IN_PF_SHIFT				16
4741 /* reserved members - off 16 */
4842 #define HINIC_FA0_FUNC_TYPE_SHIFT                               24
4943 
....@@ -51,6 +45,7 @@
5145 #define HINIC_FA0_PF_IDX_MASK                                   0xF
5246 #define HINIC_FA0_PCI_INTF_IDX_MASK                             0x3
5347 #define HINIC_FA0_FUNC_TYPE_MASK                                0x1
48
+#define HINIC_FA0_VF_IN_PF_MASK					0xFF
5449 
5550 #define HINIC_FA0_GET(val, member)                              \
5651 	(((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)
....@@ -62,16 +57,24 @@
6257 #define HINIC_FA1_IRQS_PER_FUNC_SHIFT                           20
6358 #define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT                       24
6459 /* reserved members - off 27 */
65
-#define HINIC_FA1_INIT_STATUS_SHIFT                             30
60
+#define HINIC_FA1_MGMT_INIT_STATUS_SHIFT			30
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+#define HINIC_FA1_PF_INIT_STATUS_SHIFT				31
6662 
6763 #define HINIC_FA1_AEQS_PER_FUNC_MASK                            0x3
6864 #define HINIC_FA1_CEQS_PER_FUNC_MASK                            0x7
6965 #define HINIC_FA1_IRQS_PER_FUNC_MASK                            0xF
7066 #define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK                        0x7
71
-#define HINIC_FA1_INIT_STATUS_MASK                              0x1
67
+#define HINIC_FA1_MGMT_INIT_STATUS_MASK                         0x1
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+#define HINIC_FA1_PF_INIT_STATUS_MASK				0x1
7269 
7370 #define HINIC_FA1_GET(val, member)                              \
7471 	(((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)
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+
73
+#define HINIC_FA2_GLOBAL_VF_ID_OF_PF_SHIFT	16
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+#define HINIC_FA2_GLOBAL_VF_ID_OF_PF_MASK	0x3FF
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+
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+#define HINIC_FA2_GET(val, member)				\
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+	(((val) >> HINIC_FA2_##member##_SHIFT) & HINIC_FA2_##member##_MASK)
7578 
7679 #define HINIC_FA4_OUTBOUND_STATE_SHIFT                          0
7780 #define HINIC_FA4_DB_STATE_SHIFT                                1
....@@ -149,10 +152,12 @@
149152 #define HINIC_HWIF_PPF_IDX(hwif)        ((hwif)->attr.ppf_idx)
150153 
151154 #define HINIC_FUNC_TYPE(hwif)           ((hwif)->attr.func_type)
155
+#define HINIC_IS_VF(hwif)               (HINIC_FUNC_TYPE(hwif) == HINIC_VF)
152156 #define HINIC_IS_PF(hwif)               (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
153157 #define HINIC_IS_PPF(hwif)              (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
154158 
155159 #define HINIC_PCI_CFG_REGS_BAR          0
160
+#define HINIC_PCI_INTR_REGS_BAR         2
156161 #define HINIC_PCI_DB_BAR                4
157162 
158163 #define HINIC_PCIE_ST_DISABLE           0
....@@ -164,6 +169,10 @@
164169 #define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT         0       /* Disabled */
165170 #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT  0       /* Disabled */
166171 #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT      7       /* max */
172
+
173
+#define HINIC_PCI_MSIX_ENTRY_SIZE               16
174
+#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL        12
175
+#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT       1
167176 
168177 enum hinic_pcie_nosnoop {
169178 	HINIC_PCIE_SNOOP        = 0,
....@@ -177,6 +186,7 @@
177186 
178187 enum hinic_func_type {
179188 	HINIC_PF        = 0,
189
+	HINIC_VF	    = 1,
180190 	HINIC_PPF       = 2,
181191 };
182192 
....@@ -184,7 +194,7 @@
184194 	HINIC_MOD_COMM  = 0,    /* HW communication module */
185195 	HINIC_MOD_L2NIC = 1,    /* L2NIC module */
186196 	HINIC_MOD_CFGM  = 7,    /* Configuration module */
187
-
197
+	HINIC_MOD_HILINK = 14,  /* Hilink module */
188198 	HINIC_MOD_MAX   = 15
189199 };
190200 
....@@ -208,6 +218,11 @@
208218 	HINIC_DB_DISABLE = 1,
209219 };
210220 
221
+enum hinic_msix_state {
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+	HINIC_MSIX_ENABLE,
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+	HINIC_MSIX_DISABLE,
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+};
225
+
211226 struct hinic_func_attr {
212227 	u16                     func_idx;
213228 	u8                      pf_idx;
....@@ -222,24 +237,31 @@
222237 	u8                      num_ceqs;
223238 
224239 	u8                      num_dma_attr;
240
+
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+	u16						global_vf_id_of_pf;
225242 };
226243 
227244 struct hinic_hwif {
228245 	struct pci_dev          *pdev;
229246 	void __iomem            *cfg_regs_bar;
247
+	void __iomem		*intr_regs_base;
230248 
231249 	struct hinic_func_attr  attr;
232250 };
233251 
234252 static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
235253 {
236
-	return be32_to_cpu(readl(hwif->cfg_regs_bar + reg));
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+	u32 out = readl(hwif->cfg_regs_bar + reg);
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+
256
+	return be32_to_cpu(*(__be32 *)&out);
237257 }
238258 
239259 static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
240260 					u32 val)
241261 {
242
-	writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg);
262
+	__be32 in = cpu_to_be32(val);
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+
264
+	writel(*(u32 *)&in, hwif->cfg_regs_bar + reg);
243265 }
244266 
245267 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
....@@ -251,6 +273,9 @@
251273 			u8 *pending_limit, u8 *coalesc_timer_cfg,
252274 			u8 *lli_timer, u8 *lli_credit_limit,
253275 			u8 *resend_timer);
276
+
277
+void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
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+			  enum hinic_msix_state flag);
254279 
255280 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
256281 
....@@ -266,6 +291,12 @@
266291 void hinic_db_state_set(struct hinic_hwif *hwif,
267292 			enum hinic_db_state db_state);
268293 
294
+u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif);
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+
296
+u16 hinic_global_func_id_hw(struct hinic_hwif *hwif);
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+
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+u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif);
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+
269300 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);
270301 
271302 void hinic_free_hwif(struct hinic_hwif *hwif);