forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/mtd/nand/raw/tegra_nand.c
....@@ -454,28 +454,24 @@
454454 		NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 4)),
455455 	);
456456 
457
+static void tegra_nand_select_target(struct nand_chip *chip,
458
+				     unsigned int die_nr)
459
+{
460
+	struct tegra_nand_chip *nand = to_tegra_chip(chip);
461
+	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
462
+
463
+	ctrl->cur_cs = nand->cs[die_nr];
464
+}
465
+
457466 static int tegra_nand_exec_op(struct nand_chip *chip,
458467 			      const struct nand_operation *op,
459468 			      bool check_only)
460469 {
470
+	if (!check_only)
471
+		tegra_nand_select_target(chip, op->cs);
472
+
461473 	return nand_op_parser_exec_op(chip, &tegra_nand_op_parser, op,
462474 				      check_only);
463
-}
464
-
465
-static void tegra_nand_select_chip(struct mtd_info *mtd, int die_nr)
466
-{
467
-	struct nand_chip *chip = mtd_to_nand(mtd);
468
-	struct tegra_nand_chip *nand = to_tegra_chip(chip);
469
-	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
470
-
471
-	WARN_ON(die_nr >= (int)ARRAY_SIZE(nand->cs));
472
-
473
-	if (die_nr < 0 || die_nr > 0) {
474
-		ctrl->cur_cs = -1;
475
-		return;
476
-	}
477
-
478
-	ctrl->cur_cs = nand->cs[die_nr];
479475 }
480476 
481477 static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
....@@ -483,7 +479,7 @@
483479 {
484480 	struct tegra_nand_chip *nand = to_tegra_chip(chip);
485481 
486
-	if (chip->ecc.algo == NAND_ECC_BCH && enable)
482
+	if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable)
487483 		writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
488484 	else
489485 		writel_relaxed(0, ctrl->regs + BCH_CONFIG);
....@@ -503,6 +499,8 @@
503499 	dma_addr_t dma_addr = 0, dma_addr_oob = 0;
504500 	u32 addr1, cmd, dma_ctrl;
505501 	int ret;
502
+
503
+	tegra_nand_select_target(chip, chip->cur_cs);
506504 
507505 	if (read) {
508506 		writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1);
....@@ -615,44 +613,46 @@
615613 	return ret;
616614 }
617615 
618
-static int tegra_nand_read_page_raw(struct mtd_info *mtd,
619
-				    struct nand_chip *chip, u8 *buf,
616
+static int tegra_nand_read_page_raw(struct nand_chip *chip, u8 *buf,
620617 				    int oob_required, int page)
621618 {
619
+	struct mtd_info *mtd = nand_to_mtd(chip);
622620 	void *oob_buf = oob_required ? chip->oob_poi : NULL;
623621 
624622 	return tegra_nand_page_xfer(mtd, chip, buf, oob_buf,
625623 				    mtd->oobsize, page, true);
626624 }
627625 
628
-static int tegra_nand_write_page_raw(struct mtd_info *mtd,
629
-				     struct nand_chip *chip, const u8 *buf,
626
+static int tegra_nand_write_page_raw(struct nand_chip *chip, const u8 *buf,
630627 				     int oob_required, int page)
631628 {
629
+	struct mtd_info *mtd = nand_to_mtd(chip);
632630 	void *oob_buf = oob_required ? chip->oob_poi : NULL;
633631 
634632 	return tegra_nand_page_xfer(mtd, chip, (void *)buf, oob_buf,
635633 				     mtd->oobsize, page, false);
636634 }
637635 
638
-static int tegra_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
639
-			       int page)
636
+static int tegra_nand_read_oob(struct nand_chip *chip, int page)
640637 {
638
+	struct mtd_info *mtd = nand_to_mtd(chip);
639
+
641640 	return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi,
642641 				    mtd->oobsize, page, true);
643642 }
644643 
645
-static int tegra_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
646
-				int page)
644
+static int tegra_nand_write_oob(struct nand_chip *chip, int page)
647645 {
646
+	struct mtd_info *mtd = nand_to_mtd(chip);
647
+
648648 	return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi,
649649 				    mtd->oobsize, page, false);
650650 }
651651 
652
-static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
653
-				      struct nand_chip *chip, u8 *buf,
652
+static int tegra_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
654653 				      int oob_required, int page)
655654 {
655
+	struct mtd_info *mtd = nand_to_mtd(chip);
656656 	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
657657 	struct tegra_nand_chip *nand = to_tegra_chip(chip);
658658 	void *oob_buf = oob_required ? chip->oob_poi : NULL;
....@@ -716,7 +716,7 @@
716716 		 * erased or if error correction just failed for all sub-
717717 		 * pages.
718718 		 */
719
-		ret = tegra_nand_read_oob(mtd, chip, page);
719
+		ret = tegra_nand_read_oob(chip, page);
720720 		if (ret < 0)
721721 			return ret;
722722 
....@@ -759,10 +759,10 @@
759759 	}
760760 }
761761 
762
-static int tegra_nand_write_page_hwecc(struct mtd_info *mtd,
763
-				       struct nand_chip *chip, const u8 *buf,
762
+static int tegra_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
764763 				       int oob_required, int page)
765764 {
765
+	struct mtd_info *mtd = nand_to_mtd(chip);
766766 	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
767767 	void *oob_buf = oob_required ? chip->oob_poi : NULL;
768768 	int ret;
....@@ -813,10 +813,9 @@
813813 	writel_relaxed(reg, ctrl->regs + TIMING_2);
814814 }
815815 
816
-static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
817
-					const struct nand_data_interface *conf)
816
+static int tegra_nand_setup_interface(struct nand_chip *chip, int csline,
817
+				      const struct nand_interface_config *conf)
818818 {
819
-	struct nand_chip *chip = mtd_to_nand(mtd);
820819 	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
821820 	const struct nand_sdr_timings *timings;
822821 
....@@ -841,7 +840,10 @@
841840 				   int strength_len, int bits_per_step,
842841 				   int oobsize)
843842 {
844
-	bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE;
843
+	struct nand_device *base = mtd_to_nanddev(nand_to_mtd(chip));
844
+	const struct nand_ecc_props *requirements =
845
+		nanddev_get_ecc_requirements(base);
846
+	bool maximize = base->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH;
845847 	int i;
846848 
847849 	/*
....@@ -856,7 +858,7 @@
856858 		} else {
857859 			strength_sel = strength[i];
858860 
859
-			if (strength_sel < chip->ecc_strength_ds)
861
+			if (strength_sel < requirements->strength)
860862 				continue;
861863 		}
862864 
....@@ -878,7 +880,7 @@
878880 	int strength_len, bits_per_step;
879881 
880882 	switch (chip->ecc.algo) {
881
-	case NAND_ECC_RS:
883
+	case NAND_ECC_ALGO_RS:
882884 		bits_per_step = BITS_PER_STEP_RS;
883885 		if (chip->options & NAND_IS_BOOT_MEDIUM) {
884886 			strength = rs_strength_bootable;
....@@ -888,7 +890,7 @@
888890 			strength_len = ARRAY_SIZE(rs_strength);
889891 		}
890892 		break;
891
-	case NAND_ECC_BCH:
893
+	case NAND_ECC_ALGO_BCH:
892894 		bits_per_step = BITS_PER_STEP_BCH;
893895 		if (chip->options & NAND_IS_BOOT_MEDIUM) {
894896 			strength = bch_strength_bootable;
....@@ -909,6 +911,8 @@
909911 static int tegra_nand_attach_chip(struct nand_chip *chip)
910912 {
911913 	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
914
+	const struct nand_ecc_props *requirements =
915
+		nanddev_get_ecc_requirements(&chip->base);
912916 	struct tegra_nand_chip *nand = to_tegra_chip(chip);
913917 	struct mtd_info *mtd = nand_to_mtd(chip);
914918 	int bits_per_step;
....@@ -917,12 +921,12 @@
917921 	if (chip->bbt_options & NAND_BBT_USE_FLASH)
918922 		chip->bbt_options |= NAND_BBT_NO_OOB;
919923 
920
-	chip->ecc.mode = NAND_ECC_HW;
924
+	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
921925 	chip->ecc.size = 512;
922926 	chip->ecc.steps = mtd->writesize / chip->ecc.size;
923
-	if (chip->ecc_step_ds != 512) {
927
+	if (requirements->step_size != 512) {
924928 		dev_err(ctrl->dev, "Unsupported step size %d\n",
925
-			chip->ecc_step_ds);
929
+			requirements->step_size);
926930 		return -EINVAL;
927931 	}
928932 
....@@ -936,14 +940,14 @@
936940 	if (chip->options & NAND_BUSWIDTH_16)
937941 		nand->config |= CONFIG_BUS_WIDTH_16;
938942 
939
-	if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
943
+	if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
940944 		if (mtd->writesize < 2048)
941
-			chip->ecc.algo = NAND_ECC_RS;
945
+			chip->ecc.algo = NAND_ECC_ALGO_RS;
942946 		else
943
-			chip->ecc.algo = NAND_ECC_BCH;
947
+			chip->ecc.algo = NAND_ECC_ALGO_BCH;
944948 	}
945949 
946
-	if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {
950
+	if (chip->ecc.algo == NAND_ECC_ALGO_BCH && mtd->writesize < 2048) {
947951 		dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n");
948952 		return -EINVAL;
949953 	}
....@@ -953,7 +957,7 @@
953957 		if (ret < 0) {
954958 			dev_err(ctrl->dev,
955959 				"No valid strength found, minimum %d\n",
956
-				chip->ecc_strength_ds);
960
+				requirements->strength);
957961 			return ret;
958962 		}
959963 
....@@ -964,7 +968,7 @@
964968 			   CONFIG_SKIP_SPARE_SIZE_4;
965969 
966970 	switch (chip->ecc.algo) {
967
-	case NAND_ECC_RS:
971
+	case NAND_ECC_ALGO_RS:
968972 		bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
969973 		mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
970974 		nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL |
....@@ -985,7 +989,7 @@
985989 			return -EINVAL;
986990 		}
987991 		break;
988
-	case NAND_ECC_BCH:
992
+	case NAND_ECC_ALGO_BCH:
989993 		bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
990994 		mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
991995 		nand->bch_config = BCH_ENABLE;
....@@ -1014,7 +1018,7 @@
10141018 	}
10151019 
10161020 	dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n",
1017
-		 chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS",
1021
+		 chip->ecc.algo == NAND_ECC_ALGO_BCH ? "BCH" : "RS",
10181022 		 chip->ecc.strength);
10191023 
10201024 	chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);
....@@ -1053,6 +1057,8 @@
10531057 
10541058 static const struct nand_controller_ops tegra_nand_controller_ops = {
10551059 	.attach_chip = &tegra_nand_attach_chip,
1060
+	.exec_op = tegra_nand_exec_op,
1061
+	.setup_interface = tegra_nand_setup_interface,
10561062 };
10571063 
10581064 static int tegra_nand_chips_init(struct device *dev,
....@@ -1114,10 +1120,7 @@
11141120 	if (!mtd->name)
11151121 		mtd->name = "tegra_nand";
11161122 
1117
-	chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
1118
-	chip->exec_op = tegra_nand_exec_op;
1119
-	chip->select_chip = tegra_nand_select_chip;
1120
-	chip->setup_data_interface = tegra_nand_setup_data_interface;
1123
+	chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA;
11211124 
11221125 	ret = nand_scan(chip, 1);
11231126 	if (ret)