add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/mtd/nand/raw/gpio.c
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@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * Updated, and converted to generic GPIO based driver by Russell King.
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  *
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..
@@ -9,11 +10,6 @@
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  * Device driver for NAND flash that uses a memory mapped interface to
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11
  * read/write the NAND commands and data, and GPIO pins for control signals
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  * (the DT binding refers to this as "GPIO assisted NAND flash")
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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13
  */
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14
 
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 #include <linux/kernel.h>
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@@ -29,8 +25,11 @@
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25
 #include <linux/mtd/nand-gpio.h>
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26
 #include <linux/of.h>
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27
 #include <linux/of_address.h>
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+#include <linux/delay.h>
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29
 
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 struct gpiomtd {
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+	struct nand_controller	base;
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+	void __iomem		*io;
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 	void __iomem		*io_sync;
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 	struct nand_chip	nand_chip;
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 	struct gpio_nand_platdata plat;
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@@ -73,32 +72,108 @@
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 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
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73
 #endif
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74
 
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-static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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+static int gpio_nand_exec_instr(struct nand_chip *chip,
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+				const struct nand_op_instr *instr)
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 {
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-	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
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+	struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
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+	unsigned int i;
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80
 
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-	gpio_nand_dosync(gpiomtd);
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-
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-	if (ctrl & NAND_CTRL_CHANGE) {
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-		if (gpiomtd->nce)
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-			gpiod_set_value(gpiomtd->nce, !(ctrl & NAND_NCE));
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-		gpiod_set_value(gpiomtd->cle, !!(ctrl & NAND_CLE));
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-		gpiod_set_value(gpiomtd->ale, !!(ctrl & NAND_ALE));
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+	switch (instr->type) {
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+	case NAND_OP_CMD_INSTR:
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 		gpio_nand_dosync(gpiomtd);
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+		gpiod_set_value(gpiomtd->cle, 1);
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+		gpio_nand_dosync(gpiomtd);
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+		writeb(instr->ctx.cmd.opcode, gpiomtd->io);
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+		gpio_nand_dosync(gpiomtd);
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+		gpiod_set_value(gpiomtd->cle, 0);
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+		return 0;
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+
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+	case NAND_OP_ADDR_INSTR:
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+		gpio_nand_dosync(gpiomtd);
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+		gpiod_set_value(gpiomtd->ale, 1);
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+		gpio_nand_dosync(gpiomtd);
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+		for (i = 0; i < instr->ctx.addr.naddrs; i++)
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+			writeb(instr->ctx.addr.addrs[i], gpiomtd->io);
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+		gpio_nand_dosync(gpiomtd);
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+		gpiod_set_value(gpiomtd->ale, 0);
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+		return 0;
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+
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+	case NAND_OP_DATA_IN_INSTR:
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+		gpio_nand_dosync(gpiomtd);
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+		if ((chip->options & NAND_BUSWIDTH_16) &&
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+		    !instr->ctx.data.force_8bit)
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+			ioread16_rep(gpiomtd->io, instr->ctx.data.buf.in,
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+				     instr->ctx.data.len / 2);
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+		else
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+			ioread8_rep(gpiomtd->io, instr->ctx.data.buf.in,
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+				    instr->ctx.data.len);
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+		return 0;
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+
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+	case NAND_OP_DATA_OUT_INSTR:
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+		gpio_nand_dosync(gpiomtd);
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+		if ((chip->options & NAND_BUSWIDTH_16) &&
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+		    !instr->ctx.data.force_8bit)
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+			iowrite16_rep(gpiomtd->io, instr->ctx.data.buf.out,
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+				      instr->ctx.data.len / 2);
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+		else
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+			iowrite8_rep(gpiomtd->io, instr->ctx.data.buf.out,
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+				     instr->ctx.data.len);
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+		return 0;
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+
123
+	case NAND_OP_WAITRDY_INSTR:
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+		if (!gpiomtd->rdy)
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+			return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
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+
127
+		return nand_gpio_waitrdy(chip, gpiomtd->rdy,
128
+					 instr->ctx.waitrdy.timeout_ms);
129
+
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+	default:
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+		return -EINVAL;
88
132
 	}
89
-	if (cmd == NAND_CMD_NONE)
90
-		return;
91
133
 
92
-	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
93
-	gpio_nand_dosync(gpiomtd);
134
+	return 0;
94
135
 }
95
136
 
96
-static int gpio_nand_devready(struct mtd_info *mtd)
137
+static int gpio_nand_exec_op(struct nand_chip *chip,
138
+			     const struct nand_operation *op,
139
+			     bool check_only)
97
140
 {
98
-	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
141
+	struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
142
+	unsigned int i;
143
+	int ret = 0;
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144
 
100
-	return gpiod_get_value(gpiomtd->rdy);
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+	if (check_only)
146
+		return 0;
147
+
148
+	gpio_nand_dosync(gpiomtd);
149
+	gpiod_set_value(gpiomtd->nce, 0);
150
+	for (i = 0; i < op->ninstrs; i++) {
151
+		ret = gpio_nand_exec_instr(chip, &op->instrs[i]);
152
+		if (ret)
153
+			break;
154
+
155
+		if (op->instrs[i].delay_ns)
156
+			ndelay(op->instrs[i].delay_ns);
157
+	}
158
+	gpio_nand_dosync(gpiomtd);
159
+	gpiod_set_value(gpiomtd->nce, 1);
160
+
161
+	return ret;
101
162
 }
163
+
164
+static int gpio_nand_attach_chip(struct nand_chip *chip)
165
+{
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+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
167
+	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
168
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
169
+
170
+	return 0;
171
+}
172
+
173
+static const struct nand_controller_ops gpio_nand_ops = {
174
+	.exec_op = gpio_nand_exec_op,
175
+	.attach_chip = gpio_nand_attach_chip,
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+};
102
177
 
103
178
 #ifdef CONFIG_OF
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179
 static const struct of_device_id gpio_nand_id_table[] = {
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@@ -193,8 +268,12 @@
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 static int gpio_nand_remove(struct platform_device *pdev)
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269
 {
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270
 	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
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+	struct nand_chip *chip = &gpiomtd->nand_chip;
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+	int ret;
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273
 
197
-	nand_release(&gpiomtd->nand_chip);
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+	ret = mtd_device_unregister(nand_to_mtd(chip));
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+	WARN_ON(ret);
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+	nand_cleanup(chip);
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277
 
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 	/* Enable write protection and disable the chip */
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 	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
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@@ -224,9 +303,9 @@
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 	chip = &gpiomtd->nand_chip;
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304
 
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 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	chip->IO_ADDR_R = devm_ioremap_resource(dev, res);
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-	if (IS_ERR(chip->IO_ADDR_R))
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-		return PTR_ERR(chip->IO_ADDR_R);
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+	gpiomtd->io = devm_ioremap_resource(dev, res);
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+	if (IS_ERR(gpiomtd->io))
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+		return PTR_ERR(gpiomtd->io);
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309
 
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 	res = gpio_nand_get_io_sync(pdev);
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311
 	if (res) {
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@@ -268,17 +347,13 @@
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 		ret = PTR_ERR(gpiomtd->rdy);
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348
 		goto out_ce;
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349
 	}
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-	/* Using RDY pin */
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-	if (gpiomtd->rdy)
273
-		chip->dev_ready = gpio_nand_devready;
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+
351
+	nand_controller_init(&gpiomtd->base);
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+	gpiomtd->base.ops = &gpio_nand_ops;
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353
 
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 	nand_set_flash_node(chip, pdev->dev.of_node);
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-	chip->IO_ADDR_W		= chip->IO_ADDR_R;
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-	chip->ecc.mode		= NAND_ECC_SOFT;
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-	chip->ecc.algo		= NAND_ECC_HAMMING;
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355
 	chip->options		= gpiomtd->plat.options;
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-	chip->chip_delay	= gpiomtd->plat.chip_delay;
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-	chip->cmd_ctrl		= gpio_nand_cmd_ctrl;
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+	chip->controller	= &gpiomtd->base;
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357
 
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 	mtd			= nand_to_mtd(chip);
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359
 	mtd->dev.parent		= dev;
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@@ -289,6 +364,13 @@
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364
 	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
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365
 		gpiod_direction_output(gpiomtd->nwp, 1);
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366
 
367
+	/*
368
+	 * This driver assumes that the default ECC engine should be TYPE_SOFT.
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+	 * Set ->engine_type before registering the NAND devices in order to
370
+	 * provide a driver specific default value.
371
+	 */
372
+	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
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+
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374
 	ret = nand_scan(chip, 1);
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 	if (ret)
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 		goto err_wp;