add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/mtd/nand/raw/denali_dt.c
..
..
@@ -1,19 +1,12 @@
1
+// SPDX-License-Identifier: GPL-2.0
1
2
 /*
2
3
  * NAND Flash Controller Device Driver for DT
3
4
  *
4
5
  * Copyright © 2011, Picochip.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
14
6
  */
15
7
 
16
8
 #include <linux/clk.h>
9
+#include <linux/delay.h>
17
10
 #include <linux/err.h>
18
11
 #include <linux/io.h>
19
12
 #include <linux/ioport.h>
..
..
@@ -22,19 +15,23 @@
22
15
 #include <linux/of.h>
23
16
 #include <linux/of_device.h>
24
17
 #include <linux/platform_device.h>
18
+#include <linux/reset.h>
25
19
 
26
20
 #include "denali.h"
27
21
 
28
22
 struct denali_dt {
29
-	struct denali_nand_info	denali;
23
+	struct denali_controller controller;
30
24
 	struct clk *clk;	/* core clock */
31
25
 	struct clk *clk_x;	/* bus interface clock */
32
26
 	struct clk *clk_ecc;	/* ECC circuit clock */
27
+	struct reset_control *rst;	/* core reset */
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+	struct reset_control *rst_reg;	/* register reset */
33
29
 };
34
30
 
35
31
 struct denali_dt_data {
36
32
 	unsigned int revision;
37
33
 	unsigned int caps;
34
+	unsigned int oob_skip_bytes;
38
35
 	const struct nand_ecc_caps *ecc_caps;
39
36
 };
40
37
 
..
..
@@ -42,6 +39,7 @@
42
39
 		     512, 8, 15);
43
40
 static const struct denali_dt_data denali_socfpga_data = {
44
41
 	.caps = DENALI_CAP_HW_ECC_FIXUP,
42
+	.oob_skip_bytes = 2,
45
43
 	.ecc_caps = &denali_socfpga_ecc_caps,
46
44
 };
47
45
 
..
..
@@ -50,6 +48,7 @@
50
48
 static const struct denali_dt_data denali_uniphier_v5a_data = {
51
49
 	.caps = DENALI_CAP_HW_ECC_FIXUP |
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50
 		DENALI_CAP_DMA_64BIT,
51
+	.oob_skip_bytes = 8,
53
52
 	.ecc_caps = &denali_uniphier_v5a_ecc_caps,
54
53
 };
55
54
 
..
..
@@ -59,6 +58,7 @@
59
58
 	.revision = 0x0501,
60
59
 	.caps = DENALI_CAP_HW_ECC_FIXUP |
61
60
 		DENALI_CAP_DMA_64BIT,
61
+	.oob_skip_bytes = 8,
62
62
 	.ecc_caps = &denali_uniphier_v5b_ecc_caps,
63
63
 };
64
64
 
..
..
@@ -79,33 +79,65 @@
79
79
 };
80
80
 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
81
81
 
82
+static int denali_dt_chip_init(struct denali_controller *denali,
83
+			       struct device_node *chip_np)
84
+{
85
+	struct denali_chip *dchip;
86
+	u32 bank;
87
+	int nsels, i, ret;
88
+
89
+	nsels = of_property_count_u32_elems(chip_np, "reg");
90
+	if (nsels < 0)
91
+		return nsels;
92
+
93
+	dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
94
+			     GFP_KERNEL);
95
+	if (!dchip)
96
+		return -ENOMEM;
97
+
98
+	dchip->nsels = nsels;
99
+
100
+	for (i = 0; i < nsels; i++) {
101
+		ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
102
+		if (ret)
103
+			return ret;
104
+
105
+		dchip->sels[i].bank = bank;
106
+
107
+		nand_set_flash_node(&dchip->chip, chip_np);
108
+	}
109
+
110
+	return denali_chip_init(denali, dchip);
111
+}
112
+
82
113
 static int denali_dt_probe(struct platform_device *pdev)
83
114
 {
84
115
 	struct device *dev = &pdev->dev;
85
116
 	struct resource *res;
86
117
 	struct denali_dt *dt;
87
118
 	const struct denali_dt_data *data;
88
-	struct denali_nand_info *denali;
119
+	struct denali_controller *denali;
120
+	struct device_node *np;
89
121
 	int ret;
90
122
 
91
123
 	dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
92
124
 	if (!dt)
93
125
 		return -ENOMEM;
94
-	denali = &dt->denali;
126
+	denali = &dt->controller;
95
127
 
96
128
 	data = of_device_get_match_data(dev);
97
-	if (data) {
98
-		denali->revision = data->revision;
99
-		denali->caps = data->caps;
100
-		denali->ecc_caps = data->ecc_caps;
101
-	}
129
+	if (WARN_ON(!data))
130
+		return -EINVAL;
131
+
132
+	denali->revision = data->revision;
133
+	denali->caps = data->caps;
134
+	denali->oob_skip_bytes = data->oob_skip_bytes;
135
+	denali->ecc_caps = data->ecc_caps;
102
136
 
103
137
 	denali->dev = dev;
104
138
 	denali->irq = platform_get_irq(pdev, 0);
105
-	if (denali->irq < 0) {
106
-		dev_err(dev, "no irq defined\n");
139
+	if (denali->irq < 0)
107
140
 		return denali->irq;
108
-	}
109
141
 
110
142
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg");
111
143
 	denali->reg = devm_ioremap_resource(dev, res);
..
..
@@ -117,25 +149,25 @@
117
149
 	if (IS_ERR(denali->host))
118
150
 		return PTR_ERR(denali->host);
119
151
 
120
-	/*
121
-	 * A single anonymous clock is supported for the backward compatibility.
122
-	 * New platforms should support all the named clocks.
123
-	 */
124
152
 	dt->clk = devm_clk_get(dev, "nand");
125
153
 	if (IS_ERR(dt->clk))
126
-		dt->clk = devm_clk_get(dev, NULL);
127
-	if (IS_ERR(dt->clk)) {
128
-		dev_err(dev, "no clk available\n");
129
154
 		return PTR_ERR(dt->clk);
130
-	}
131
155
 
132
156
 	dt->clk_x = devm_clk_get(dev, "nand_x");
133
157
 	if (IS_ERR(dt->clk_x))
134
-		dt->clk_x = NULL;
158
+		return PTR_ERR(dt->clk_x);
135
159
 
136
160
 	dt->clk_ecc = devm_clk_get(dev, "ecc");
137
161
 	if (IS_ERR(dt->clk_ecc))
138
-		dt->clk_ecc = NULL;
162
+		return PTR_ERR(dt->clk_ecc);
163
+
164
+	dt->rst = devm_reset_control_get_optional_shared(dev, "nand");
165
+	if (IS_ERR(dt->rst))
166
+		return PTR_ERR(dt->rst);
167
+
168
+	dt->rst_reg = devm_reset_control_get_optional_shared(dev, "reg");
169
+	if (IS_ERR(dt->rst_reg))
170
+		return PTR_ERR(dt->rst_reg);
139
171
 
140
172
 	ret = clk_prepare_enable(dt->clk);
141
173
 	if (ret)
..
..
@@ -149,27 +181,51 @@
149
181
 	if (ret)
150
182
 		goto out_disable_clk_x;
151
183
 
152
-	if (dt->clk_x) {
153
-		denali->clk_rate = clk_get_rate(dt->clk);
154
-		denali->clk_x_rate = clk_get_rate(dt->clk_x);
155
-	} else {
156
-		/*
157
-		 * Hardcode the clock rates for the backward compatibility.
158
-		 * This works for both SOCFPGA and UniPhier.
159
-		 */
160
-		dev_notice(dev,
161
-			   "necessary clock is missing. default clock rates are used.\n");
162
-		denali->clk_rate = 50000000;
163
-		denali->clk_x_rate = 200000000;
164
-	}
184
+	denali->clk_rate = clk_get_rate(dt->clk);
185
+	denali->clk_x_rate = clk_get_rate(dt->clk_x);
165
186
 
166
-	ret = denali_init(denali);
187
+	/*
188
+	 * Deassert the register reset, and the core reset in this order.
189
+	 * Deasserting the core reset while the register reset is asserted
190
+	 * will cause unpredictable behavior in the controller.
191
+	 */
192
+	ret = reset_control_deassert(dt->rst_reg);
167
193
 	if (ret)
168
194
 		goto out_disable_clk_ecc;
169
195
 
196
+	ret = reset_control_deassert(dt->rst);
197
+	if (ret)
198
+		goto out_assert_rst_reg;
199
+
200
+	/*
201
+	 * When the reset is deasserted, the initialization sequence is kicked
202
+	 * (bootstrap process). The driver must wait until it finished.
203
+	 * Otherwise, it will result in unpredictable behavior.
204
+	 */
205
+	usleep_range(200, 1000);
206
+
207
+	ret = denali_init(denali);
208
+	if (ret)
209
+		goto out_assert_rst;
210
+
211
+	for_each_child_of_node(dev->of_node, np) {
212
+		ret = denali_dt_chip_init(denali, np);
213
+		if (ret) {
214
+			of_node_put(np);
215
+			goto out_remove_denali;
216
+		}
217
+	}
218
+
170
219
 	platform_set_drvdata(pdev, dt);
220
+
171
221
 	return 0;
172
222
 
223
+out_remove_denali:
224
+	denali_remove(denali);
225
+out_assert_rst:
226
+	reset_control_assert(dt->rst);
227
+out_assert_rst_reg:
228
+	reset_control_assert(dt->rst_reg);
173
229
 out_disable_clk_ecc:
174
230
 	clk_disable_unprepare(dt->clk_ecc);
175
231
 out_disable_clk_x:
..
..
@@ -184,7 +240,9 @@
184
240
 {
185
241
 	struct denali_dt *dt = platform_get_drvdata(pdev);
186
242
 
187
-	denali_remove(&dt->denali);
243
+	denali_remove(&dt->controller);
244
+	reset_control_assert(dt->rst);
245
+	reset_control_assert(dt->rst_reg);
188
246
 	clk_disable_unprepare(dt->clk_ecc);
189
247
 	clk_disable_unprepare(dt->clk_x);
190
248
 	clk_disable_unprepare(dt->clk);
..
..
@@ -202,6 +260,6 @@
202
260
 };
203
261
 module_platform_driver(denali_dt_driver);
204
262
 
205
-MODULE_LICENSE("GPL");
263
+MODULE_LICENSE("GPL v2");
206
264
 MODULE_AUTHOR("Jamie Iles");
207
265
 MODULE_DESCRIPTION("DT driver for Denali NAND controller");