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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * BCM47XX NAND flash driver |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License version 2 as |
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8 | | - * published by the Free Software Foundation. |
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9 | | - * |
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10 | 6 | */ |
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11 | 7 | |
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12 | 8 | #include "bcm47xxnflash.h" |
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.. | .. |
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170 | 166 | * NAND chip ops |
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171 | 167 | **************************************************/ |
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172 | 168 | |
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173 | | -static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct mtd_info *mtd, int cmd, |
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174 | | - unsigned int ctrl) |
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| 169 | +static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct nand_chip *nand_chip, |
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| 170 | + int cmd, unsigned int ctrl) |
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175 | 171 | { |
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176 | | - struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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177 | 172 | struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip); |
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178 | 173 | u32 code = 0; |
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179 | 174 | |
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.. | .. |
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191 | 186 | } |
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192 | 187 | |
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193 | 188 | /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */ |
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194 | | -static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd, |
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195 | | - int chip) |
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| 189 | +static void bcm47xxnflash_ops_bcm4706_select_chip(struct nand_chip *chip, |
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| 190 | + int cs) |
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196 | 191 | { |
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197 | 192 | return; |
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198 | 193 | } |
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199 | 194 | |
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200 | | -static int bcm47xxnflash_ops_bcm4706_dev_ready(struct mtd_info *mtd) |
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| 195 | +static int bcm47xxnflash_ops_bcm4706_dev_ready(struct nand_chip *nand_chip) |
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201 | 196 | { |
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202 | | - struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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203 | 197 | struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip); |
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204 | 198 | |
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205 | 199 | return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY); |
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.. | .. |
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212 | 206 | * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert |
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213 | 207 | * standard commands would be much more complicated. |
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214 | 208 | */ |
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215 | | -static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd, |
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| 209 | +static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct nand_chip *nand_chip, |
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216 | 210 | unsigned command, int column, |
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217 | 211 | int page_addr) |
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218 | 212 | { |
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219 | | - struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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| 213 | + struct mtd_info *mtd = nand_to_mtd(nand_chip); |
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220 | 214 | struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip); |
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221 | 215 | struct bcma_drv_cc *cc = b47n->cc; |
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222 | 216 | u32 ctlcode; |
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.. | .. |
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229 | 223 | |
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230 | 224 | switch (command) { |
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231 | 225 | case NAND_CMD_RESET: |
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232 | | - nand_chip->cmd_ctrl(mtd, command, NAND_CTRL_CLE); |
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| 226 | + nand_chip->legacy.cmd_ctrl(nand_chip, command, NAND_CTRL_CLE); |
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233 | 227 | |
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234 | 228 | ndelay(100); |
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235 | | - nand_wait_ready(mtd); |
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| 229 | + nand_wait_ready(nand_chip); |
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236 | 230 | break; |
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237 | 231 | case NAND_CMD_READID: |
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238 | 232 | ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0; |
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.. | .. |
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310 | 304 | b47n->curr_command = command; |
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311 | 305 | } |
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312 | 306 | |
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313 | | -static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd) |
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| 307 | +static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct nand_chip *nand_chip) |
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314 | 308 | { |
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315 | | - struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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| 309 | + struct mtd_info *mtd = nand_to_mtd(nand_chip); |
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316 | 310 | struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip); |
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317 | 311 | struct bcma_drv_cc *cc = b47n->cc; |
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318 | 312 | u32 tmp = 0; |
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.. | .. |
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338 | 332 | return 0; |
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339 | 333 | } |
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340 | 334 | |
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341 | | -static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd, |
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| 335 | +static void bcm47xxnflash_ops_bcm4706_read_buf(struct nand_chip *nand_chip, |
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342 | 336 | uint8_t *buf, int len) |
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343 | 337 | { |
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344 | | - struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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345 | 338 | struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip); |
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346 | 339 | |
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347 | 340 | switch (b47n->curr_command) { |
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348 | 341 | case NAND_CMD_READ0: |
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349 | 342 | case NAND_CMD_READOOB: |
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350 | | - bcm47xxnflash_ops_bcm4706_read(mtd, buf, len); |
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| 343 | + bcm47xxnflash_ops_bcm4706_read(nand_to_mtd(nand_chip), buf, |
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| 344 | + len); |
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351 | 345 | return; |
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352 | 346 | } |
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353 | 347 | |
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354 | 348 | pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command); |
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355 | 349 | } |
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356 | 350 | |
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357 | | -static void bcm47xxnflash_ops_bcm4706_write_buf(struct mtd_info *mtd, |
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| 351 | +static void bcm47xxnflash_ops_bcm4706_write_buf(struct nand_chip *nand_chip, |
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358 | 352 | const uint8_t *buf, int len) |
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359 | 353 | { |
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360 | | - struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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361 | 354 | struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip); |
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362 | 355 | |
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363 | 356 | switch (b47n->curr_command) { |
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364 | 357 | case NAND_CMD_SEQIN: |
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365 | | - bcm47xxnflash_ops_bcm4706_write(mtd, buf, len); |
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| 358 | + bcm47xxnflash_ops_bcm4706_write(nand_to_mtd(nand_chip), buf, |
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| 359 | + len); |
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366 | 360 | return; |
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367 | 361 | } |
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368 | 362 | |
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.. | .. |
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385 | 379 | u8 tbits, col_bits, col_size, row_bits, row_bsize; |
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386 | 380 | u32 val; |
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387 | 381 | |
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388 | | - b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip; |
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389 | | - nand_chip->cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl; |
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390 | | - nand_chip->dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready; |
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391 | | - b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc; |
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392 | | - b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; |
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393 | | - b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; |
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394 | | - b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf; |
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395 | | - b47n->nand_chip.set_features = nand_get_set_features_notsupp; |
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396 | | - b47n->nand_chip.get_features = nand_get_set_features_notsupp; |
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| 382 | + nand_chip->legacy.select_chip = bcm47xxnflash_ops_bcm4706_select_chip; |
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| 383 | + nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl; |
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| 384 | + nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready; |
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| 385 | + b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc; |
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| 386 | + b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; |
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| 387 | + b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; |
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| 388 | + b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf; |
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| 389 | + b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp; |
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| 390 | + b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp; |
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397 | 391 | |
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398 | | - nand_chip->chip_delay = 50; |
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| 392 | + nand_chip->legacy.chip_delay = 50; |
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399 | 393 | b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; |
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400 | | - b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */ |
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| 394 | + /* TODO: implement ECC */ |
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| 395 | + b47n->nand_chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_NONE; |
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401 | 396 | |
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402 | 397 | /* Enable NAND flash access */ |
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403 | 398 | bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG, |
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.. | .. |
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430 | 425 | } |
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431 | 426 | |
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432 | 427 | /* Configure FLASH */ |
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433 | | - chipsize = b47n->nand_chip.chipsize >> 20; |
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| 428 | + chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20; |
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434 | 429 | tbits = ffs(chipsize); /* find first bit set */ |
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435 | 430 | if (!tbits || tbits != fls(chipsize)) { |
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436 | 431 | pr_err("Invalid flash size: 0x%lX\n", chipsize); |
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