add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/mmc/host/sdhci-esdhc.h
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@@ -1,14 +1,12 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Freescale eSDHC controller driver generics for OF and pltfm.
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  *
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  * Copyright (c) 2007 Freescale Semiconductor, Inc.
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  * Copyright (c) 2009 MontaVista Software, Inc.
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  * Copyright (c) 2010 Pengutronix e.K.
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- *   Author: Wolfram Sang <w.sang@pengutronix.de>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License.
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+ * Copyright 2020 NXP
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+ *   Author: Wolfram Sang <kernel@pengutronix.de>
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  */
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 #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
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@@ -34,6 +32,7 @@
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 /* Present State Register */
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 #define ESDHC_PRSSTAT			0x24
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+#define ESDHC_CLOCK_GATE_OFF		0x00000080
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 #define ESDHC_CLOCK_STABLE		0x00000008
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 /* Protocol Control Register */
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@@ -54,12 +53,52 @@
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 #define ESDHC_CLOCK_HCKEN		0x00000002
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 #define ESDHC_CLOCK_IPGEN		0x00000001
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+/* System Control 2 Register */
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+#define ESDHC_SYSTEM_CONTROL_2		0x3c
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+#define ESDHC_SMPCLKSEL			0x00800000
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+#define ESDHC_EXTN			0x00400000
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+
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 /* Host Controller Capabilities Register 2 */
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 #define ESDHC_CAPABILITIES_1		0x114
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 /* Tuning Block Control Register */
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 #define ESDHC_TBCTL			0x120
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+#define ESDHC_HS400_WNDW_ADJUST		0x00000040
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+#define ESDHC_HS400_MODE		0x00000010
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 #define ESDHC_TB_EN			0x00000004
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+#define ESDHC_TB_MODE_MASK		0x00000003
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+#define ESDHC_TB_MODE_SW		0x00000003
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+#define ESDHC_TB_MODE_3			0x00000002
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+
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+#define ESDHC_TBSTAT			0x124
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+
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+#define ESDHC_TBPTR			0x128
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+#define ESDHC_WNDW_STRT_PTR_SHIFT	8
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+#define ESDHC_WNDW_STRT_PTR_MASK	(0x7f << 8)
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+#define ESDHC_WNDW_END_PTR_MASK		0x7f
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+
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+/* SD Clock Control Register */
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+#define ESDHC_SDCLKCTL			0x144
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+#define ESDHC_LPBK_CLK_SEL		0x80000000
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+#define ESDHC_CMD_CLK_CTL		0x00008000
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+
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+/* SD Timing Control Register */
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+#define ESDHC_SDTIMNGCTL		0x148
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+#define ESDHC_FLW_CTL_BG		0x00008000
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+
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+/* DLL Config 0 Register */
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+#define ESDHC_DLLCFG0			0x160
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+#define ESDHC_DLL_ENABLE		0x80000000
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+#define ESDHC_DLL_RESET			0x40000000
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+#define ESDHC_DLL_FREQ_SEL		0x08000000
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+
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+/* DLL Config 1 Register */
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+#define ESDHC_DLLCFG1			0x164
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+#define ESDHC_DLL_PD_PULSE_STRETCH_SEL	0x80000000
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+
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+/* DLL Status 0 Register */
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+#define ESDHC_DLLSTAT0			0x170
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+#define ESDHC_DLL_STS_SLV_LOCK		0x08000000
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 /* Control Register for DMA transfer */
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 #define ESDHC_DMA_SYSCTL		0x40c