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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/mmc/host/renesas_sdhi_internal_dmac.c
....@@ -1,12 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * DMA support for Internal DMAC with SDHI SD/SDIO controller
34  *
4
- * Copyright (C) 2016-17 Renesas Electronics Corporation
5
+ * Copyright (C) 2016-19 Renesas Electronics Corporation
56  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
9
- * published by the Free Software Foundation.
7
+ * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
108  */
119 
1210 #include <linux/bitops.h>
....@@ -35,9 +33,9 @@
3533 
3634 /* DM_CM_DTRAN_MODE */
3735 #define DTRAN_MODE_CH_NUM_CH0	0	/* "downstream" = for write commands */
38
-#define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "uptream" = for read commands */
39
-#define DTRAN_MODE_BUS_WID_TH	(BIT(5) | BIT(4))
40
-#define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address */
36
+#define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "upstream" = for read commands */
37
+#define DTRAN_MODE_BUS_WIDTH	(BIT(5) | BIT(4))
38
+#define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address, 0 = Fixed */
4139 
4240 /* DM_CM_DTRAN_CTRL */
4341 #define DTRAN_CTRL_DM_START	BIT(0)
....@@ -76,27 +74,30 @@
7674 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY	0
7775 #define SDHI_INTERNAL_DMAC_RX_IN_USE	1
7876 
77
+/* RZ/A2 does not have the ADRR_MODE bit */
78
+#define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
79
+
7980 /* Definitions for sampling clocks */
8081 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
8182 	{
8283 		.clk_rate = 0,
8384 		.tap = 0x00000300,
85
+		.tap_hs400_4tap = 0x00000100,
8486 	},
8587 };
8688 
87
-static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
89
+static const struct renesas_sdhi_of_data of_rza2_compatible = {
8890 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
89
-			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
90
-			  TMIO_MMC_HAVE_4TAP_HS400,
91
+			  TMIO_MMC_HAVE_CBSY,
92
+	.tmio_ocr_mask	= MMC_VDD_32_33,
9193 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
9294 			  MMC_CAP_CMD23,
93
-	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
9495 	.bus_shift	= 2,
95
-	.scc_offset	= 0x1000,
96
+	.scc_offset	= 0 - 0x1000,
9697 	.taps		= rcar_gen3_scc_taps,
9798 	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
98
-	/* DMAC can handle 0xffffffff blk count but only 1 segment */
99
-	.max_blk_count	= 0xffffffff,
99
+	/* DMAC can handle 32bit blk count but only 1 segment */
100
+	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
100101 	.max_segs	= 1,
101102 };
102103 
....@@ -105,19 +106,21 @@
105106 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
106107 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
107108 			  MMC_CAP_CMD23,
108
-	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
109
+	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
109110 	.bus_shift	= 2,
110111 	.scc_offset	= 0x1000,
111112 	.taps		= rcar_gen3_scc_taps,
112113 	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
113
-	/* DMAC can handle 0xffffffff blk count but only 1 segment */
114
-	.max_blk_count	= 0xffffffff,
114
+	/* DMAC can handle 32bit blk count but only 1 segment */
115
+	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
115116 	.max_segs	= 1,
116117 };
117118 
118119 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
119
-	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, },
120
-	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, },
120
+	{ .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
121
+	{ .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
122
+	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
123
+	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
121124 	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
122125 	{},
123126 };
....@@ -174,7 +177,10 @@
174177 				     struct mmc_data *data)
175178 {
176179 	struct scatterlist *sg = host->sg_ptr;
177
-	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
180
+	u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
181
+
182
+	if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags))
183
+		dtran_mode |= DTRAN_MODE_ADDR_MODE;
178184 
179185 	if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
180186 			mmc_get_dma_dir(data)))
....@@ -201,13 +207,14 @@
201207 	renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
202208 					    sg_dma_address(sg));
203209 
210
+	host->dma_on = true;
211
+
204212 	return;
205213 
206214 force_pio_with_unmap:
207215 	dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
208216 
209217 force_pio:
210
-	host->force_pio = true;
211218 	renesas_sdhi_internal_dmac_enable_dma(host, false);
212219 }
213220 
....@@ -226,6 +233,9 @@
226233 {
227234 	enum dma_data_direction dir;
228235 
236
+	if (!host->dma_on)
237
+		return false;
238
+
229239 	if (!host->data)
230240 		return false;
231241 
....@@ -239,6 +249,8 @@
239249 
240250 	if (dir == DMA_FROM_DEVICE)
241251 		clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
252
+
253
+	host->dma_on = false;
242254 
243255 	return true;
244256 }
....@@ -254,6 +266,12 @@
254266 	tmio_mmc_do_data_irq(host);
255267 out:
256268 	spin_unlock_irq(&host->lock);
269
+}
270
+
271
+static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
272
+{
273
+	if (host->data)
274
+		renesas_sdhi_internal_dmac_complete(host);
257275 }
258276 
259277 static void
....@@ -293,41 +311,30 @@
293311 	.release = renesas_sdhi_internal_dmac_release_dma,
294312 	.abort = renesas_sdhi_internal_dmac_abort_dma,
295313 	.dataend = renesas_sdhi_internal_dmac_dataend_dma,
314
+	.end = renesas_sdhi_internal_dmac_end_dma,
296315 };
297316 
298317 /*
299318  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
300319  * implementation as others may use a different implementation.
301320  */
302
-static const struct soc_device_attribute gen3_soc_whitelist[] = {
303
-	/* specific ones */
321
+static const struct soc_device_attribute soc_dma_quirks[] = {
322
+	{ .soc_id = "r7s9210",
323
+	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
304324 	{ .soc_id = "r8a7795", .revision = "ES1.*",
305325 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
306326 	{ .soc_id = "r8a7796", .revision = "ES1.0",
307327 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
308
-	/* generic ones */
309
-	{ .soc_id = "r8a774a1" },
310
-	{ .soc_id = "r8a7795" },
311
-	{ .soc_id = "r8a7796" },
312
-	{ .soc_id = "r8a77965" },
313
-	{ .soc_id = "r8a77980" },
314
-	{ .soc_id = "r8a77995" },
315328 	{ /* sentinel */ }
316329 };
317330 
318331 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
319332 {
320
-	const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist);
333
+	const struct soc_device_attribute *soc = soc_device_match(soc_dma_quirks);
321334 	struct device *dev = &pdev->dev;
322335 
323
-	if (!soc)
324
-		return -ENODEV;
325
-
326
-	global_flags |= (unsigned long)soc->data;
327
-
328
-	dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
329
-	if (!dev->dma_parms)
330
-		return -ENOMEM;
336
+	if (soc)
337
+		global_flags |= (unsigned long)soc->data;
331338 
332339 	/* value is max of SD_SECCNT. Confirmed by HW engineers */
333340 	dma_set_max_seg_size(dev, 0xffffffff);
....@@ -346,6 +353,7 @@
346353 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
347354 	.driver		= {
348355 		.name	= "renesas_sdhi_internal_dmac",
356
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
349357 		.pm	= &renesas_sdhi_internal_dmac_dev_pm_ops,
350358 		.of_match_table = renesas_sdhi_internal_dmac_of_match,
351359 	},