add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/misc/mei/hw-me.h
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@@ -1,20 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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- *
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+ * Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
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  * Intel Management Engine Interface (Intel MEI) Linux driver
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- * Copyright (c) 2003-2012, Intel Corporation.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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  */
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-
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-
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 #ifndef _MEI_INTERFACE_H_
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 #define _MEI_INTERFACE_H_
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@@ -31,14 +19,18 @@
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  *
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  * @fw_status: FW status
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  * @quirk_probe: device exclusion quirk
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+ * @kind: MEI head kind
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  * @dma_size: device DMA buffers size
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  * @fw_ver_supported: is fw version retrievable from FW
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+ * @hw_trc_supported: does the hw support trc register
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  */
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 struct mei_cfg {
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 	const struct mei_fw_status fw_status;
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-	bool (*quirk_probe)(struct pci_dev *pdev);
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+	bool (*quirk_probe)(const struct pci_dev *pdev);
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+	const char *kind;
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 	size_t dma_size[DMA_DSCR_NUM];
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 	u32 fw_ver_supported:1;
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+	u32 hw_trc_supported:1;
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 };
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@@ -54,16 +46,20 @@
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  *
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  * @cfg: per device generation config and ops
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  * @mem_addr: io memory address
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+ * @irq: irq number
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  * @pg_state: power gating state
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  * @d0i3_supported: di03 support
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  * @hbuf_depth: depth of hardware host/write buffer in slots
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+ * @read_fws: read FW status register handler
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  */
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 struct mei_me_hw {
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 	const struct mei_cfg *cfg;
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 	void __iomem *mem_addr;
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+	int irq;
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 	enum mei_pg_state pg_state;
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 	bool d0i3_supported;
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 	u8 hbuf_depth;
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+	int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
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 };
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 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
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@@ -82,10 +78,22 @@
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  *                         with quirk for Node Manager exclusion.
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  * @MEI_ME_PCH8_CFG:       Platform Controller Hub Gen8 and newer
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  *                         client platforms.
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- * @MEI_ME_PCH8_SPS_CFG:   Platform Controller Hub Gen8 and newer
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+ * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
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+ *                         client platforms (iTouch).
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+ * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
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  *                         servers platforms with quirk for
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  *                         SPS firmware exclusion.
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  * @MEI_ME_PCH12_CFG:      Platform Controller Hub Gen12 and newer
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+ * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
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+ *                         servers platforms with quirk for
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+ *                         SPS firmware exclusion.
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+ * @MEI_ME_PCH12_SPS_CFG:  Platform Controller Hub Gen12 5.0 and newer
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+ *                         servers platforms with quirk for
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+ *                         SPS firmware exclusion.
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+ * @MEI_ME_PCH15_CFG:      Platform Controller Hub Gen15 and newer
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+ * @MEI_ME_PCH15_SPS_CFG:  Platform Controller Hub Gen15 and newer
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+ *                         servers platforms with quirk for
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+ *                         SPS firmware exclusion.
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  * @MEI_ME_NUM_CFG:        Upper Sentinel.
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  */
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 enum mei_cfg_idx {
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@@ -96,14 +104,20 @@
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 	MEI_ME_PCH7_CFG,
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 	MEI_ME_PCH_CPT_PBG_CFG,
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 	MEI_ME_PCH8_CFG,
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-	MEI_ME_PCH8_SPS_CFG,
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+	MEI_ME_PCH8_ITOUCH_CFG,
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+	MEI_ME_PCH8_SPS_4_CFG,
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 	MEI_ME_PCH12_CFG,
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+	MEI_ME_PCH12_SPS_4_CFG,
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+	MEI_ME_PCH12_SPS_CFG,
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+	MEI_ME_PCH12_SPS_ITOUCH_CFG,
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+	MEI_ME_PCH15_CFG,
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+	MEI_ME_PCH15_SPS_CFG,
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 	MEI_ME_NUM_CFG,
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 };
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 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
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-struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
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+struct mei_device *mei_me_dev_init(struct device *parent,
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 				   const struct mei_cfg *cfg);
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 int mei_me_pg_enter_sync(struct mei_device *dev);