add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/media/rc/sunxi-cir.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Driver for Allwinner sunXi IR controller
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  *
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@@ -7,16 +8,6 @@
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  * Based on sun5i-ir.c:
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  * Copyright (C) 2007-2012 Daniel Wang
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  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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- * the License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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11
  */
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12
 
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 #include <linux/clk.h>
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@@ -48,11 +39,11 @@
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39
 
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 /* Rx Interrupt Enable */
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 #define SUNXI_IR_RXINT_REG    0x2C
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-/* Rx FIFO Overflow */
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+/* Rx FIFO Overflow Interrupt Enable */
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 #define REG_RXINT_ROI_EN		BIT(0)
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-/* Rx Packet End */
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+/* Rx Packet End Interrupt Enable */
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 #define REG_RXINT_RPEI_EN		BIT(1)
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-/* Rx FIFO Data Available */
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+/* Rx FIFO Data Available Interrupt Enable */
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 #define REG_RXINT_RAI_EN		BIT(4)
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48
 
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 /* Rx FIFO available byte level */
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@@ -60,6 +51,12 @@
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51
 
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 /* Rx Interrupt Status */
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 #define SUNXI_IR_RXSTA_REG    0x30
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+/* Rx FIFO Overflow */
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+#define REG_RXSTA_ROI			REG_RXINT_ROI_EN
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+/* Rx Packet End */
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+#define REG_RXSTA_RPE			REG_RXINT_RPEI_EN
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+/* Rx FIFO Data Available */
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+#define REG_RXSTA_RA			REG_RXINT_RAI_EN
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 /* RX FIFO Get Available Counter */
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 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
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 /* Clear all interrupt status value */
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@@ -81,6 +78,17 @@
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 /* Time after which device stops sending data in ms */
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 #define SUNXI_IR_TIMEOUT      120
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80
 
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+/**
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+ * struct sunxi_ir_quirks - Differences between SoC variants.
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+ *
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+ * @has_reset: SoC needs reset deasserted.
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+ * @fifo_size: size of the fifo.
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+ */
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+struct sunxi_ir_quirks {
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+	bool		has_reset;
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+	int		fifo_size;
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+};
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+
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 struct sunxi_ir {
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 	spinlock_t      ir_lock;
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94
 	struct rc_dev   *rc;
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@@ -99,7 +107,7 @@
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 	unsigned char dt;
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 	unsigned int cnt, rc;
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 	struct sunxi_ir *ir = dev_id;
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-	DEFINE_IR_RAW_EVENT(rawir);
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+	struct ir_raw_event rawir = {};
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111
 
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 	spin_lock(&ir->ir_lock);
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113
 
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@@ -108,7 +116,7 @@
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 	/* clean all pending statuses */
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 	writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
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118
 
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-	if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
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+	if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {
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 		/* How many messages in fifo */
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 		rc  = REG_RXSTA_GET_AC(status);
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122
 		/* Sanity check */
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@@ -124,9 +132,9 @@
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132
 		}
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 	}
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134
 
127
-	if (status & REG_RXINT_ROI_EN) {
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+	if (status & REG_RXSTA_ROI) {
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 		ir_raw_event_reset(ir->rc);
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-	} else if (status & REG_RXINT_RPEI_EN) {
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+	} else if (status & REG_RXSTA_RPE) {
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 		ir_raw_event_set_idle(ir->rc, true);
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 		ir_raw_event_handle(ir->rc);
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 	} else {
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@@ -145,6 +153,7 @@
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153
 
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 	struct device *dev = &pdev->dev;
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 	struct device_node *dn = dev->of_node;
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+	const struct sunxi_ir_quirks *quirks;
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 	struct resource *res;
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 	struct sunxi_ir *ir;
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 	u32 b_clk_freq = SUNXI_IR_BASE_CLK;
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@@ -153,12 +162,15 @@
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 	if (!ir)
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 		return -ENOMEM;
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164
 
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+	quirks = of_device_get_match_data(&pdev->dev);
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+	if (!quirks) {
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+		dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
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+		return -ENODEV;
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+	}
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+
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 	spin_lock_init(&ir->ir_lock);
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172
 
158
-	if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
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-		ir->fifo_size = 64;
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-	else
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-		ir->fifo_size = 16;
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+	ir->fifo_size = quirks->fifo_size;
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174
 
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 	/* Clock */
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 	ir->apb_clk = devm_clk_get(dev, "apb");
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@@ -175,13 +187,15 @@
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 	/* Base clock frequency (optional) */
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 	of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
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189
 
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-	/* Reset (optional) */
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-	ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
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-	if (IS_ERR(ir->rst))
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-		return PTR_ERR(ir->rst);
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-	ret = reset_control_deassert(ir->rst);
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-	if (ret)
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-		return ret;
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+	/* Reset */
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+	if (quirks->has_reset) {
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+		ir->rst = devm_reset_control_get_exclusive(dev, NULL);
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+		if (IS_ERR(ir->rst))
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+			return PTR_ERR(ir->rst);
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+		ret = reset_control_deassert(ir->rst);
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+		if (ret)
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+			return ret;
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+	}
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 	ret = clk_set_rate(ir->clk, b_clk_freq);
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 	if (ret) {
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@@ -206,7 +220,6 @@
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 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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 	ir->base = devm_ioremap_resource(dev, res);
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 	if (IS_ERR(ir->base)) {
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-		dev_err(dev, "failed to map registers\n");
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 		ret = PTR_ERR(ir->base);
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 		goto exit_clkdisable_clk;
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 	}
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@@ -230,8 +243,8 @@
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 	ir->rc->dev.parent = dev;
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 	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
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 	/* Frequency after IR internal divider with sample period in ns */
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-	ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64));
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-	ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
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+	ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
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+	ir->rc->timeout = MS_TO_US(SUNXI_IR_TIMEOUT);
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 	ir->rc->driver_name = SUNXI_IR_DEV;
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249
 
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 	ret = rc_register_device(ir->rc);
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@@ -245,7 +258,6 @@
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 	/* IRQ */
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 	ir->irq = platform_get_irq(pdev, 0);
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 	if (ir->irq < 0) {
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-		dev_err(dev, "no irq resource\n");
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 		ret = ir->irq;
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 		goto exit_free_dev;
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 	}
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@@ -318,10 +330,35 @@
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 	return 0;
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 }
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332
 
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+static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
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+	.has_reset = false,
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+	.fifo_size = 16,
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+};
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+
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+static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
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+	.has_reset = false,
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+	.fifo_size = 64,
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+};
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+
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+static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
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+	.has_reset = true,
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+	.fifo_size = 64,
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+};
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+
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 static const struct of_device_id sunxi_ir_match[] = {
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-	{ .compatible = "allwinner,sun4i-a10-ir", },
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-	{ .compatible = "allwinner,sun5i-a13-ir", },
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-	{},
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+	{
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+		.compatible = "allwinner,sun4i-a10-ir",
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+		.data = &sun4i_a10_ir_quirks,
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+	},
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+	{
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+		.compatible = "allwinner,sun5i-a13-ir",
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+		.data = &sun5i_a13_ir_quirks,
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+	},
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+	{
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+		.compatible = "allwinner,sun6i-a31-ir",
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+		.data = &sun6i_a31_ir_quirks,
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+	},
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+	{}
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 };
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 MODULE_DEVICE_TABLE(of, sunxi_ir_match);
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