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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (c) 2014 Linaro Ltd. |
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3 | 4 | * Copyright (c) 2014 Hisilicon Limited. |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify it |
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6 | | - * under the terms and conditions of the GNU General Public License, |
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7 | | - * version 2, as published by the Free Software Foundation. |
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8 | 5 | */ |
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9 | 6 | |
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10 | 7 | #include <linux/clk.h> |
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.. | .. |
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40 | 37 | #define INT_CLR_RCV BIT(16) |
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41 | 38 | #define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17)) |
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42 | 39 | |
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43 | | -#define IR_CLK 0x48 |
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44 | 40 | #define IR_CLK_ENABLE BIT(4) |
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45 | 41 | #define IR_CLK_RESET BIT(5) |
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| 42 | + |
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| 43 | +/* IR_ENABLE register bits */ |
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| 44 | +#define IR_ENABLE_EN BIT(0) |
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| 45 | +#define IR_ENABLE_EN_EXTRA BIT(8) |
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46 | 46 | |
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47 | 47 | #define IR_CFG_WIDTH_MASK 0xffff |
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48 | 48 | #define IR_CFG_WIDTH_SHIFT 16 |
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.. | .. |
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61 | 61 | |
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62 | 62 | #define IR_HIX5HD2_NAME "hix5hd2-ir" |
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63 | 63 | |
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| 64 | +/* Need to set extra bit for enabling IR */ |
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| 65 | +#define HIX5HD2_FLAG_EXTRA_ENABLE BIT(0) |
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| 66 | + |
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| 67 | +struct hix5hd2_soc_data { |
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| 68 | + u32 clk_reg; |
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| 69 | + u32 flags; |
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| 70 | +}; |
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| 71 | + |
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| 72 | +static const struct hix5hd2_soc_data hix5hd2_data = { |
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| 73 | + .clk_reg = 0x48, |
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| 74 | +}; |
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| 75 | + |
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| 76 | +static const struct hix5hd2_soc_data hi3796cv300_data = { |
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| 77 | + .clk_reg = 0x60, |
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| 78 | + .flags = HIX5HD2_FLAG_EXTRA_ENABLE, |
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| 79 | +}; |
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| 80 | + |
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64 | 81 | struct hix5hd2_ir_priv { |
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65 | 82 | int irq; |
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66 | 83 | void __iomem *base; |
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.. | .. |
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69 | 86 | struct regmap *regmap; |
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70 | 87 | struct clk *clock; |
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71 | 88 | unsigned long rate; |
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| 89 | + const struct hix5hd2_soc_data *socdata; |
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72 | 90 | }; |
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73 | 91 | |
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74 | | -static int hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on) |
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| 92 | +static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on) |
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75 | 93 | { |
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| 94 | + u32 clk_reg = dev->socdata->clk_reg; |
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76 | 95 | u32 val; |
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77 | 96 | int ret = 0; |
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78 | 97 | |
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79 | 98 | if (dev->regmap) { |
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80 | | - regmap_read(dev->regmap, IR_CLK, &val); |
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| 99 | + regmap_read(dev->regmap, clk_reg, &val); |
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81 | 100 | if (on) { |
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82 | 101 | val &= ~IR_CLK_RESET; |
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83 | 102 | val |= IR_CLK_ENABLE; |
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.. | .. |
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85 | 104 | val &= ~IR_CLK_ENABLE; |
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86 | 105 | val |= IR_CLK_RESET; |
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87 | 106 | } |
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88 | | - regmap_write(dev->regmap, IR_CLK, val); |
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| 107 | + regmap_write(dev->regmap, clk_reg, val); |
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89 | 108 | } else { |
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90 | 109 | if (on) |
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91 | 110 | ret = clk_prepare_enable(dev->clock); |
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.. | .. |
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95 | 114 | return ret; |
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96 | 115 | } |
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97 | 116 | |
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| 117 | +static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv) |
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| 118 | +{ |
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| 119 | + u32 val = IR_ENABLE_EN; |
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| 120 | + |
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| 121 | + if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE) |
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| 122 | + val |= IR_ENABLE_EN_EXTRA; |
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| 123 | + |
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| 124 | + writel_relaxed(val, priv->base + IR_ENABLE); |
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| 125 | +} |
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| 126 | + |
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98 | 127 | static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv) |
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99 | 128 | { |
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100 | 129 | int timeout = 10000; |
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101 | 130 | u32 val, rate; |
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102 | 131 | |
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103 | | - writel_relaxed(0x01, priv->base + IR_ENABLE); |
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| 132 | + hix5hd2_ir_enable(priv); |
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| 133 | + |
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104 | 134 | while (readl_relaxed(priv->base + IR_BUSY)) { |
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105 | 135 | if (timeout--) { |
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106 | 136 | udelay(1); |
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.. | .. |
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131 | 161 | struct hix5hd2_ir_priv *priv = rdev->priv; |
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132 | 162 | int ret; |
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133 | 163 | |
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134 | | - ret = hix5hd2_ir_enable(priv, true); |
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| 164 | + ret = hix5hd2_ir_clk_enable(priv, true); |
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135 | 165 | if (ret) |
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136 | 166 | return ret; |
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137 | 167 | |
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138 | 168 | ret = hix5hd2_ir_config(priv); |
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139 | 169 | if (ret) { |
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140 | | - hix5hd2_ir_enable(priv, false); |
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| 170 | + hix5hd2_ir_clk_enable(priv, false); |
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141 | 171 | return ret; |
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142 | 172 | } |
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143 | 173 | return 0; |
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.. | .. |
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147 | 177 | { |
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148 | 178 | struct hix5hd2_ir_priv *priv = rdev->priv; |
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149 | 179 | |
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150 | | - hix5hd2_ir_enable(priv, false); |
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| 180 | + hix5hd2_ir_clk_enable(priv, false); |
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151 | 181 | } |
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152 | 182 | |
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153 | 183 | static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data) |
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.. | .. |
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175 | 205 | } |
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176 | 206 | |
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177 | 207 | if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) { |
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178 | | - DEFINE_IR_RAW_EVENT(ev); |
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| 208 | + struct ir_raw_event ev = {}; |
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179 | 209 | |
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180 | 210 | symb_num = readl_relaxed(priv->base + IR_DATAH); |
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181 | 211 | for (i = 0; i < symb_num; i++) { |
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.. | .. |
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184 | 214 | data_h = ((symb_val >> 16) & 0xffff) * 10; |
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185 | 215 | symb_time = (data_l + data_h) / 10; |
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186 | 216 | |
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187 | | - ev.duration = US_TO_NS(data_l); |
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| 217 | + ev.duration = data_l; |
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188 | 218 | ev.pulse = true; |
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189 | 219 | ir_raw_event_store(priv->rdev, &ev); |
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190 | 220 | |
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191 | 221 | if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) { |
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192 | | - ev.duration = US_TO_NS(data_h); |
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| 222 | + ev.duration = data_h; |
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193 | 223 | ev.pulse = false; |
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194 | 224 | ir_raw_event_store(priv->rdev, &ev); |
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195 | 225 | } else { |
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.. | .. |
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208 | 238 | return IRQ_HANDLED; |
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209 | 239 | } |
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210 | 240 | |
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| 241 | +static const struct of_device_id hix5hd2_ir_table[] = { |
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| 242 | + { .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, }, |
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| 243 | + { .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, }, |
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| 244 | + {}, |
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| 245 | +}; |
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| 246 | +MODULE_DEVICE_TABLE(of, hix5hd2_ir_table); |
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| 247 | + |
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211 | 248 | static int hix5hd2_ir_probe(struct platform_device *pdev) |
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212 | 249 | { |
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213 | 250 | struct rc_dev *rdev; |
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.. | .. |
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215 | 252 | struct resource *res; |
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216 | 253 | struct hix5hd2_ir_priv *priv; |
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217 | 254 | struct device_node *node = pdev->dev.of_node; |
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| 255 | + const struct of_device_id *of_id; |
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218 | 256 | const char *map_name; |
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219 | 257 | int ret; |
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220 | 258 | |
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221 | 259 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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222 | 260 | if (!priv) |
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223 | 261 | return -ENOMEM; |
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| 262 | + |
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| 263 | + of_id = of_match_device(hix5hd2_ir_table, dev); |
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| 264 | + if (!of_id) { |
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| 265 | + dev_err(dev, "Unable to initialize IR data\n"); |
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| 266 | + return -ENODEV; |
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| 267 | + } |
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| 268 | + priv->socdata = of_id->data; |
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224 | 269 | |
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225 | 270 | priv->regmap = syscon_regmap_lookup_by_phandle(node, |
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226 | 271 | "hisilicon,power-syscon"); |
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.. | .. |
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235 | 280 | return PTR_ERR(priv->base); |
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236 | 281 | |
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237 | 282 | priv->irq = platform_get_irq(pdev, 0); |
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238 | | - if (priv->irq < 0) { |
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239 | | - dev_err(dev, "irq can not get\n"); |
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| 283 | + if (priv->irq < 0) |
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240 | 284 | return priv->irq; |
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241 | | - } |
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242 | 285 | |
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243 | 286 | rdev = rc_allocate_device(RC_DRIVER_IR_RAW); |
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244 | 287 | if (!rdev) |
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.. | .. |
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268 | 311 | rdev->input_id.vendor = 0x0001; |
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269 | 312 | rdev->input_id.product = 0x0001; |
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270 | 313 | rdev->input_id.version = 0x0100; |
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271 | | - rdev->rx_resolution = US_TO_NS(10); |
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272 | | - rdev->timeout = US_TO_NS(IR_CFG_SYMBOL_MAXWIDTH * 10); |
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| 314 | + rdev->rx_resolution = 10; |
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| 315 | + rdev->timeout = IR_CFG_SYMBOL_MAXWIDTH * 10; |
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273 | 316 | |
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274 | 317 | ret = rc_register_device(rdev); |
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275 | 318 | if (ret < 0) |
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.. | .. |
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314 | 357 | struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); |
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315 | 358 | |
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316 | 359 | clk_disable_unprepare(priv->clock); |
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317 | | - hix5hd2_ir_enable(priv, false); |
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| 360 | + hix5hd2_ir_clk_enable(priv, false); |
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318 | 361 | |
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319 | 362 | return 0; |
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320 | 363 | } |
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.. | .. |
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324 | 367 | struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); |
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325 | 368 | int ret; |
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326 | 369 | |
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327 | | - ret = hix5hd2_ir_enable(priv, true); |
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| 370 | + ret = hix5hd2_ir_clk_enable(priv, true); |
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328 | 371 | if (ret) |
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329 | 372 | return ret; |
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330 | 373 | |
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331 | 374 | ret = clk_prepare_enable(priv->clock); |
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332 | 375 | if (ret) { |
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333 | | - hix5hd2_ir_enable(priv, false); |
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| 376 | + hix5hd2_ir_clk_enable(priv, false); |
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334 | 377 | return ret; |
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335 | 378 | } |
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336 | 379 | |
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337 | | - writel_relaxed(0x01, priv->base + IR_ENABLE); |
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| 380 | + hix5hd2_ir_enable(priv); |
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| 381 | + |
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338 | 382 | writel_relaxed(0x00, priv->base + IR_INTM); |
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339 | 383 | writel_relaxed(0xff, priv->base + IR_INTC); |
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340 | 384 | writel_relaxed(0x01, priv->base + IR_START); |
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.. | .. |
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345 | 389 | |
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346 | 390 | static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend, |
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347 | 391 | hix5hd2_ir_resume); |
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348 | | - |
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349 | | -static const struct of_device_id hix5hd2_ir_table[] = { |
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350 | | - { .compatible = "hisilicon,hix5hd2-ir", }, |
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351 | | - {}, |
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352 | | -}; |
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353 | | -MODULE_DEVICE_TABLE(of, hix5hd2_ir_table); |
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354 | 392 | |
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355 | 393 | static struct platform_driver hix5hd2_ir_driver = { |
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356 | 394 | .driver = { |
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