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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/media/platform/s3c-camif/camif-regs.h
....@@ -1,16 +1,15 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Register definition file for s3c24xx/s3c64xx SoC CAMIF driver
34  *
45  * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
56  * Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
9
- * published by the Free Software Foundation.
107 */
118 
129 #ifndef CAMIF_REGS_H_
1310 #define CAMIF_REGS_H_
11
+
12
+#include <linux/bitops.h>
1413 
1514 #include "camif-core.h"
1615 #include <media/drv-intf/s3c_camif.h>
....@@ -22,7 +21,7 @@
2221 
2322 /* Camera input format */
2423 #define S3C_CAMIF_REG_CISRCFMT			0x00
25
-#define  CISRCFMT_ITU601_8BIT			(1 << 31)
24
+#define  CISRCFMT_ITU601_8BIT			BIT(31)
2625 #define  CISRCFMT_ITU656_8BIT			(0 << 31)
2726 #define  CISRCFMT_ORDER422_YCBYCR		(0 << 14)
2827 #define  CISRCFMT_ORDER422_YCRYCB		(1 << 14)
....@@ -33,14 +32,14 @@
3332 
3433 /* Window offset */
3534 #define S3C_CAMIF_REG_CIWDOFST			0x04
36
-#define  CIWDOFST_WINOFSEN			(1 << 31)
37
-#define  CIWDOFST_CLROVCOFIY			(1 << 30)
38
-#define  CIWDOFST_CLROVRLB_PR			(1 << 28)
39
-/* #define  CIWDOFST_CLROVPRFIY			(1 << 27) */
40
-#define  CIWDOFST_CLROVCOFICB			(1 << 15)
41
-#define  CIWDOFST_CLROVCOFICR			(1 << 14)
42
-#define  CIWDOFST_CLROVPRFICB			(1 << 13)
43
-#define  CIWDOFST_CLROVPRFICR			(1 << 12)
35
+#define  CIWDOFST_WINOFSEN			BIT(31)
36
+#define  CIWDOFST_CLROVCOFIY			BIT(30)
37
+#define  CIWDOFST_CLROVRLB_PR			BIT(28)
38
+/* #define  CIWDOFST_CLROVPRFIY			BIT(27) */
39
+#define  CIWDOFST_CLROVCOFICB			BIT(15)
40
+#define  CIWDOFST_CLROVCOFICR			BIT(14)
41
+#define  CIWDOFST_CLROVPRFICB			BIT(13)
42
+#define  CIWDOFST_CLROVPRFICR			BIT(12)
4443 #define  CIWDOFST_OFST_MASK			(0x7ff << 16 | 0x7ff)
4544 
4645 /* Window offset 2 */
....@@ -49,24 +48,24 @@
4948 
5049 /* Global control */
5150 #define S3C_CAMIF_REG_CIGCTRL			0x08
52
-#define  CIGCTRL_SWRST				(1 << 31)
53
-#define  CIGCTRL_CAMRST				(1 << 30)
51
+#define  CIGCTRL_SWRST				BIT(31)
52
+#define  CIGCTRL_CAMRST				BIT(30)
5453 #define  CIGCTRL_TESTPATTERN_NORMAL		(0 << 27)
5554 #define  CIGCTRL_TESTPATTERN_COLOR_BAR		(1 << 27)
5655 #define  CIGCTRL_TESTPATTERN_HOR_INC		(2 << 27)
5756 #define  CIGCTRL_TESTPATTERN_VER_INC		(3 << 27)
5857 #define  CIGCTRL_TESTPATTERN_MASK		(3 << 27)
59
-#define  CIGCTRL_INVPOLPCLK			(1 << 26)
60
-#define  CIGCTRL_INVPOLVSYNC			(1 << 25)
61
-#define  CIGCTRL_INVPOLHREF			(1 << 24)
62
-#define  CIGCTRL_IRQ_OVFEN			(1 << 22)
63
-#define  CIGCTRL_HREF_MASK			(1 << 21)
64
-#define  CIGCTRL_IRQ_LEVEL			(1 << 20)
58
+#define  CIGCTRL_INVPOLPCLK			BIT(26)
59
+#define  CIGCTRL_INVPOLVSYNC			BIT(25)
60
+#define  CIGCTRL_INVPOLHREF			BIT(24)
61
+#define  CIGCTRL_IRQ_OVFEN			BIT(22)
62
+#define  CIGCTRL_HREF_MASK			BIT(21)
63
+#define  CIGCTRL_IRQ_LEVEL			BIT(20)
6564 /* IRQ_CLR_C, IRQ_CLR_P */
66
-#define  CIGCTRL_IRQ_CLR(id)			(1 << (19 - (id)))
67
-#define  CIGCTRL_FIELDMODE			(1 << 2)
68
-#define  CIGCTRL_INVPOLFIELD			(1 << 1)
69
-#define  CIGCTRL_CAM_INTERLACE			(1 << 0)
65
+#define  CIGCTRL_IRQ_CLR(id)			BIT(19 - (id))
66
+#define  CIGCTRL_FIELDMODE			BIT(2)
67
+#define  CIGCTRL_INVPOLFIELD			BIT(1)
68
+#define  CIGCTRL_CAM_INTERLACE			BIT(0)
7069 
7170 /* Y DMA output frame start address. n = 0..3. */
7271 #define S3C_CAMIF_REG_CIYSA(id, n)		(0x18 + (id) * 0x54 + (n) * 4)
....@@ -77,8 +76,8 @@
7776 
7877 /* CICOTRGFMT, CIPRTRGFMT - Target format */
7978 #define S3C_CAMIF_REG_CITRGFMT(id, _offs)	(0x48 + (id) * (0x34 + (_offs)))
80
-#define  CITRGFMT_IN422				(1 << 31) /* only for s3c24xx */
81
-#define  CITRGFMT_OUT422			(1 << 30) /* only for s3c24xx */
79
+#define  CITRGFMT_IN422				BIT(31) /* only for s3c24xx */
80
+#define  CITRGFMT_OUT422			BIT(30) /* only for s3c24xx */
8281 #define  CITRGFMT_OUTFORMAT_YCBCR420		(0 << 29) /* only for s3c6410 */
8382 #define  CITRGFMT_OUTFORMAT_YCBCR422		(1 << 29) /* only for s3c6410 */
8483 #define  CITRGFMT_OUTFORMAT_YCBCR422I		(2 << 29) /* only for s3c6410 */
....@@ -91,7 +90,7 @@
9190 #define  CITRGFMT_FLIP_180			(3 << 14)
9291 #define  CITRGFMT_FLIP_MASK			(3 << 14)
9392 /* Preview path only */
94
-#define  CITRGFMT_ROT90_PR			(1 << 13)
93
+#define  CITRGFMT_ROT90_PR			BIT(13)
9594 #define  CITRGFMT_TARGETVSIZE(x)		((x) << 0)
9695 #define  CITRGFMT_TARGETSIZE_MASK		((0x1fff << 16) | 0x1fff)
9796 
....@@ -105,7 +104,7 @@
105104 #define  CICTRL_RGBBURST2(x)			((x) << 14)
106105 #define  CICTRL_CBURST1(x)			((x) << 9)
107106 #define  CICTRL_CBURST2(x)			((x) << 4)
108
-#define  CICTRL_LASTIRQ_ENABLE			(1 << 2)
107
+#define  CICTRL_LASTIRQ_ENABLE			BIT(2)
109108 #define  CICTRL_ORDER422_MASK			(3 << 0)
110109 
111110 /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
....@@ -116,22 +115,22 @@
116115 
117116 /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
118117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs)	(0x58 + (id) * (0x34 + (_offs)))
119
-#define  CISCCTRL_SCALERBYPASS			(1 << 31)
118
+#define  CISCCTRL_SCALERBYPASS			BIT(31)
120119 /* s3c244x preview path only, s3c64xx both */
121
-#define  CIPRSCCTRL_SAMPLE			(1 << 31)
120
+#define  CIPRSCCTRL_SAMPLE			BIT(31)
122121 /* 0 - 16-bit RGB, 1 - 24-bit RGB */
123
-#define  CIPRSCCTRL_RGB_FORMAT_24BIT		(1 << 30) /* only for s3c244x */
124
-#define  CIPRSCCTRL_SCALEUP_H			(1 << 29) /* only for s3c244x */
125
-#define  CIPRSCCTRL_SCALEUP_V			(1 << 28) /* only for s3c244x */
122
+#define  CIPRSCCTRL_RGB_FORMAT_24BIT		BIT(30) /* only for s3c244x */
123
+#define  CIPRSCCTRL_SCALEUP_H			BIT(29) /* only for s3c244x */
124
+#define  CIPRSCCTRL_SCALEUP_V			BIT(28) /* only for s3c244x */
126125 /* s3c64xx */
127
-#define  CISCCTRL_SCALEUP_H			(1 << 30)
128
-#define  CISCCTRL_SCALEUP_V			(1 << 29)
126
+#define  CISCCTRL_SCALEUP_H			BIT(30)
127
+#define  CISCCTRL_SCALEUP_V			BIT(29)
129128 #define  CISCCTRL_SCALEUP_MASK			(0x3 << 29)
130
-#define  CISCCTRL_CSCR2Y_WIDE			(1 << 28)
131
-#define  CISCCTRL_CSCY2R_WIDE			(1 << 27)
132
-#define  CISCCTRL_LCDPATHEN_FIFO		(1 << 26)
133
-#define  CISCCTRL_INTERLACE			(1 << 25)
134
-#define  CISCCTRL_SCALERSTART			(1 << 15)
129
+#define  CISCCTRL_CSCR2Y_WIDE			BIT(28)
130
+#define  CISCCTRL_CSCY2R_WIDE			BIT(27)
131
+#define  CISCCTRL_LCDPATHEN_FIFO		BIT(26)
132
+#define  CISCCTRL_INTERLACE			BIT(25)
133
+#define  CISCCTRL_SCALERSTART			BIT(15)
135134 #define  CISCCTRL_INRGB_FMT_RGB565		(0 << 13)
136135 #define  CISCCTRL_INRGB_FMT_RGB666		(1 << 13)
137136 #define  CISCCTRL_INRGB_FMT_RGB888		(2 << 13)
....@@ -140,8 +139,8 @@
140139 #define  CISCCTRL_OUTRGB_FMT_RGB666		(1 << 11)
141140 #define  CISCCTRL_OUTRGB_FMT_RGB888		(2 << 11)
142141 #define  CISCCTRL_OUTRGB_FMT_MASK		(3 << 11)
143
-#define  CISCCTRL_EXTRGB_EXTENSION		(1 << 10)
144
-#define  CISCCTRL_ONE2ONE			(1 << 9)
142
+#define  CISCCTRL_EXTRGB_EXTENSION		BIT(10)
143
+#define  CISCCTRL_ONE2ONE			BIT(9)
145144 #define  CISCCTRL_MAIN_RATIO_MASK		(0x1ff << 16 | 0x1ff)
146145 
147146 /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */
....@@ -150,38 +149,38 @@
150149 
151150 /* Codec (id = 0) or preview (id = 1) path status. */
152151 #define S3C_CAMIF_REG_CISTATUS(id, _offs)	(0x64 + (id) * (0x34 + (_offs)))
153
-#define  CISTATUS_OVFIY_STATUS			(1 << 31)
154
-#define  CISTATUS_OVFICB_STATUS			(1 << 30)
155
-#define  CISTATUS_OVFICR_STATUS			(1 << 29)
152
+#define  CISTATUS_OVFIY_STATUS			BIT(31)
153
+#define  CISTATUS_OVFICB_STATUS			BIT(30)
154
+#define  CISTATUS_OVFICR_STATUS			BIT(29)
156155 #define  CISTATUS_OVF_MASK			(0x7 << 29)
157156 #define  CIPRSTATUS_OVF_MASK			(0x3 << 30)
158
-#define  CISTATUS_VSYNC_STATUS			(1 << 28)
157
+#define  CISTATUS_VSYNC_STATUS			BIT(28)
159158 #define  CISTATUS_FRAMECNT_MASK			(3 << 26)
160159 #define  CISTATUS_FRAMECNT(__reg)		(((__reg) >> 26) & 0x3)
161
-#define  CISTATUS_WINOFSTEN_STATUS		(1 << 25)
162
-#define  CISTATUS_IMGCPTEN_STATUS		(1 << 22)
163
-#define  CISTATUS_IMGCPTENSC_STATUS		(1 << 21)
164
-#define  CISTATUS_VSYNC_A_STATUS		(1 << 20)
165
-#define  CISTATUS_FRAMEEND_STATUS		(1 << 19) /* 17 on s3c64xx */
160
+#define  CISTATUS_WINOFSTEN_STATUS		BIT(25)
161
+#define  CISTATUS_IMGCPTEN_STATUS		BIT(22)
162
+#define  CISTATUS_IMGCPTENSC_STATUS		BIT(21)
163
+#define  CISTATUS_VSYNC_A_STATUS		BIT(20)
164
+#define  CISTATUS_FRAMEEND_STATUS		BIT(19) /* 17 on s3c64xx */
166165 
167166 /* Image capture enable */
168167 #define S3C_CAMIF_REG_CIIMGCPT(_offs)		(0xa0 + (_offs))
169
-#define  CIIMGCPT_IMGCPTEN			(1 << 31)
170
-#define  CIIMGCPT_IMGCPTEN_SC(id)		(1 << (30 - (id)))
168
+#define  CIIMGCPT_IMGCPTEN			BIT(31)
169
+#define  CIIMGCPT_IMGCPTEN_SC(id)		BIT(30 - (id))
171170 /* Frame control: 1 - one-shot, 0 - free run */
172
-#define  CIIMGCPT_CPT_FREN_ENABLE(id)		(1 << (25 - (id)))
171
+#define  CIIMGCPT_CPT_FREN_ENABLE(id)		BIT(25 - (id))
173172 #define  CIIMGCPT_CPT_FRMOD_ENABLE		(0 << 18)
174
-#define  CIIMGCPT_CPT_FRMOD_CNT			(1 << 18)
173
+#define  CIIMGCPT_CPT_FRMOD_CNT			BIT(18)
175174 
176175 /* Capture sequence */
177176 #define S3C_CAMIF_REG_CICPTSEQ			0xc4
178177 
179178 /* Image effects */
180179 #define S3C_CAMIF_REG_CIIMGEFF(_offs)		(0xb0 + (_offs))
181
-#define  CIIMGEFF_IE_ENABLE(id)			(1 << (30 + (id)))
180
+#define  CIIMGEFF_IE_ENABLE(id)			BIT(30 + (id))
182181 #define  CIIMGEFF_IE_ENABLE_MASK		(3 << 30)
183182 /* Image effect: 1 - after scaler, 0 - before scaler */
184
-#define  CIIMGEFF_IE_AFTER_SC			(1 << 29)
183
+#define  CIIMGEFF_IE_AFTER_SC			BIT(29)
185184 #define  CIIMGEFF_FIN_MASK			(7 << 26)
186185 #define  CIIMGEFF_FIN_BYPASS			(0 << 26)
187186 #define  CIIMGEFF_FIN_ARBITRARY			(1 << 26)
....@@ -210,8 +209,8 @@
210209 
211210 /* Real input DMA data size. n = 0 - codec, 1 - preview. */
212211 #define S3C_CAMIF_REG_MSWIDTH(id)		(0xf8 + (id) * 0x2c)
213
-#define  AUTOLOAD_ENABLE			(1 << 31)
214
-#define  ADDR_CH_DIS				(1 << 30)
212
+#define  AUTOLOAD_ENABLE			BIT(31)
213
+#define  ADDR_CH_DIS				BIT(30)
215214 #define  MSHEIGHT(x)				(((x) & 0x3ff) << 16)
216215 #define  MSWIDTH(x)				((x) & 0x3ff)
217216 
....@@ -222,12 +221,12 @@
222221 #define  MSCTRL_ORDER422_M_CBYCRY		(2 << 4)
223222 #define  MSCTRL_ORDER422_M_CRYCBY		(3 << 4)
224223 /* 0 - camera, 1 - DMA */
225
-#define  MSCTRL_SEL_DMA_CAM			(1 << 3)
224
+#define  MSCTRL_SEL_DMA_CAM			BIT(3)
226225 #define  MSCTRL_INFORMAT_M_YCBCR420		(0 << 1)
227226 #define  MSCTRL_INFORMAT_M_YCBCR422		(1 << 1)
228227 #define  MSCTRL_INFORMAT_M_YCBCR422I		(2 << 1)
229228 #define  MSCTRL_INFORMAT_M_RGB			(3 << 1)
230
-#define  MSCTRL_ENVID_M				(1 << 0)
229
+#define  MSCTRL_ENVID_M				BIT(0)
231230 
232231 /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */
233232 #define S3C_CAMIF_REG_CISSY(id)			(0x12c + (id) * 0x0c)