add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/media/platform/rockchip/ispp/hw.c
..
..
@@ -14,7 +14,7 @@
14
14
 #include <linux/pinctrl/consumer.h>
15
15
 #include <linux/pm_runtime.h>
16
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 #include <linux/reset.h>
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-#include <media/videobuf2-dma-contig.h>
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+#include <media/videobuf2-cma-sg.h>
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 #include <media/videobuf2-dma-sg.h>
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 #include <soc/rockchip/rockchip_iommu.h>
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20
 
..
..
@@ -43,6 +43,7 @@
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43
 {
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 	writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
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 	udelay(10);
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+	writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
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 	if (hw->reset) {
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48
 		reset_control_assert(hw->reset);
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 		udelay(20);
..
..
@@ -55,43 +56,63 @@
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 		rockchip_iommu_disable(hw->dev);
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 		rockchip_iommu_enable(hw->dev);
57
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 	}
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-
59
-	writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
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-	writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
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-	writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
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-	writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
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-	writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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-	writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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-	writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
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+	if (hw->ispp_ver == ISPP_V10) {
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+		writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
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+		writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
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+		writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
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+		writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
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+		writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+		writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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+		writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
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 		FBCH_EMPTY_TNR | FBCD_DEC_ERR_NR | FBCD_DEC_ERR_TNR |
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 		BUS_ERR_NR | BUS_ERR_TNR | SCL2_INT | SCL1_INT |
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 		SCL0_INT | FEC_INT | ORB_INT | SHP_INT | NR_INT | TNR_INT,
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 		hw->base_addr + RKISPP_CTRL_INT_MSK);
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-	writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+		writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+	} else if (hw->ispp_ver == ISPP_V20) {
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+		writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+		writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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+		writel(FEC_INT, hw->base_addr + RKISPP_CTRL_INT_MSK);
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+		writel(GATE_DIS_FEC, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+	}
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+
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 }
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80
 
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 /* using default value if reg no write for multi device */
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 static void default_sw_reg_flag(struct rkispp_device *dev)
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 {
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-	u32 reg[] = {
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-		RKISPP_TNR_CTRL,
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-		RKISPP_TNR_CORE_CTRL,
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-		RKISPP_NR_CTRL,
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-		RKISPP_NR_UVNR_CTRL_PARA,
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-		RKISPP_SHARP_CTRL,
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-		RKISPP_SHARP_CORE_CTRL,
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-		RKISPP_SCL0_CTRL,
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-		RKISPP_SCL1_CTRL,
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-		RKISPP_SCL2_CTRL,
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-		RKISPP_ORB_CORE_CTRL,
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-		RKISPP_FEC_CTRL,
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-		RKISPP_FEC_CORE_CTRL
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-	};
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-	u32 i, *flag;
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+	if (dev->hw_dev->ispp_ver == ISPP_V10) {
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+		u32 reg[] = {
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+			RKISPP_TNR_CTRL,
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+			RKISPP_TNR_CORE_CTRL,
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+			RKISPP_NR_CTRL,
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+			RKISPP_NR_UVNR_CTRL_PARA,
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+			RKISPP_SHARP_CTRL,
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+			RKISPP_SHARP_CORE_CTRL,
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+			RKISPP_SCL0_CTRL,
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+			RKISPP_SCL1_CTRL,
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+			RKISPP_SCL2_CTRL,
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+			RKISPP_ORB_CORE_CTRL,
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+			RKISPP_FEC_CTRL,
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+			RKISPP_FEC_CORE_CTRL
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+		};
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+		u32 i, *flag;
91
100
 
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-	for (i = 0; i < ARRAY_SIZE(reg); i++) {
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-		flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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-		*flag = 0xffffffff;
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+		for (i = 0; i < ARRAY_SIZE(reg); i++) {
102
+			flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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+			*flag = 0xffffffff;
104
+		}
105
+	} else if (dev->hw_dev->ispp_ver == ISPP_V20) {
106
+		u32 reg[] = {
107
+			RKISPP_FEC_CTRL,
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+			RKISPP_FEC_CORE_CTRL
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+		};
110
+		u32 i, *flag;
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+
112
+		for (i = 0; i < ARRAY_SIZE(reg); i++) {
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+			flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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+			*flag = 0xffffffff;
115
+		}
95
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 	}
96
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 }
97
118
 
..
..
@@ -124,14 +145,18 @@
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 static int enable_sys_clk(struct rkispp_hw_dev *dev)
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 {
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 	struct rkispp_device *ispp = dev->ispp[dev->cur_dev_id];
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-	u32 w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
128
-	int i, ret = -EINVAL;
148
+	int w, i, ret = -EINVAL;
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149
 
130
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 	for (i = 0; i < dev->clks_num; i++) {
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 		ret = clk_prepare_enable(dev->clks[i]);
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 		if (ret < 0)
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 			goto err;
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 	}
155
+
156
+	if (!ispp)
157
+		return ret;
158
+
159
+	w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
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160
 
136
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 	for (i = 0; i < dev->clk_rate_tbl_num; i++)
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 		if (w <= dev->clk_rate_tbl[i].refer_data)
..
..
@@ -181,6 +206,12 @@
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 	"hclk_ispp",
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 };
183
208
 
209
+static const char * const rk3588_ispp_clks[] = {
210
+	"clk_ispp",
211
+	"aclk_ispp",
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+	"hclk_ispp",
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+};
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+
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 static const struct ispp_clk_info rv1126_ispp_clk_rate[] = {
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 	{
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 		.clk_rate = 150,
..
..
@@ -200,8 +231,31 @@
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 	}
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 };
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233
 
234
+static const struct ispp_clk_info rk3588_ispp_clk_rate[] = {
235
+	{
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+		.clk_rate = 300,
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+		.refer_data = 1920, //width
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+	}, {
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+		.clk_rate = 400,
240
+		.refer_data = 2688,
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+	}, {
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+		.clk_rate = 500,
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+		.refer_data = 3072,
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+	}, {
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+		.clk_rate = 600,
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+		.refer_data = 3840,
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+	}, {
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+		.clk_rate = 702,
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+		.refer_data = 4672,
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+	}
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+};
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+
203
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 static struct irqs_data rv1126_ispp_irqs[] = {
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 	{"ispp_irq", irq_hdl},
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+	{"fec_irq", irq_hdl},
256
+};
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+
258
+static struct irqs_data rk3588_ispp_irqs[] = {
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 	{"fec_irq", irq_hdl},
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 };
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261
 
..
..
@@ -215,10 +269,23 @@
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 	.ispp_ver = ISPP_V10,
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270
 };
217
271
 
272
+static const struct ispp_match_data rk3588_ispp_match_data = {
273
+	.clks = rk3588_ispp_clks,
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+	.clks_num = ARRAY_SIZE(rk3588_ispp_clks),
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+	.clk_rate_tbl = rk3588_ispp_clk_rate,
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+	.clk_rate_tbl_num = ARRAY_SIZE(rk3588_ispp_clk_rate),
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+	.irqs = rk3588_ispp_irqs,
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+	.num_irqs = ARRAY_SIZE(rk3588_ispp_irqs),
279
+	.ispp_ver = ISPP_V20,
280
+};
281
+
218
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 static const struct of_device_id rkispp_hw_of_match[] = {
219
283
 	{
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 		.compatible = "rockchip,rv1126-rkispp",
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 		.data = &rv1126_ispp_match_data,
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+	}, {
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+		.compatible = "rockchip,rk3588-rkispp",
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+		.data = &rk3588_ispp_match_data,
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 	},
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 	{},
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 };
..
..
@@ -328,10 +395,13 @@
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 	atomic_set(&hw_dev->refcnt, 0);
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 	INIT_LIST_HEAD(&hw_dev->list);
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 	hw_dev->is_idle = true;
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-	hw_dev->is_single = false;
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+	hw_dev->is_single = true;
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+	/* for frame end reset and config reg */
400
+	if (hw_dev->ispp_ver == ISPP_V10)
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+		hw_dev->is_single = false;
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402
 	hw_dev->is_fec_ext = false;
333
403
 	hw_dev->is_dma_contig = true;
334
-	hw_dev->is_dma_sg_ops = false;
404
+	hw_dev->is_dma_sg_ops = true;
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405
 	hw_dev->is_shutdown = false;
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406
 	hw_dev->is_first = true;
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407
 	hw_dev->is_mmu = is_iommu_enable(dev);
..
..
@@ -340,19 +410,10 @@
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 		is_mem_reserved = false;
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 		if (!hw_dev->is_mmu)
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 			dev_info(dev, "No reserved memory region. default cma area!\n");
343
-		else
344
-			hw_dev->is_dma_contig = false;
345
413
 	}
346
-	if (is_mem_reserved) {
347
-		/* reserved memory using rdma_sg */
348
-		hw_dev->mem_ops = &vb2_rdma_sg_memops;
349
-		hw_dev->is_dma_sg_ops = true;
350
-	} else if (hw_dev->is_mmu) {
351
-		hw_dev->mem_ops = &vb2_dma_sg_memops;
352
-		hw_dev->is_dma_sg_ops = true;
353
-	} else {
354
-		hw_dev->mem_ops = &vb2_dma_contig_memops;
355
-	}
414
+	if (hw_dev->is_mmu && !is_mem_reserved)
415
+		hw_dev->is_dma_contig = false;
416
+	hw_dev->mem_ops = &vb2_cma_sg_memops;
356
417
 
357
418
 	rkispp_register_fec(hw_dev);
358
419
 	pm_runtime_enable(&pdev->dev);
..
..
@@ -380,6 +441,7 @@
380
441
 	if (pm_runtime_active(&pdev->dev)) {
381
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 		writel(0, hw_dev->base_addr + RKISPP_CTRL_INT_MSK);
382
443
 		writel(GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
444
+		writel(~GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
383
445
 	}
384
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 	dev_info(&pdev->dev, "%s\n", __func__);
385
447
 }
..
..
@@ -414,8 +476,6 @@
414
476
 }
415
477
 
416
478
 static const struct dev_pm_ops rkispp_hw_pm_ops = {
417
-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
418
-				pm_runtime_force_resume)
419
479
 	SET_RUNTIME_PM_OPS(rkispp_runtime_suspend,
420
480
 			   rkispp_runtime_resume, NULL)
421
481
 };