forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/media/platform/rockchip/isp/regs.h
....@@ -36,6 +36,7 @@
3636 #define _RKISP_REGS_H
3737 #include "dev.h"
3838 #include "regs_v2x.h"
39
+#include "regs_v3x.h"
3940 
4041 #define CIF_ISP_PACK_4BYTE(a, b, c, d)	\
4142 	(((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
....@@ -181,7 +182,8 @@
181182 #define MI_CTRL_SP_OUTPUT_YUV444		(3 << 28)
182183 #define MI_CTRL_SP_OUTPUT_RGB565		(4 << 28)
183184 #define MI_CTRL_SP_OUTPUT_RGB666		(5 << 28)
184
-#define MI_CTRL_SP_OUTPUT_RGB888		(6 << 28)
185
+#define MI_CTRL_SP_OUTPUT_ARGB888		(6 << 28)
186
+#define MI_CTRL_SP_OUTPUT_RGB888		(7 << 28)
185187 
186188 #define MI_CTRL_MP_FMT_MASK			GENMASK(23, 22)
187189 #define MI_CTRL_SP_FMT_MASK			GENMASK(30, 24)
....@@ -1642,17 +1644,33 @@
16421644 	writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr);
16431645 }
16441646 
1645
-static inline bool mp_is_stream_stopped(void __iomem *base)
1647
+static inline bool mp_is_stream_stopped(struct rkisp_stream *stream)
16461648 {
1647
-	int en;
1649
+	u32 en = CIF_MI_CTRL_SHD_MP_OUT_ENABLED | CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
1650
+	u32 reg = CIF_MI_CTRL_SHD;
1651
+	bool is_direct = true;
16481652 
1649
-	en = CIF_MI_CTRL_SHD_MP_IN_ENABLED | CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
1650
-	return !(readl(base + CIF_MI_CTRL_SHD) & en);
1653
+	if (!stream->ispdev->hw_dev->is_single) {
1654
+		is_direct = false;
1655
+		reg = CIF_MI_CTRL;
1656
+		en = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
1657
+	}
1658
+
1659
+	return !(rkisp_read(stream->ispdev, reg, is_direct) & en);
16511660 }
16521661 
1653
-static inline bool sp_is_stream_stopped(void __iomem *base)
1662
+static inline bool sp_is_stream_stopped(struct rkisp_stream *stream)
16541663 {
1655
-	return !(readl(base + CIF_MI_CTRL_SHD) & CIF_MI_CTRL_SHD_SP_IN_ENABLED);
1664
+	u32 reg = CIF_MI_CTRL_SHD, en = CIF_MI_CTRL_SHD_SP_OUT_ENABLED;
1665
+	bool is_direct = true;
1666
+
1667
+	if (!stream->ispdev->hw_dev->is_single) {
1668
+		is_direct = false;
1669
+		reg = CIF_MI_CTRL;
1670
+		en = CIF_MI_CTRL_SP_ENABLE;
1671
+	}
1672
+
1673
+	return !(rkisp_read(stream->ispdev, reg, is_direct) & en);
16561674 }
16571675 
16581676 static inline void isp_set_bits(void __iomem *addr, u32 bit_mask, u32 val)
....@@ -1734,7 +1752,9 @@
17341752 
17351753 static inline void mi_frame_end_int_enable(struct rkisp_stream *stream)
17361754 {
1737
-	void __iomem *base = stream->ispdev->base_addr;
1755
+	struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1756
+	void __iomem *base = !hw->is_unite ?
1757
+		hw->base_addr : hw->base_next_addr;
17381758 	void __iomem *addr = base + CIF_MI_IMSC;
17391759 
17401760 	writel(CIF_MI_FRAME(stream) | readl(addr), addr);
....@@ -1742,7 +1762,9 @@
17421762 
17431763 static inline void mi_frame_end_int_disable(struct rkisp_stream *stream)
17441764 {
1745
-	void __iomem *base = stream->ispdev->base_addr;
1765
+	struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1766
+	void __iomem *base = !hw->is_unite ?
1767
+		hw->base_addr : hw->base_next_addr;
17461768 	void __iomem *addr = base + CIF_MI_IMSC;
17471769 
17481770 	writel(~CIF_MI_FRAME(stream) & readl(addr), addr);
....@@ -1750,42 +1772,27 @@
17501772 
17511773 static inline void mi_frame_end_int_clear(struct rkisp_stream *stream)
17521774 {
1753
-	void __iomem *base = stream->ispdev->base_addr;
1775
+	struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1776
+	void __iomem *base = !hw->is_unite ?
1777
+		hw->base_addr : hw->base_next_addr;
17541778 	void __iomem *addr = base + CIF_MI_ICR;
17551779 
17561780 	writel(CIF_MI_FRAME(stream), addr);
17571781 }
17581782 
1759
-static inline void mp_set_chain_mode(void __iomem *base)
1783
+static inline void stream_data_path(struct rkisp_stream *stream)
17601784 {
1761
-	u32 dpcl = readl(base + CIF_VI_DPCL);
1785
+	struct rkisp_device *dev = stream->ispdev;
1786
+	bool is_unite = dev->hw_dev->is_unite;
1787
+	u32 dpcl = 0;
17621788 
1763
-	dpcl |= CIF_VI_DPCL_CHAN_MODE_MP;
1764
-	writel(dpcl, base + CIF_VI_DPCL);
1765
-}
1789
+	if (stream->id == RKISP_STREAM_MP)
1790
+		dpcl |= CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
1791
+	else if (stream->id == RKISP_STREAM_SP)
1792
+		dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
17661793 
1767
-static inline void sp_set_chain_mode(void __iomem *base)
1768
-{
1769
-	u32 dpcl = readl(base + CIF_VI_DPCL);
1770
-
1771
-	dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
1772
-	writel(dpcl, base + CIF_VI_DPCL);
1773
-}
1774
-
1775
-static inline void mp_set_data_path(void __iomem *base)
1776
-{
1777
-	u32 dpcl = readl(base + CIF_VI_DPCL);
1778
-
1779
-	dpcl = dpcl | CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
1780
-	writel(dpcl, base + CIF_VI_DPCL);
1781
-}
1782
-
1783
-static inline void sp_set_data_path(void __iomem *base)
1784
-{
1785
-	u32 dpcl = readl(base + CIF_VI_DPCL);
1786
-
1787
-	dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
1788
-	writel(dpcl, base + CIF_VI_DPCL);
1794
+	if (dpcl)
1795
+		rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite);
17891796 }
17901797 
17911798 static inline void mp_set_uv_swap(void __iomem *base)
....@@ -1906,13 +1913,17 @@
19061913 
19071914 static inline void force_cfg_update(struct rkisp_device *dev)
19081915 {
1909
-	void __iomem *base = dev->base_addr;
1910
-	u32 val = readl(base + CIF_MI_CTRL);
1916
+	u32 val = CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
1917
+	bool is_unite = dev->hw_dev->is_unite;
19111918 
1919
+	if (dev->isp_ver == ISP_V21) {
1920
+		val |= rkisp_read_reg_cache(dev, CIF_MI_CTRL);
1921
+		rkisp_write(dev, CIF_MI_CTRL, val, true);
1922
+	}
19121923 	dev->hw_dev->is_mi_update = true;
1913
-	val |= CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
1914
-	writel(val, base + CIF_MI_CTRL);
1915
-	writel(CIF_MI_INIT_SOFT_UPD, base + CIF_MI_INIT);
1924
+	rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite);
1925
+	val = CIF_MI_INIT_SOFT_UPD;
1926
+	rkisp_unite_write(dev, CIF_MI_INIT, val, true, is_unite);
19161927 }
19171928 
19181929 static inline void dmatx0_ctrl(void __iomem *base, u32 val)