forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/media/platform/rockchip/isp/regs.c
....@@ -33,6 +33,7 @@
3333  */
3434 
3535 #include <media/v4l2-common.h>
36
+#include <linux/rk-camera-module.h>
3637 #include "regs.h"
3738 
3839 void rkisp_disable_dcrop(struct rkisp_stream *stream, bool async)
....@@ -44,7 +45,8 @@
4445 
4546 	if (async && dev->hw_dev->is_single)
4647 		val = CIF_DUAL_CROP_GEN_CFG_UPD;
47
-	rkisp_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false);
48
+	rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl,
49
+			     mask, val, false, dev->hw_dev->is_unite);
4850 }
4951 
5052 void rkisp_config_dcrop(struct rkisp_stream *stream,
....@@ -52,16 +54,56 @@
5254 {
5355 	struct rkisp_device *dev = stream->ispdev;
5456 	u32 val = stream->config->dual_crop.yuvmode_mask;
57
+	bool is_unite = dev->hw_dev->is_unite;
58
+	struct v4l2_rect tmp = *rect;
59
+	u32 reg;
5560 
56
-	rkisp_write(dev, stream->config->dual_crop.h_offset, rect->left, false);
57
-	rkisp_write(dev, stream->config->dual_crop.v_offset, rect->top, false);
58
-	rkisp_write(dev, stream->config->dual_crop.h_size, rect->width, false);
59
-	rkisp_write(dev, stream->config->dual_crop.v_size, rect->height, false);
61
+	if (is_unite) {
62
+		tmp.width /= 2;
63
+		if (stream->id == RKISP_STREAM_FBC)
64
+			tmp.width &= ~0xf;
65
+	}
66
+	reg = stream->config->dual_crop.h_offset;
67
+	rkisp_write(dev, reg, tmp.left, false);
68
+	reg = stream->config->dual_crop.h_size;
69
+	rkisp_write(dev, reg, tmp.width, false);
70
+
71
+	reg = stream->config->dual_crop.v_offset;
72
+	rkisp_unite_write(dev, reg, tmp.top, false, is_unite);
73
+	reg = stream->config->dual_crop.v_size;
74
+	rkisp_unite_write(dev, reg, tmp.height, false, is_unite);
75
+
6076 	if (async && dev->hw_dev->is_single)
6177 		val |= CIF_DUAL_CROP_GEN_CFG_UPD;
6278 	else
6379 		val |= CIF_DUAL_CROP_CFG_UPD;
64
-	rkisp_set_bits(dev, stream->config->dual_crop.ctrl, 0, val, false);
80
+	if (is_unite) {
81
+		u32 right_w, left_w = tmp.width;
82
+
83
+		reg = stream->config->dual_crop.h_offset;
84
+		rkisp_next_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, false);
85
+		reg = stream->config->dual_crop.h_size;
86
+		right_w = rect->width - left_w;
87
+		rkisp_next_write(dev, reg, right_w, false);
88
+		reg = stream->config->dual_crop.ctrl;
89
+		rkisp_next_set_bits(dev, reg, 0, val, false);
90
+		/* output with scale */
91
+		if (stream->out_fmt.width < rect->width) {
92
+			left_w += RKMOUDLE_UNITE_EXTEND_PIXEL;
93
+			reg = stream->config->dual_crop.h_size;
94
+			rkisp_write(dev, reg, left_w, false);
95
+		}
96
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
97
+			 "left dcrop (%d, %d) %dx%d\n",
98
+			 tmp.left, tmp.top, left_w, tmp.height);
99
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
100
+			 "right dcrop (%d, %d) %dx%d\n",
101
+			 RKMOUDLE_UNITE_EXTEND_PIXEL, tmp.top, right_w, tmp.height);
102
+	}
103
+	if (val) {
104
+		reg = stream->config->dual_crop.ctrl;
105
+		rkisp_set_bits(dev, reg, 0, val, false);
106
+	}
65107 }
66108 
67109 void rkisp_dump_rsz_regs(struct rkisp_stream *stream)
....@@ -107,7 +149,8 @@
107149 
108150 	if (async && dev->hw_dev->is_single)
109151 		val = CIF_RSZ_CTRL_CFG_UPD_AUTO;
110
-	rkisp_set_bits(dev, stream->config->rsz.ctrl, 0, val, false);
152
+	rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0,
153
+			     val, false, dev->hw_dev->is_unite);
111154 }
112155 
113156 static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
....@@ -121,7 +164,8 @@
121164 	u32 scale_vy_addr = stream->config->rsz.scale_vy;
122165 	u32 scale_vc_addr = stream->config->rsz.scale_vc;
123166 	u32 rsz_ctrl_addr = stream->config->rsz.ctrl;
124
-	u32 scale_hy, scale_hc, scale_vy, scale_vc, rsz_ctrl = 0;
167
+	u32 scale_hy = 1, scale_hc = 1, scale_vy = 1, scale_vc = 1;
168
+	u32 rsz_ctrl = 0;
125169 
126170 	if (in_y->width < out_y->width) {
127171 		rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE |
....@@ -176,7 +220,140 @@
176220 		rkisp_write(dev, scale_vc_addr, scale_vc, false);
177221 	}
178222 
223
+	if (dev->hw_dev->is_unite) {
224
+		u32 hy_size_reg = stream->id == RKISP_STREAM_MP ?
225
+			ISP3X_MAIN_RESIZE_HY_SIZE : ISP3X_SELF_RESIZE_HY_SIZE;
226
+		u32 hc_size_reg = stream->id == RKISP_STREAM_MP ?
227
+			ISP3X_MAIN_RESIZE_HC_SIZE : ISP3X_SELF_RESIZE_HC_SIZE;
228
+		u32 hy_offs_mi_reg = stream->id == RKISP_STREAM_MP ?
229
+			ISP3X_MAIN_RESIZE_HY_OFFS_MI : ISP3X_SELF_RESIZE_HY_OFFS_MI;
230
+		u32 hc_offs_mi_reg = stream->id == RKISP_STREAM_MP ?
231
+			ISP3X_MAIN_RESIZE_HC_OFFS_MI : ISP3X_SELF_RESIZE_HC_OFFS_MI;
232
+		u32 in_crop_offs_reg = stream->id == RKISP_STREAM_MP ?
233
+			ISP3X_MAIN_RESIZE_IN_CROP_OFFSET : ISP3X_SELF_RESIZE_IN_CROP_OFFSET;
234
+		u32 isp_in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
235
+		u32 scl_w = out_y->width / 2;
236
+		u32 left_y = scale_hy == 1 ? scl_w : DIV_ROUND_UP(scl_w * 65536, scale_hy);
237
+		u32 left_c = scale_hc == 1 ? scl_w / 2 : DIV_ROUND_UP(scl_w * 65536 / 2, scale_hc);
238
+		u32 phase_src_y = left_y * scale_hy;
239
+		u32 phase_dst_y = scl_w * 65536;
240
+		u32 phase_left_y = scale_hy == 1 ? 0 : scale_hy - (phase_src_y - phase_dst_y);
241
+		u32 phase_src_c = left_c * scale_hc;
242
+		u32 phase_dst_c = scl_w * 65536 / 2;
243
+		u32 phase_left_c = scale_hc == 1 ? 0 : scale_hc - (phase_src_c - phase_dst_c);
244
+		u32 right_y = phase_left_y ? in_y->width - (left_y - 1) : in_y->width - left_y;
245
+		u32 right_c = phase_left_c ? in_y->width - (left_c - 1) * 2 : in_y->width - left_c * 2;
246
+		u32 right_crop_y = isp_in_w - right_y;
247
+		u32 right_crop_c = isp_in_w - right_c;
248
+		u32 extend = RKMOUDLE_UNITE_EXTEND_PIXEL;
249
+		u32 right_scl_in_y;
250
+		u32 right_scl_in_c;
251
+
252
+		if (right_crop_y < RKMOUDLE_UNITE_EXTEND_PIXEL) {
253
+			u32 reg;
254
+
255
+			extend = right_crop_y & ~0x1;
256
+			reg = stream->config->dual_crop.h_offset;
257
+			rkisp_next_write(dev, reg, extend, false);
258
+			reg = stream->config->dual_crop.h_size;
259
+			rkisp_next_write(dev, reg, isp_in_w - extend, false);
260
+			reg = stream->config->dual_crop.ctrl;
261
+			rkisp_next_write(dev, reg, rkisp_next_read_reg_cache(dev, reg), false);
262
+		}
263
+		right_scl_in_y = right_crop_y - extend;
264
+		right_scl_in_c = right_crop_c - extend;
265
+
266
+		/* left isp */
267
+		rkisp_write(dev, hy_size_reg, scl_w, false);
268
+		rkisp_write(dev, hc_size_reg, scl_w, false);
269
+		rkisp_write(dev, hy_offs_mi_reg, 0, false);
270
+		rkisp_write(dev, hc_offs_mi_reg, 0, false);
271
+		rkisp_write(dev, in_crop_offs_reg, 0, false);
272
+
273
+		/* right isp */
274
+		rkisp_next_write(dev, hy_size_reg, scl_w, false);
275
+		rkisp_next_write(dev, hc_size_reg, scl_w, false);
276
+		rkisp_next_write(dev, scale_hy_addr, scale_hy, false);
277
+		rkisp_next_write(dev, scale_hcb_addr, scale_hc, false);
278
+		rkisp_next_write(dev, scale_hcr_addr, scale_hc, false);
279
+		rkisp_next_write(dev, scale_vy_addr, scale_vy, false);
280
+		rkisp_next_write(dev, scale_vc_addr, scale_vc, false);
281
+		rkisp_next_write(dev, stream->config->rsz.phase_hy, phase_left_y, false);
282
+		rkisp_next_write(dev, stream->config->rsz.phase_hc, phase_left_c, false);
283
+		rkisp_next_write(dev, stream->config->rsz.phase_vy, 0, false);
284
+		rkisp_next_write(dev, stream->config->rsz.phase_vc, 0, false);
285
+		rkisp_next_write(dev, hy_offs_mi_reg, scl_w & 15, false);
286
+		rkisp_next_write(dev, hc_offs_mi_reg, scl_w & 15, false);
287
+		rkisp_next_write(dev, in_crop_offs_reg,
288
+				 right_scl_in_c << 4 | right_scl_in_y, false);
289
+
290
+		rsz_ctrl |= ISP3X_SCL_CLIP_EN;
291
+		rkisp_next_write(dev, rsz_ctrl_addr,
292
+				 rsz_ctrl | ISP3X_SCL_HPHASE_EN | ISP3X_SCL_IN_CLIP_EN, false);
293
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
294
+			 "scl:%dx%d, scl factor[hy:%d hc:%d vy:%d vc:%d]\n",
295
+			 scl_w, out_y->height, scale_hy, scale_hc, scale_vy, scale_vc);
296
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
297
+			 "scl_left size[y:%d c:%d] phase[y:%d c:%d]\n",
298
+			 left_y, left_c, phase_left_y, phase_left_c);
299
+		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
300
+			 "scl_right size[y:%d c:%d] offs_mi[y:%d c:%d] in_crop[y:%d c:%d]\n",
301
+			 right_y, right_c, scl_w & 15, scl_w & 15, right_scl_in_y, right_scl_in_c);
302
+	}
179303 	rkisp_write(dev, rsz_ctrl_addr, rsz_ctrl, false);
304
+}
305
+
306
+static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
307
+				struct v4l2_rect *in_c, struct v4l2_rect *out_y,
308
+				struct v4l2_rect *out_c, bool async)
309
+{
310
+	struct rkisp_device *dev = stream->ispdev;
311
+	u32 rsz_ctrl = 0, val, hy, hc;
312
+	bool is_avg = false;
313
+
314
+	rkisp_write(dev, ISP32_SELF_SCALE_HY_OFFS, 0, true);
315
+	rkisp_write(dev, ISP32_SELF_SCALE_HC_OFFS, 0, true);
316
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HY, 0, true);
317
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HC, 0, true);
318
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VY, 0, true);
319
+	rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VC, 0, true);
320
+
321
+	val = in_y->width | in_y->height << 16;
322
+	rkisp_write(dev, ISP32_SELF_SCALE_SRC_SIZE, val, false);
323
+	val = out_y->width | out_y->height << 16;
324
+	rkisp_write(dev, ISP32_SELF_SCALE_DST_SIZE, val, false);
325
+
326
+	if (in_y->width != out_y->width) {
327
+		rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE | CIF_RSZ_CTRL_SCALE_HC_ENABLE;
328
+		if (is_avg) {
329
+			hy = ((out_y->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->width - 1) + 1;
330
+			hc = ((out_c->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_c->width - 1) + 1;
331
+			rsz_ctrl |= ISP32_SCALE_AVG_H_EN;
332
+		} else {
333
+			hy = ((in_y->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->width - 1);
334
+			hc = ((in_c->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_c->width - 1);
335
+		}
336
+		rkisp_write(dev, ISP32_SELF_SCALE_HY_FAC, hy, false);
337
+		rkisp_write(dev, ISP32_SELF_SCALE_HC_FAC, hc, false);
338
+	}
339
+
340
+	if (in_y->height != out_y->height) {
341
+		rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE | CIF_RSZ_CTRL_SCALE_VC_ENABLE;
342
+		if (is_avg) {
343
+			val = ((out_y->height - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->height - 1) + 1;
344
+			rsz_ctrl |= ISP32_SCALE_AVG_V_EN;
345
+		} else {
346
+			val = ((in_y->height - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->height - 1);
347
+		}
348
+		rkisp_write(dev, ISP32_SELF_SCALE_VY_FAC, val, false);
349
+		rkisp_write(dev, ISP32_SELF_SCALE_VC_FAC, val, false);
350
+	}
351
+
352
+	rkisp_write(dev, ISP32_SELF_SCALE_CTRL, rsz_ctrl, false);
353
+	val = ISP32_SCALE_FORCE_UPD;
354
+	if (async && dev->hw_dev->is_single)
355
+		val = ISP32_SCALE_GEN_UPD;
356
+	rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, val, true);
180357 }
181358 
182359 void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
....@@ -185,6 +362,12 @@
185362 {
186363 	struct rkisp_device *dev = stream->ispdev;
187364 	int i = 0;
365
+	bool is_unite = dev->hw_dev->is_unite;
366
+
367
+	if (dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) {
368
+		set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
369
+		return;
370
+	}
188371 
189372 	/* No phase offset */
190373 	rkisp_write(dev, stream->config->rsz.phase_hy, 0, true);
....@@ -194,8 +377,8 @@
194377 
195378 	/* Linear interpolation */
196379 	for (i = 0; i < 64; i++) {
197
-		rkisp_write(dev, stream->config->rsz.scale_lut_addr, i, true);
198
-		rkisp_write(dev, stream->config->rsz.scale_lut, i, true);
380
+		rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true, is_unite);
381
+		rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true, is_unite);
199382 	}
200383 
201384 	set_scale(stream, in_y, in_c, out_y, out_c);
....@@ -205,8 +388,10 @@
205388 
206389 void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
207390 {
208
-	rkisp_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
391
+	bool is_unite = stream->ispdev->hw_dev->is_unite;
209392 
210
-	if (!async)
211
-		update_rsz_shadow(stream, async);
393
+	rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false, is_unite);
394
+	if (stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)
395
+		return;
396
+	update_rsz_shadow(stream, async);
212397 }