~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* ispreg.h
3	4	*
..	..	@@ -8,10 +9,6 @@
8	9	*
9	10	* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10	11	* Sakari Ailus <sakari.ailus@iki.fi>
11		- *
12		- * This program is free software; you can redistribute it and/or modify
13		- * it under the terms of the GNU General Public License version 2 as
14		- * published by the Free Software Foundation.
15	12	*/
16	13
17	14	#ifndef OMAP3_ISP_REG_H
..	..	@@ -48,7 +45,7 @@
48	45
49	46	#define ISPCCP2_REVISION (0x000)
50	47	#define ISPCCP2_SYSCONFIG (0x004)
51		-#define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1)
	48	+#define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
52	49	#define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
53	50	#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
54	51	#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \
..	..	@@ -58,44 +55,44 @@
58	55	#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \
59	56	(0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
60	57	#define ISPCCP2_SYSSTATUS (0x008)
61		-#define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0)
	58	+#define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
62	59	#define ISPCCP2_LC01_IRQENABLE (0x00C)
63	60	#define ISPCCP2_LC01_IRQSTATUS (0x010)
64		-#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11)
65		-#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10)
66		-#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9)
67		-#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8)
68		-#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7)
69		-#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5)
70		-#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4)
71		-#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3)
72		-#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2)
73		-#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1)
74		-#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0)
	61	+#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
	62	+#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
	63	+#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
	64	+#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
	65	+#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
	66	+#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
	67	+#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
	68	+#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
	69	+#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2)
	70	+#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1)
	71	+#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0)
75	72
76	73	#define ISPCCP2_LC23_IRQENABLE (0x014)
77	74	#define ISPCCP2_LC23_IRQSTATUS (0x018)
78	75	#define ISPCCP2_LCM_IRQENABLE (0x02C)
79		-#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0)
80		-#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1)
	76	+#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0)
	77	+#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1)
81	78	#define ISPCCP2_LCM_IRQSTATUS (0x030)
82	79	#define ISPCCP2_CTRL (0x040)
83		-#define ISPCCP2_CTRL_IF_EN (1 << 0)
84		-#define ISPCCP2_CTRL_PHY_SEL (1 << 1)
	80	+#define ISPCCP2_CTRL_IF_EN BIT(0)
	81	+#define ISPCCP2_CTRL_PHY_SEL BIT(1)
85	82	#define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
86	83	#define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1)
87	84	#define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
88	85	#define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
89		-#define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2)
	86	+#define ISPCCP2_CTRL_IO_OUT_SEL BIT(2)
90	87	#define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
91	88	#define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2
92		-#define ISPCCP2_CTRL_MODE (1 << 4)
93		-#define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9)
94		-#define ISPCCP2_CTRL_INV (1 << 10)
	89	+#define ISPCCP2_CTRL_MODE BIT(4)
	90	+#define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9)
	91	+#define ISPCCP2_CTRL_INV BIT(10)
95	92	#define ISPCCP2_CTRL_INV_MASK 0x1
96	93	#define ISPCCP2_CTRL_INV_SHIFT 10
97		-#define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11)
98		-#define ISPCCP2_CTRL_VP_CLK_POL (1 << 12)
	94	+#define ISPCCP2_CTRL_VP_ONLY_EN BIT(11)
	95	+#define ISPCCP2_CTRL_VP_CLK_POL BIT(12)
99	96	#define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
100	97	#define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12
101	98	#define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
..	..	@@ -105,12 +102,12 @@
105	102	#define ISPCCP2_DBG (0x044)
106	103	#define ISPCCP2_GNQ (0x048)
107	104	#define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
108		-#define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0)
109		-#define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19)
	105	+#define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0)
	106	+#define ISPCCP2_LCx_CTRL_CRC_EN BIT(19)
110	107	#define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
111	108	#define ISPCCP2_LCx_CTRL_CRC_SHIFT 2
112	109	#define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19
113		-#define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1)
	110	+#define ISPCCP2_LCx_CTRL_REGION_EN BIT(1)
114	111	#define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
115	112	#define ISPCCP2_LCx_CTRL_REGION_SHIFT 1
116	113	#define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
..	..	@@ -130,8 +127,8 @@
130	127	#define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
131	128	#define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
132	129	#define ISPCCP2_LCM_CTRL (0x1D0)
133		-#define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0)
134		-#define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2)
	130	+#define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0)
	131	+#define ISPCCP2_LCM_CTRL_DST_PORT BIT(2)
135	132	#define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2
136	133	#define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3
137	134	#define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
..	..	@@ -141,8 +138,8 @@
141	138	#define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
142	139	#define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20
143	140	#define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
144		-#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22)
145		-#define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23)
	141	+#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22)
	142	+#define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23)
146	143	#define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24
147	144	#define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
148	145	#define ISPCCP2_LCM_VSIZE (0x1D4)
..	..	@@ -204,19 +201,19 @@
204	201
205	202	/* SBL */
206	203	#define ISPSBL_PCR 0x4
207		-#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16)
208		-#define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17)
209		-#define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18)
210		-#define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19)
211		-#define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20)
212		-#define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21)
213		-#define ISPSBL_PCR_PRV_WBL_OVF (1 << 22)
214		-#define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23)
215		-#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24)
216		-#define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25)
217		-#define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26)
	204	+#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16)
	205	+#define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17)
	206	+#define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18)
	207	+#define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19)
	208	+#define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20)
	209	+#define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21)
	210	+#define ISPSBL_PCR_PRV_WBL_OVF BIT(22)
	211	+#define ISPSBL_PCR_CCDC_WBL_OVF BIT(23)
	212	+#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24)
	213	+#define ISPSBL_PCR_CSIA_WBL_OVF BIT(25)
	214	+#define ISPSBL_PCR_CSIB_WBL_OVF BIT(26)
218	215	#define ISPSBL_CCDC_WR_0 (0x028)
219		-#define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21)
	216	+#define ISPSBL_CCDC_WR_0_DATA_READY BIT(21)
220	217	#define ISPSBL_CCDC_WR_1 (0x02C)
221	218	#define ISPSBL_CCDC_WR_2 (0x030)
222	219	#define ISPSBL_CCDC_WR_3 (0x034)
..	..	@@ -369,16 +366,16 @@
369	366
370	367	#define ISP_INT_CLR 0xFF113F11
371	368	#define ISPPRV_PCR_EN 1
372		-#define ISPPRV_PCR_BUSY (1 << 1)
373		-#define ISPPRV_PCR_SOURCE (1 << 2)
374		-#define ISPPRV_PCR_ONESHOT (1 << 3)
375		-#define ISPPRV_PCR_WIDTH (1 << 4)
376		-#define ISPPRV_PCR_INVALAW (1 << 5)
377		-#define ISPPRV_PCR_DRKFEN (1 << 6)
378		-#define ISPPRV_PCR_DRKFCAP (1 << 7)
379		-#define ISPPRV_PCR_HMEDEN (1 << 8)
380		-#define ISPPRV_PCR_NFEN (1 << 9)
381		-#define ISPPRV_PCR_CFAEN (1 << 10)
	369	+#define ISPPRV_PCR_BUSY BIT(1)
	370	+#define ISPPRV_PCR_SOURCE BIT(2)
	371	+#define ISPPRV_PCR_ONESHOT BIT(3)
	372	+#define ISPPRV_PCR_WIDTH BIT(4)
	373	+#define ISPPRV_PCR_INVALAW BIT(5)
	374	+#define ISPPRV_PCR_DRKFEN BIT(6)
	375	+#define ISPPRV_PCR_DRKFCAP BIT(7)
	376	+#define ISPPRV_PCR_HMEDEN BIT(8)
	377	+#define ISPPRV_PCR_NFEN BIT(9)
	378	+#define ISPPRV_PCR_CFAEN BIT(10)
382	379	#define ISPPRV_PCR_CFAFMT_SHIFT 11
383	380	#define ISPPRV_PCR_CFAFMT_MASK 0x7800
384	381	#define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
..	..	@@ -387,22 +384,22 @@
387	384	#define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11)
388	385	#define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11)
389	386	#define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11)
390		-#define ISPPRV_PCR_YNENHEN (1 << 15)
391		-#define ISPPRV_PCR_SUPEN (1 << 16)
	387	+#define ISPPRV_PCR_YNENHEN BIT(15)
	388	+#define ISPPRV_PCR_SUPEN BIT(16)
392	389	#define ISPPRV_PCR_YCPOS_SHIFT 17
393	390	#define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
394	391	#define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17)
395	392	#define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17)
396	393	#define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17)
397		-#define ISPPRV_PCR_RSZPORT (1 << 19)
398		-#define ISPPRV_PCR_SDRPORT (1 << 20)
399		-#define ISPPRV_PCR_SCOMP_EN (1 << 21)
	394	+#define ISPPRV_PCR_RSZPORT BIT(19)
	395	+#define ISPPRV_PCR_SDRPORT BIT(20)
	396	+#define ISPPRV_PCR_SCOMP_EN BIT(21)
400	397	#define ISPPRV_PCR_SCOMP_SFT_SHIFT (22)
401	398	#define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22)
402		-#define ISPPRV_PCR_GAMMA_BYPASS (1 << 26)
403		-#define ISPPRV_PCR_DCOREN (1 << 27)
404		-#define ISPPRV_PCR_DCCOUP (1 << 28)
405		-#define ISPPRV_PCR_DRK_FAIL (1 << 31)
	399	+#define ISPPRV_PCR_GAMMA_BYPASS BIT(26)
	400	+#define ISPPRV_PCR_DCOREN BIT(27)
	401	+#define ISPPRV_PCR_DCCOUP BIT(28)
	402	+#define ISPPRV_PCR_DRK_FAIL BIT(31)
406	403
407	404	#define ISPPRV_HORZ_INFO_EPH_SHIFT 0
408	405	#define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
..	..	@@ -426,8 +423,8 @@
426	423	#define ISPPRV_AVE_ODDDIST_4 0x3
427	424
428	425	#define ISPPRV_HMED_THRESHOLD_SHIFT 0
429		-#define ISPPRV_HMED_EVENDIST (1 << 8)
430		-#define ISPPRV_HMED_ODDDIST (1 << 9)
	426	+#define ISPPRV_HMED_EVENDIST BIT(8)
	427	+#define ISPPRV_HMED_ODDDIST BIT(9)
431	428
432	429	#define ISPPRV_WBGAIN_COEF0_SHIFT 0
433	430	#define ISPPRV_WBGAIN_COEF1_SHIFT 8
..	..	@@ -520,8 +517,8 @@
520	517	/* Define bit fields within selected registers */
521	518	#define ISP_REVISION_SHIFT 0
522	519
523		-#define ISP_SYSCONFIG_AUTOIDLE (1 << 0)
524		-#define ISP_SYSCONFIG_SOFTRESET (1 << 1)
	520	+#define ISP_SYSCONFIG_AUTOIDLE BIT(0)
	521	+#define ISP_SYSCONFIG_SOFTRESET BIT(1)
525	522	#define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12
526	523	#define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
527	524	#define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
..	..	@@ -529,68 +526,68 @@
529	526
530	527	#define ISP_SYSSTATUS_RESETDONE 0
531	528
532		-#define IRQ0ENABLE_CSIA_IRQ (1 << 0)
533		-#define IRQ0ENABLE_CSIC_IRQ (1 << 1)
534		-#define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3)
535		-#define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4)
536		-#define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5)
537		-#define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6)
538		-#define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7)
	529	+#define IRQ0ENABLE_CSIA_IRQ BIT(0)
	530	+#define IRQ0ENABLE_CSIC_IRQ BIT(1)
	531	+#define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3)
	532	+#define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4)
	533	+#define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5)
	534	+#define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6)
	535	+#define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7)
539	536	#define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ \| \
540	537	IRQ0ENABLE_CCP2_LC0_IRQ \| \
541	538	IRQ0ENABLE_CCP2_LC1_IRQ \| \
542	539	IRQ0ENABLE_CCP2_LC2_IRQ \| \
543	540	IRQ0ENABLE_CCP2_LC3_IRQ)
544	541
545		-#define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8)
546		-#define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9)
547		-#define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10)
548		-#define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11)
549		-#define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12)
550		-#define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13)
551		-#define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16)
552		-#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17)
553		-#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
554		-#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
555		-#define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20)
556		-#define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24)
557		-#define IRQ0ENABLE_OVF_IRQ (1 << 25)
558		-#define IRQ0ENABLE_PING_IRQ (1 << 26)
559		-#define IRQ0ENABLE_PONG_IRQ (1 << 27)
560		-#define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28)
561		-#define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29)
562		-#define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30)
563		-#define IRQ0ENABLE_HS_VS_IRQ (1 << 31)
	542	+#define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8)
	543	+#define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9)
	544	+#define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10)
	545	+#define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11)
	546	+#define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12)
	547	+#define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13)
	548	+#define IRQ0ENABLE_HIST_DONE_IRQ BIT(16)
	549	+#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17)
	550	+#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18)
	551	+#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19)
	552	+#define IRQ0ENABLE_PRV_DONE_IRQ BIT(20)
	553	+#define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24)
	554	+#define IRQ0ENABLE_OVF_IRQ BIT(25)
	555	+#define IRQ0ENABLE_PING_IRQ BIT(26)
	556	+#define IRQ0ENABLE_PONG_IRQ BIT(27)
	557	+#define IRQ0ENABLE_MMU_ERR_IRQ BIT(28)
	558	+#define IRQ0ENABLE_OCP_ERR_IRQ BIT(29)
	559	+#define IRQ0ENABLE_SEC_ERR_IRQ BIT(30)
	560	+#define IRQ0ENABLE_HS_VS_IRQ BIT(31)
564	561
565		-#define IRQ0STATUS_CSIA_IRQ (1 << 0)
566		-#define IRQ0STATUS_CSI2C_IRQ (1 << 1)
567		-#define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3)
568		-#define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4)
	562	+#define IRQ0STATUS_CSIA_IRQ BIT(0)
	563	+#define IRQ0STATUS_CSI2C_IRQ BIT(1)
	564	+#define IRQ0STATUS_CCP2_LCM_IRQ BIT(3)
	565	+#define IRQ0STATUS_CCP2_LC0_IRQ BIT(4)
569	566	#define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ \| \
570	567	IRQ0STATUS_CCP2_LC0_IRQ)
571	568
572		-#define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5)
573		-#define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6)
574		-#define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7)
575		-#define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8)
576		-#define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9)
577		-#define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10)
578		-#define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11)
579		-#define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12)
580		-#define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13)
581		-#define IRQ0STATUS_HIST_DONE_IRQ (1 << 16)
582		-#define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17)
583		-#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
584		-#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
585		-#define IRQ0STATUS_PRV_DONE_IRQ (1 << 20)
586		-#define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24)
587		-#define IRQ0STATUS_OVF_IRQ (1 << 25)
588		-#define IRQ0STATUS_PING_IRQ (1 << 26)
589		-#define IRQ0STATUS_PONG_IRQ (1 << 27)
590		-#define IRQ0STATUS_MMU_ERR_IRQ (1 << 28)
591		-#define IRQ0STATUS_OCP_ERR_IRQ (1 << 29)
592		-#define IRQ0STATUS_SEC_ERR_IRQ (1 << 30)
593		-#define IRQ0STATUS_HS_VS_IRQ (1 << 31)
	569	+#define IRQ0STATUS_CSIB_LC1_IRQ BIT(5)
	570	+#define IRQ0STATUS_CSIB_LC2_IRQ BIT(6)
	571	+#define IRQ0STATUS_CSIB_LC3_IRQ BIT(7)
	572	+#define IRQ0STATUS_CCDC_VD0_IRQ BIT(8)
	573	+#define IRQ0STATUS_CCDC_VD1_IRQ BIT(9)
	574	+#define IRQ0STATUS_CCDC_VD2_IRQ BIT(10)
	575	+#define IRQ0STATUS_CCDC_ERR_IRQ BIT(11)
	576	+#define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12)
	577	+#define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13)
	578	+#define IRQ0STATUS_HIST_DONE_IRQ BIT(16)
	579	+#define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17)
	580	+#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18)
	581	+#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19)
	582	+#define IRQ0STATUS_PRV_DONE_IRQ BIT(20)
	583	+#define IRQ0STATUS_RSZ_DONE_IRQ BIT(24)
	584	+#define IRQ0STATUS_OVF_IRQ BIT(25)
	585	+#define IRQ0STATUS_PING_IRQ BIT(26)
	586	+#define IRQ0STATUS_PONG_IRQ BIT(27)
	587	+#define IRQ0STATUS_MMU_ERR_IRQ BIT(28)
	588	+#define IRQ0STATUS_OCP_ERR_IRQ BIT(29)
	589	+#define IRQ0STATUS_SEC_ERR_IRQ BIT(30)
	590	+#define IRQ0STATUS_HS_VS_IRQ BIT(31)
594	591
595	592	#define TCTRL_GRESET_LEN 0
596	593
..	..	@@ -610,20 +607,20 @@
610	607	#define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
611	608
612	609	#define ISPCTRL_PAR_CLK_POL_SHIFT 4
613		-#define ISPCTRL_PAR_CLK_POL_INV (1 << 4)
614		-#define ISPCTRL_PING_PONG_EN (1 << 5)
	610	+#define ISPCTRL_PAR_CLK_POL_INV BIT(4)
	611	+#define ISPCTRL_PING_PONG_EN BIT(5)
615	612	#define ISPCTRL_SHIFT_SHIFT 6
616	613	#define ISPCTRL_SHIFT_0 (0x0 << 6)
617	614	#define ISPCTRL_SHIFT_2 (0x1 << 6)
618	615	#define ISPCTRL_SHIFT_4 (0x2 << 6)
619	616	#define ISPCTRL_SHIFT_MASK (0x3 << 6)
620	617
621		-#define ISPCTRL_CCDC_CLK_EN (1 << 8)
622		-#define ISPCTRL_SCMP_CLK_EN (1 << 9)
623		-#define ISPCTRL_H3A_CLK_EN (1 << 10)
624		-#define ISPCTRL_HIST_CLK_EN (1 << 11)
625		-#define ISPCTRL_PREV_CLK_EN (1 << 12)
626		-#define ISPCTRL_RSZ_CLK_EN (1 << 13)
	618	+#define ISPCTRL_CCDC_CLK_EN BIT(8)
	619	+#define ISPCTRL_SCMP_CLK_EN BIT(9)
	620	+#define ISPCTRL_H3A_CLK_EN BIT(10)
	621	+#define ISPCTRL_HIST_CLK_EN BIT(11)
	622	+#define ISPCTRL_PREV_CLK_EN BIT(12)
	623	+#define ISPCTRL_RSZ_CLK_EN BIT(13)
627	624	#define ISPCTRL_SYNC_DETECT_SHIFT 14
628	625	#define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
629	626	#define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
..	..	@@ -631,17 +628,17 @@
631	628	#define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
632	629	#define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
633	630
634		-#define ISPCTRL_CCDC_RAM_EN (1 << 16)
635		-#define ISPCTRL_PREV_RAM_EN (1 << 17)
636		-#define ISPCTRL_SBL_RD_RAM_EN (1 << 18)
637		-#define ISPCTRL_SBL_WR1_RAM_EN (1 << 19)
638		-#define ISPCTRL_SBL_WR0_RAM_EN (1 << 20)
639		-#define ISPCTRL_SBL_AUTOIDLE (1 << 21)
640		-#define ISPCTRL_SBL_SHARED_WPORTC (1 << 26)
641		-#define ISPCTRL_SBL_SHARED_RPORTA (1 << 27)
642		-#define ISPCTRL_SBL_SHARED_RPORTB (1 << 28)
643		-#define ISPCTRL_JPEG_FLUSH (1 << 30)
644		-#define ISPCTRL_CCDC_FLUSH (1 << 31)
	631	+#define ISPCTRL_CCDC_RAM_EN BIT(16)
	632	+#define ISPCTRL_PREV_RAM_EN BIT(17)
	633	+#define ISPCTRL_SBL_RD_RAM_EN BIT(18)
	634	+#define ISPCTRL_SBL_WR1_RAM_EN BIT(19)
	635	+#define ISPCTRL_SBL_WR0_RAM_EN BIT(20)
	636	+#define ISPCTRL_SBL_AUTOIDLE BIT(21)
	637	+#define ISPCTRL_SBL_SHARED_WPORTC BIT(26)
	638	+#define ISPCTRL_SBL_SHARED_RPORTA BIT(27)
	639	+#define ISPCTRL_SBL_SHARED_RPORTB BIT(28)
	640	+#define ISPCTRL_JPEG_FLUSH BIT(30)
	641	+#define ISPCTRL_CCDC_FLUSH BIT(31)
645	642
646	643	#define ISPSECURE_SECUREMODE 0
647	644
..	..	@@ -658,20 +655,20 @@
658	655	#define ISPTCTRL_CTRL_DIVC_SHIFT 10
659	656	#define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
660	657
661		-#define ISPTCTRL_CTRL_SHUTEN (1 << 21)
662		-#define ISPTCTRL_CTRL_PSTRBEN (1 << 22)
663		-#define ISPTCTRL_CTRL_STRBEN (1 << 23)
664		-#define ISPTCTRL_CTRL_SHUTPOL (1 << 24)
665		-#define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26)
	658	+#define ISPTCTRL_CTRL_SHUTEN BIT(21)
	659	+#define ISPTCTRL_CTRL_PSTRBEN BIT(22)
	660	+#define ISPTCTRL_CTRL_STRBEN BIT(23)
	661	+#define ISPTCTRL_CTRL_SHUTPOL BIT(24)
	662	+#define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26)
666	663
667	664	#define ISPTCTRL_CTRL_INSEL_SHIFT 27
668	665	#define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
669	666	#define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
670	667	#define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
671	668
672		-#define ISPTCTRL_CTRL_GRESETEn (1 << 29)
673		-#define ISPTCTRL_CTRL_GRESETPOL (1 << 30)
674		-#define ISPTCTRL_CTRL_GRESETDIR (1 << 31)
	669	+#define ISPTCTRL_CTRL_GRESETEn BIT(29)
	670	+#define ISPTCTRL_CTRL_GRESETPOL BIT(30)
	671	+#define ISPTCTRL_CTRL_GRESETDIR BIT(31)
675	672
676	673	#define ISPTCTRL_FRAME_SHUT_SHIFT 0
677	674	#define ISPTCTRL_FRAME_PSTRB_SHIFT 6
..	..	@@ -682,33 +679,33 @@
682	679	#define ISPCCDC_PID_TID_SHIFT 16
683	680
684	681	#define ISPCCDC_PCR_EN 1
685		-#define ISPCCDC_PCR_BUSY (1 << 1)
	682	+#define ISPCCDC_PCR_BUSY BIT(1)
686	683
687	684	#define ISPCCDC_SYN_MODE_VDHDOUT 0x1
688		-#define ISPCCDC_SYN_MODE_FLDOUT (1 << 1)
689		-#define ISPCCDC_SYN_MODE_VDPOL (1 << 2)
690		-#define ISPCCDC_SYN_MODE_HDPOL (1 << 3)
691		-#define ISPCCDC_SYN_MODE_FLDPOL (1 << 4)
692		-#define ISPCCDC_SYN_MODE_EXWEN (1 << 5)
693		-#define ISPCCDC_SYN_MODE_DATAPOL (1 << 6)
694		-#define ISPCCDC_SYN_MODE_FLDMODE (1 << 7)
	685	+#define ISPCCDC_SYN_MODE_FLDOUT BIT(1)
	686	+#define ISPCCDC_SYN_MODE_VDPOL BIT(2)
	687	+#define ISPCCDC_SYN_MODE_HDPOL BIT(3)
	688	+#define ISPCCDC_SYN_MODE_FLDPOL BIT(4)
	689	+#define ISPCCDC_SYN_MODE_EXWEN BIT(5)
	690	+#define ISPCCDC_SYN_MODE_DATAPOL BIT(6)
	691	+#define ISPCCDC_SYN_MODE_FLDMODE BIT(7)
695	692	#define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
696	693	#define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
697	694	#define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
698	695	#define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
699	696	#define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
700	697	#define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
701		-#define ISPCCDC_SYN_MODE_PACK8 (1 << 11)
	698	+#define ISPCCDC_SYN_MODE_PACK8 BIT(11)
702	699	#define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12)
703	700	#define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
704	701	#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12)
705	702	#define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12)
706		-#define ISPCCDC_SYN_MODE_LPF (1 << 14)
707		-#define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15)
708		-#define ISPCCDC_SYN_MODE_VDHDEN (1 << 16)
709		-#define ISPCCDC_SYN_MODE_WEN (1 << 17)
710		-#define ISPCCDC_SYN_MODE_VP2SDR (1 << 18)
711		-#define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19)
	703	+#define ISPCCDC_SYN_MODE_LPF BIT(14)
	704	+#define ISPCCDC_SYN_MODE_FLDSTAT BIT(15)
	705	+#define ISPCCDC_SYN_MODE_VDHDEN BIT(16)
	706	+#define ISPCCDC_SYN_MODE_WEN BIT(17)
	707	+#define ISPCCDC_SYN_MODE_VP2SDR BIT(18)
	708	+#define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19)
712	709
713	710	#define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
714	711	#define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
..	..	@@ -734,7 +731,7 @@
734	731
735	732	#define ISPCCDC_HSIZE_OFF_SHIFT 0
736	733
737		-#define ISPCCDC_SDOFST_FIINV (1 << 14)
	734	+#define ISPCCDC_SDOFST_FIINV BIT(14)
738	735	#define ISPCCDC_SDOFST_FOFST_SHIFT 12
739	736	#define ISPCCDC_SDOFST_FOFST_MASK (3 << 12)
740	737	#define ISPCCDC_SDOFST_LOFST3_SHIFT 0
..	..	@@ -746,7 +743,7 @@
746	743	#define ISPCCDC_CLAMP_OBST_SHIFT 10
747	744	#define ISPCCDC_CLAMP_OBSLN_SHIFT 25
748	745	#define ISPCCDC_CLAMP_OBSLEN_SHIFT 28
749		-#define ISPCCDC_CLAMP_CLAMPEN (1 << 31)
	746	+#define ISPCCDC_CLAMP_CLAMPEN BIT(31)
750	747
751	748	#define ISPCCDC_COLPTN_R_Ye 0x0
752	749	#define ISPCCDC_COLPTN_Gr_Cy 0x1
..	..	@@ -775,8 +772,8 @@
775	772	#define ISPCCDC_BLKCMP_R_YE_SHIFT 24
776	773
777	774	#define ISPCCDC_FPC_FPNUM_SHIFT 0
778		-#define ISPCCDC_FPC_FPCEN (1 << 15)
779		-#define ISPCCDC_FPC_FPERR (1 << 16)
	775	+#define ISPCCDC_FPC_FPCEN BIT(15)
	776	+#define ISPCCDC_FPC_FPERR BIT(16)
780	777
781	778	#define ISPCCDC_VDINT_1_SHIFT 0
782	779	#define ISPCCDC_VDINT_1_MASK 0x00007fff
..	..	@@ -787,23 +784,23 @@
787	784	#define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
788	785	#define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
789	786	#define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
790		-#define ISPCCDC_ALAW_CCDTBL (1 << 3)
	787	+#define ISPCCDC_ALAW_CCDTBL BIT(3)
791	788
792	789	#define ISPCCDC_REC656IF_R656ON 1
793		-#define ISPCCDC_REC656IF_ECCFVH (1 << 1)
	790	+#define ISPCCDC_REC656IF_ECCFVH BIT(1)
794	791
795		-#define ISPCCDC_CFG_BW656 (1 << 5)
	792	+#define ISPCCDC_CFG_BW656 BIT(5)
796	793	#define ISPCCDC_CFG_FIDMD_SHIFT 6
797		-#define ISPCCDC_CFG_WENLOG (1 << 8)
	794	+#define ISPCCDC_CFG_WENLOG BIT(8)
798	795	#define ISPCCDC_CFG_WENLOG_AND (0 << 8)
799	796	#define ISPCCDC_CFG_WENLOG_OR (1 << 8)
800		-#define ISPCCDC_CFG_Y8POS (1 << 11)
801		-#define ISPCCDC_CFG_BSWD (1 << 12)
802		-#define ISPCCDC_CFG_MSBINVI (1 << 13)
803		-#define ISPCCDC_CFG_VDLC (1 << 15)
	797	+#define ISPCCDC_CFG_Y8POS BIT(11)
	798	+#define ISPCCDC_CFG_BSWD BIT(12)
	799	+#define ISPCCDC_CFG_MSBINVI BIT(13)
	800	+#define ISPCCDC_CFG_VDLC BIT(15)
804	801
805	802	#define ISPCCDC_FMTCFG_FMTEN 0x1
806		-#define ISPCCDC_FMTCFG_LNALT (1 << 1)
	803	+#define ISPCCDC_FMTCFG_LNALT BIT(1)
807	804	#define ISPCCDC_FMTCFG_LNUM_SHIFT 2
808	805	#define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4
809	806	#define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8
..	..	@@ -812,7 +809,7 @@
812	809	#define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
813	810	#define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
814	811	#define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
815		-#define ISPCCDC_FMTCFG_VPEN (1 << 15)
	812	+#define ISPCCDC_FMTCFG_VPEN BIT(15)
816	813
817	814	#define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
818	815	#define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16
..	..	@@ -842,9 +839,9 @@
842	839	#define ISPRSZ_PID_CID_SHIFT 8
843	840	#define ISPRSZ_PID_TID_SHIFT 16
844	841
845		-#define ISPRSZ_PCR_ENABLE (1 << 0)
846		-#define ISPRSZ_PCR_BUSY (1 << 1)
847		-#define ISPRSZ_PCR_ONESHOT (1 << 2)
	842	+#define ISPRSZ_PCR_ENABLE BIT(0)
	843	+#define ISPRSZ_PCR_BUSY BIT(1)
	844	+#define ISPRSZ_PCR_ONESHOT BIT(2)
848	845
849	846	#define ISPRSZ_CNT_HRSZ_SHIFT 0
850	847	#define ISPRSZ_CNT_HRSZ_MASK \
..	..	@@ -856,10 +853,10 @@
856	853	#define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
857	854	#define ISPRSZ_CNT_VSTPH_SHIFT 23
858	855	#define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
859		-#define ISPRSZ_CNT_YCPOS (1 << 26)
860		-#define ISPRSZ_CNT_INPTYP (1 << 27)
861		-#define ISPRSZ_CNT_INPSRC (1 << 28)
862		-#define ISPRSZ_CNT_CBILIN (1 << 29)
	856	+#define ISPRSZ_CNT_YCPOS BIT(26)
	857	+#define ISPRSZ_CNT_INPTYP BIT(27)
	858	+#define ISPRSZ_CNT_INPSRC BIT(28)
	859	+#define ISPRSZ_CNT_CBILIN BIT(29)
863	860
864	861	#define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
865	862	#define ISPRSZ_OUT_SIZE_HORZ_MASK \
..	..	@@ -1084,8 +1081,8 @@
1084	1081	#define ISPH3A_PCR_AF_RGBPOS_SHIFT 11
1085	1082	#define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22
1086	1083	#define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
1087		-#define ISPH3A_PCR_BUSYAF (1 << 15)
1088		-#define ISPH3A_PCR_BUSYAEAWB (1 << 18)
	1084	+#define ISPH3A_PCR_BUSYAF BIT(15)
	1085	+#define ISPH3A_PCR_BUSYAEAWB BIT(18)
1089	1086
1090	1087	#define ISPH3A_AEWWIN1_WINHC_SHIFT 0
1091	1088	#define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
..	..	@@ -1169,15 +1166,15 @@
1169	1166
1170	1167	#define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
1171	1168
1172		-#define ISPCCDC_LSC_ENABLE 1
1173		-#define ISPCCDC_LSC_BUSY (1 << 7)
	1169	+#define ISPCCDC_LSC_ENABLE BIT(0)
	1170	+#define ISPCCDC_LSC_BUSY BIT(7)
1174	1171	#define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
1175	1172	#define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8
1176	1173	#define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
1177	1174	#define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12
1178	1175	#define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
1179	1176	#define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1
1180		-#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6)
	1177	+#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6)
1181	1178
1182	1179	#define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
1183	1180	#define ISPCCDC_LSC_INITIAL_X_SHIFT 0
..	..	@@ -1199,43 +1196,43 @@
1199	1196	(0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1200	1197	#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \
1201	1198	(0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1202		-#define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1)
1203		-#define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0)
	1199	+#define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1)
	1200	+#define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0)
1204	1201
1205	1202	#define ISPCSI2_SYSSTATUS (0x014)
1206		-#define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0)
	1203	+#define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0)
1207	1204
1208	1205	#define ISPCSI2_IRQSTATUS (0x018)
1209		-#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14)
1210		-#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13)
1211		-#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12)
1212		-#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
1213		-#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10)
1214		-#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9)
1215		-#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8)
1216		-#define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n))
	1206	+#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14)
	1207	+#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13)
	1208	+#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12)
	1209	+#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11)
	1210	+#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10)
	1211	+#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9)
	1212	+#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8)
	1213	+#define ISPCSI2_IRQSTATUS_CONTEXT(n) BIT(n)
1217	1214
1218	1215	#define ISPCSI2_IRQENABLE (0x01c)
1219	1216	#define ISPCSI2_CTRL (0x040)
1220		-#define ISPCSI2_CTRL_VP_CLK_EN (1 << 15)
1221		-#define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11)
	1217	+#define ISPCSI2_CTRL_VP_CLK_EN BIT(15)
	1218	+#define ISPCSI2_CTRL_VP_ONLY_EN BIT(11)
1222	1219	#define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8
1223	1220	#define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \
1224	1221	(3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
1225		-#define ISPCSI2_CTRL_DBG_EN (1 << 7)
	1222	+#define ISPCSI2_CTRL_DBG_EN BIT(7)
1226	1223	#define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5
1227	1224	#define ISPCSI2_CTRL_BURST_SIZE_MASK \
1228	1225	(3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
1229		-#define ISPCSI2_CTRL_FRAME (1 << 3)
1230		-#define ISPCSI2_CTRL_ECC_EN (1 << 2)
1231		-#define ISPCSI2_CTRL_SECURE (1 << 1)
1232		-#define ISPCSI2_CTRL_IF_EN (1 << 0)
	1226	+#define ISPCSI2_CTRL_FRAME BIT(3)
	1227	+#define ISPCSI2_CTRL_ECC_EN BIT(2)
	1228	+#define ISPCSI2_CTRL_SECURE BIT(1)
	1229	+#define ISPCSI2_CTRL_IF_EN BIT(0)
1233	1230
1234	1231	#define ISPCSI2_DBG_H (0x044)
1235	1232	#define ISPCSI2_GNQ (0x048)
1236	1233	#define ISPCSI2_PHY_CFG (0x050)
1237		-#define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30)
1238		-#define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29)
	1234	+#define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30)
	1235	+#define ISPCSI2_PHY_CFG_RESET_DONE BIT(29)
1239	1236	#define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27
1240	1237	#define ISPCSI2_PHY_CFG_PWR_CMD_MASK \
1241	1238	(0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
..	..	@@ -1254,7 +1251,7 @@
1254	1251	(0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1255	1252	#define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \
1256	1253	(0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1257		-#define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24)
	1254	+#define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24)
1258	1255
1259	1256	#define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4))
1260	1257	#define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \
..	..	@@ -1303,63 +1300,63 @@
1303	1300	(0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1304	1301
1305	1302	#define ISPCSI2_PHY_IRQSTATUS (0x054)
1306		-#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26)
1307		-#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25)
1308		-#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24)
1309		-#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23)
1310		-#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22)
1311		-#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21)
1312		-#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20)
1313		-#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19)
1314		-#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18)
1315		-#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17)
1316		-#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16)
1317		-#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15)
1318		-#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14)
1319		-#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13)
1320		-#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12)
1321		-#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11)
1322		-#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10)
1323		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9)
1324		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8)
1325		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7)
1326		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6)
1327		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5)
1328		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4)
1329		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3)
1330		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2)
1331		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1)
1332		-#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1
	1303	+#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26)
	1304	+#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25)
	1305	+#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24)
	1306	+#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23)
	1307	+#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22)
	1308	+#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21)
	1309	+#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20)
	1310	+#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19)
	1311	+#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18)
	1312	+#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17)
	1313	+#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16)
	1314	+#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15)
	1315	+#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14)
	1316	+#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13)
	1317	+#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12)
	1318	+#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11)
	1319	+#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10)
	1320	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9)
	1321	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8)
	1322	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7)
	1323	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6)
	1324	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5)
	1325	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4)
	1326	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3)
	1327	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2)
	1328	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1)
	1329	+#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0)
1333	1330
1334	1331	#define ISPCSI2_SHORT_PACKET (0x05c)
1335	1332	#define ISPCSI2_PHY_IRQENABLE (0x060)
1336		-#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26)
1337		-#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25)
1338		-#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24)
1339		-#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23)
1340		-#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22)
1341		-#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21)
1342		-#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20)
1343		-#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19)
1344		-#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18)
1345		-#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17)
1346		-#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16)
1347		-#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15)
1348		-#define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14)
1349		-#define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13)
1350		-#define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12)
1351		-#define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11)
1352		-#define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10)
1353		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9)
1354		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8)
1355		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7)
1356		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6)
1357		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5)
1358		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4)
1359		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3)
1360		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2)
1361		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1)
1362		-#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0)
	1333	+#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26)
	1334	+#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25)
	1335	+#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24)
	1336	+#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23)
	1337	+#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22)
	1338	+#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21)
	1339	+#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20)
	1340	+#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19)
	1341	+#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18)
	1342	+#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17)
	1343	+#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16)
	1344	+#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15)
	1345	+#define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14)
	1346	+#define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13)
	1347	+#define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12)
	1348	+#define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11)
	1349	+#define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10)
	1350	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9)
	1351	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8)
	1352	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7)
	1353	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6)
	1354	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5)
	1355	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4)
	1356	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3)
	1357	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2)
	1358	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1)
	1359	+#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0)
1363	1360
1364	1361	#define ISPCSI2_DBG_P (0x068)
1365	1362	#define ISPCSI2_TIMING (0x06c)
..	..	@@ -1374,12 +1371,12 @@
1374	1371	#define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8
1375	1372	#define ISPCSI2_CTX_CTRL1_COUNT_MASK \
1376	1373	(0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1377		-#define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7)
1378		-#define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6)
1379		-#define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5)
1380		-#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4)
1381		-#define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3)
1382		-#define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0)
	1374	+#define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7)
	1375	+#define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6)
	1376	+#define ISPCSI2_CTX_CTRL1_CS_EN BIT(5)
	1377	+#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4)
	1378	+#define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3)
	1379	+#define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0)
1383	1380
1384	1381	#define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
1385	1382	#define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13
..	..	@@ -1388,7 +1385,7 @@
1388	1385	#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11
1389	1386	#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
1390	1387	(0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1391		-#define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10)
	1388	+#define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10)
1392	1389	#define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
1393	1390	#define ISPCSI2_CTX_CTRL2_FORMAT_MASK \
1394	1391	(0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
..	..	@@ -1404,24 +1401,24 @@
1404	1401	#define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
1405	1402	#define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
1406	1403	#define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
1407		-#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8)
1408		-#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7)
1409		-#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6)
1410		-#define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5)
1411		-#define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3)
1412		-#define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2)
1413		-#define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1)
1414		-#define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0)
	1404	+#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8)
	1405	+#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7)
	1406	+#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6)
	1407	+#define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5)
	1408	+#define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3)
	1409	+#define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2)
	1410	+#define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1)
	1411	+#define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0)
1415	1412
1416	1413	#define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
1417		-#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8)
1418		-#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7)
1419		-#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6)
1420		-#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5)
1421		-#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3)
1422		-#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2)
1423		-#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1)
1424		-#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0)
	1414	+#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8)
	1415	+#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7)
	1416	+#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6)
	1417	+#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5)
	1418	+#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3)
	1419	+#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2)
	1420	+#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1)
	1421	+#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0)
1425	1422
1426	1423	#define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
1427	1424	#define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5
..	..	@@ -1457,9 +1454,9 @@
1457	1454	(0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1458	1455
1459	1456	#define ISPCSIPHY_REG1 (0x004)
1460		-#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29)
	1457	+#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29)
1461	1458	/* This field is for OMAP3630 only */
1462		-#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25)
	1459	+#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25)
1463	1460	#define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18
1464	1461	#define ISPCSIPHY_REG1_TCLK_TERM_MASK \
1465	1462	(0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
..	..	@@ -1501,11 +1498,11 @@
1501	1498	*/
1502	1499
1503	1500	/* OMAP343X_CONTROL_CSIRXFE */
1504		-#define OMAP343X_CONTROL_CSIRXFE_CSIB_INV (1 << 7)
1505		-#define OMAP343X_CONTROL_CSIRXFE_RESENABLE (1 << 8)
1506		-#define OMAP343X_CONTROL_CSIRXFE_SELFORM (1 << 10)
1507		-#define OMAP343X_CONTROL_CSIRXFE_PWRDNZ (1 << 12)
1508		-#define OMAP343X_CONTROL_CSIRXFE_RESET (1 << 13)
	1501	+#define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7)
	1502	+#define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8)
	1503	+#define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10)
	1504	+#define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12)
	1505	+#define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13)
1509	1506
1510	1507	/* OMAP3630_CONTROL_CAMERA_PHY_CTRL */
1511	1508	#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2
..	..	@@ -1516,6 +1513,6 @@
1516	1513	#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3
1517	1514	#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3
1518	1515	/* CCP2B: set to receive data from PHY2 instead of PHY1 */
1519		-#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 (1 << 4)
	1516	+#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4)
1520	1517
1521	1518	#endif /* OMAP3_ISP_REG_H */