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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/media/platform/exynos4-is/fimc-reg.h
....@@ -1,22 +1,21 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Samsung camera host interface (FIMC) registers definition
34  *
45  * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 
118 #ifndef FIMC_REG_H_
129 #define FIMC_REG_H_
1310 
11
+#include <linux/bitops.h>
12
+
1413 #include "fimc-core.h"
1514 
1615 /* Input source format */
1716 #define FIMC_REG_CISRCFMT			0x00
18
-#define FIMC_REG_CISRCFMT_ITU601_8BIT		(1 << 31)
19
-#define FIMC_REG_CISRCFMT_ITU601_16BIT		(1 << 29)
17
+#define FIMC_REG_CISRCFMT_ITU601_8BIT		BIT(31)
18
+#define FIMC_REG_CISRCFMT_ITU601_16BIT		BIT(29)
2019 #define FIMC_REG_CISRCFMT_ORDER422_YCBYCR	(0 << 14)
2120 #define FIMC_REG_CISRCFMT_ORDER422_YCRYCB	(1 << 14)
2221 #define FIMC_REG_CISRCFMT_ORDER422_CBYCRY	(2 << 14)
....@@ -24,45 +23,45 @@
2423 
2524 /* Window offset */
2625 #define FIMC_REG_CIWDOFST			0x04
27
-#define FIMC_REG_CIWDOFST_OFF_EN		(1 << 31)
28
-#define FIMC_REG_CIWDOFST_CLROVFIY		(1 << 30)
29
-#define FIMC_REG_CIWDOFST_CLROVRLB		(1 << 29)
26
+#define FIMC_REG_CIWDOFST_OFF_EN		BIT(31)
27
+#define FIMC_REG_CIWDOFST_CLROVFIY		BIT(30)
28
+#define FIMC_REG_CIWDOFST_CLROVRLB		BIT(29)
3029 #define FIMC_REG_CIWDOFST_HOROFF_MASK		(0x7ff << 16)
31
-#define FIMC_REG_CIWDOFST_CLROVFICB		(1 << 15)
32
-#define FIMC_REG_CIWDOFST_CLROVFICR		(1 << 14)
30
+#define FIMC_REG_CIWDOFST_CLROVFICB		BIT(15)
31
+#define FIMC_REG_CIWDOFST_CLROVFICR		BIT(14)
3332 #define FIMC_REG_CIWDOFST_VEROFF_MASK		(0xfff << 0)
3433 
3534 /* Global control */
3635 #define FIMC_REG_CIGCTRL			0x08
37
-#define FIMC_REG_CIGCTRL_SWRST			(1 << 31)
38
-#define FIMC_REG_CIGCTRL_CAMRST_A		(1 << 30)
39
-#define FIMC_REG_CIGCTRL_SELCAM_ITU_A		(1 << 29)
36
+#define FIMC_REG_CIGCTRL_SWRST			BIT(31)
37
+#define FIMC_REG_CIGCTRL_CAMRST_A		BIT(30)
38
+#define FIMC_REG_CIGCTRL_SELCAM_ITU_A		BIT(29)
4039 #define FIMC_REG_CIGCTRL_TESTPAT_NORMAL		(0 << 27)
4140 #define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR	(1 << 27)
4241 #define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC	(2 << 27)
4342 #define FIMC_REG_CIGCTRL_TESTPAT_VER_INC	(3 << 27)
4443 #define FIMC_REG_CIGCTRL_TESTPAT_MASK		(3 << 27)
4544 #define FIMC_REG_CIGCTRL_TESTPAT_SHIFT		27
46
-#define FIMC_REG_CIGCTRL_INVPOLPCLK		(1 << 26)
47
-#define FIMC_REG_CIGCTRL_INVPOLVSYNC		(1 << 25)
48
-#define FIMC_REG_CIGCTRL_INVPOLHREF		(1 << 24)
49
-#define FIMC_REG_CIGCTRL_IRQ_OVFEN		(1 << 22)
50
-#define FIMC_REG_CIGCTRL_HREF_MASK		(1 << 21)
51
-#define FIMC_REG_CIGCTRL_IRQ_LEVEL		(1 << 20)
52
-#define FIMC_REG_CIGCTRL_IRQ_CLR		(1 << 19)
53
-#define FIMC_REG_CIGCTRL_IRQ_ENABLE		(1 << 16)
54
-#define FIMC_REG_CIGCTRL_SHDW_DISABLE		(1 << 12)
45
+#define FIMC_REG_CIGCTRL_INVPOLPCLK		BIT(26)
46
+#define FIMC_REG_CIGCTRL_INVPOLVSYNC		BIT(25)
47
+#define FIMC_REG_CIGCTRL_INVPOLHREF		BIT(24)
48
+#define FIMC_REG_CIGCTRL_IRQ_OVFEN		BIT(22)
49
+#define FIMC_REG_CIGCTRL_HREF_MASK		BIT(21)
50
+#define FIMC_REG_CIGCTRL_IRQ_LEVEL		BIT(20)
51
+#define FIMC_REG_CIGCTRL_IRQ_CLR		BIT(19)
52
+#define FIMC_REG_CIGCTRL_IRQ_ENABLE		BIT(16)
53
+#define FIMC_REG_CIGCTRL_SHDW_DISABLE		BIT(12)
5554 /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
56
-#define FIMC_REG_CIGCTRL_SELWB_A		(1 << 10)
57
-#define FIMC_REG_CIGCTRL_CAM_JPEG		(1 << 8)
58
-#define FIMC_REG_CIGCTRL_SELCAM_MIPI_A		(1 << 7)
59
-#define FIMC_REG_CIGCTRL_CAMIF_SELWB		(1 << 6)
55
+#define FIMC_REG_CIGCTRL_SELWB_A		BIT(10)
56
+#define FIMC_REG_CIGCTRL_CAM_JPEG		BIT(8)
57
+#define FIMC_REG_CIGCTRL_SELCAM_MIPI_A		BIT(7)
58
+#define FIMC_REG_CIGCTRL_CAMIF_SELWB		BIT(6)
6059 /* 0 - ITU601; 1 - ITU709 */
61
-#define FIMC_REG_CIGCTRL_CSC_ITU601_709		(1 << 5)
62
-#define FIMC_REG_CIGCTRL_INVPOLHSYNC		(1 << 4)
63
-#define FIMC_REG_CIGCTRL_SELCAM_MIPI		(1 << 3)
64
-#define FIMC_REG_CIGCTRL_INVPOLFIELD		(1 << 1)
65
-#define FIMC_REG_CIGCTRL_INTERLACE		(1 << 0)
60
+#define FIMC_REG_CIGCTRL_CSC_ITU601_709		BIT(5)
61
+#define FIMC_REG_CIGCTRL_INVPOLHSYNC		BIT(4)
62
+#define FIMC_REG_CIGCTRL_SELCAM_MIPI		BIT(3)
63
+#define FIMC_REG_CIGCTRL_INVPOLFIELD		BIT(1)
64
+#define FIMC_REG_CIGCTRL_INTERLACE		BIT(0)
6665 
6766 /* Window offset 2 */
6867 #define FIMC_REG_CIWDOFST2			0x14
....@@ -76,7 +75,7 @@
7675 
7776 /* Target image format */
7877 #define FIMC_REG_CITRGFMT			0x48
79
-#define FIMC_REG_CITRGFMT_INROT90		(1 << 31)
78
+#define FIMC_REG_CITRGFMT_INROT90		BIT(31)
8079 #define FIMC_REG_CITRGFMT_YCBCR420		(0 << 29)
8180 #define FIMC_REG_CITRGFMT_YCBCR422		(1 << 29)
8281 #define FIMC_REG_CITRGFMT_YCBCR422_1P		(2 << 29)
....@@ -89,7 +88,7 @@
8988 #define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR		(2 << 14)
9089 #define FIMC_REG_CITRGFMT_FLIP_180		(3 << 14)
9190 #define FIMC_REG_CITRGFMT_FLIP_MASK		(3 << 14)
92
-#define FIMC_REG_CITRGFMT_OUTROT90		(1 << 13)
91
+#define FIMC_REG_CITRGFMT_OUTROT90		BIT(13)
9392 #define FIMC_REG_CITRGFMT_VSIZE_MASK		(0xfff << 0)
9493 
9594 /* Output DMA control */
....@@ -99,7 +98,7 @@
9998 #define FIMC_REG_CIOCTRL_ORDER422_YCRYCB	(1 << 0)
10099 #define FIMC_REG_CIOCTRL_ORDER422_CBYCRY	(2 << 0)
101100 #define FIMC_REG_CIOCTRL_ORDER422_CRYCBY	(3 << 0)
102
-#define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE		(1 << 2)
101
+#define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE		BIT(2)
103102 #define FIMC_REG_CIOCTRL_YCBCR_3PLANE		(0 << 3)
104103 #define FIMC_REG_CIOCTRL_YCBCR_2PLANE		(1 << 3)
105104 #define FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK	(1 << 3)
....@@ -119,14 +118,14 @@
119118 
120119 /* Main scaler control */
121120 #define FIMC_REG_CISCCTRL			0x58
122
-#define FIMC_REG_CISCCTRL_SCALERBYPASS		(1 << 31)
123
-#define FIMC_REG_CISCCTRL_SCALEUP_H		(1 << 30)
124
-#define FIMC_REG_CISCCTRL_SCALEUP_V		(1 << 29)
125
-#define FIMC_REG_CISCCTRL_CSCR2Y_WIDE		(1 << 28)
126
-#define FIMC_REG_CISCCTRL_CSCY2R_WIDE		(1 << 27)
127
-#define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO	(1 << 26)
128
-#define FIMC_REG_CISCCTRL_INTERLACE		(1 << 25)
129
-#define FIMC_REG_CISCCTRL_SCALERSTART		(1 << 15)
121
+#define FIMC_REG_CISCCTRL_SCALERBYPASS		BIT(31)
122
+#define FIMC_REG_CISCCTRL_SCALEUP_H		BIT(30)
123
+#define FIMC_REG_CISCCTRL_SCALEUP_V		BIT(29)
124
+#define FIMC_REG_CISCCTRL_CSCR2Y_WIDE		BIT(28)
125
+#define FIMC_REG_CISCCTRL_CSCY2R_WIDE		BIT(27)
126
+#define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO	BIT(26)
127
+#define FIMC_REG_CISCCTRL_INTERLACE		BIT(25)
128
+#define FIMC_REG_CISCCTRL_SCALERSTART		BIT(15)
130129 #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB565	(0 << 13)
131130 #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB666	(1 << 13)
132131 #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB888	(2 << 13)
....@@ -135,8 +134,8 @@
135134 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666	(1 << 11)
136135 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888	(2 << 11)
137136 #define FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK	(3 << 11)
138
-#define FIMC_REG_CISCCTRL_RGB_EXT		(1 << 10)
139
-#define FIMC_REG_CISCCTRL_ONE2ONE		(1 << 9)
137
+#define FIMC_REG_CISCCTRL_RGB_EXT		BIT(10)
138
+#define FIMC_REG_CISCCTRL_ONE2ONE		BIT(9)
140139 #define FIMC_REG_CISCCTRL_MHRATIO(x)		((x) << 16)
141140 #define FIMC_REG_CISCCTRL_MVRATIO(x)		((x) << 0)
142141 #define FIMC_REG_CISCCTRL_MHRATIO_MASK		(0x1ff << 16)
....@@ -150,39 +149,39 @@
150149 
151150 /* General status */
152151 #define FIMC_REG_CISTATUS			0x64
153
-#define FIMC_REG_CISTATUS_OVFIY			(1 << 31)
154
-#define FIMC_REG_CISTATUS_OVFICB		(1 << 30)
155
-#define FIMC_REG_CISTATUS_OVFICR		(1 << 29)
156
-#define FIMC_REG_CISTATUS_VSYNC			(1 << 28)
152
+#define FIMC_REG_CISTATUS_OVFIY			BIT(31)
153
+#define FIMC_REG_CISTATUS_OVFICB		BIT(30)
154
+#define FIMC_REG_CISTATUS_OVFICR		BIT(29)
155
+#define FIMC_REG_CISTATUS_VSYNC			BIT(28)
157156 #define FIMC_REG_CISTATUS_FRAMECNT_MASK		(3 << 26)
158157 #define FIMC_REG_CISTATUS_FRAMECNT_SHIFT	26
159
-#define FIMC_REG_CISTATUS_WINOFF_EN		(1 << 25)
160
-#define FIMC_REG_CISTATUS_IMGCPT_EN		(1 << 22)
161
-#define FIMC_REG_CISTATUS_IMGCPT_SCEN		(1 << 21)
162
-#define FIMC_REG_CISTATUS_VSYNC_A		(1 << 20)
163
-#define FIMC_REG_CISTATUS_VSYNC_B		(1 << 19)
164
-#define FIMC_REG_CISTATUS_OVRLB			(1 << 18)
165
-#define FIMC_REG_CISTATUS_FRAME_END		(1 << 17)
166
-#define FIMC_REG_CISTATUS_LASTCAPT_END		(1 << 16)
167
-#define FIMC_REG_CISTATUS_VVALID_A		(1 << 15)
168
-#define FIMC_REG_CISTATUS_VVALID_B		(1 << 14)
158
+#define FIMC_REG_CISTATUS_WINOFF_EN		BIT(25)
159
+#define FIMC_REG_CISTATUS_IMGCPT_EN		BIT(22)
160
+#define FIMC_REG_CISTATUS_IMGCPT_SCEN		BIT(21)
161
+#define FIMC_REG_CISTATUS_VSYNC_A		BIT(20)
162
+#define FIMC_REG_CISTATUS_VSYNC_B		BIT(19)
163
+#define FIMC_REG_CISTATUS_OVRLB			BIT(18)
164
+#define FIMC_REG_CISTATUS_FRAME_END		BIT(17)
165
+#define FIMC_REG_CISTATUS_LASTCAPT_END		BIT(16)
166
+#define FIMC_REG_CISTATUS_VVALID_A		BIT(15)
167
+#define FIMC_REG_CISTATUS_VVALID_B		BIT(14)
169168 
170169 /* Indexes to the last and the currently processed buffer. */
171170 #define FIMC_REG_CISTATUS2			0x68
172171 
173172 /* Image capture control */
174173 #define FIMC_REG_CIIMGCPT			0xc0
175
-#define FIMC_REG_CIIMGCPT_IMGCPTEN		(1 << 31)
176
-#define FIMC_REG_CIIMGCPT_IMGCPTEN_SC		(1 << 30)
177
-#define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE	(1 << 25)
178
-#define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT		(1 << 18)
174
+#define FIMC_REG_CIIMGCPT_IMGCPTEN		BIT(31)
175
+#define FIMC_REG_CIIMGCPT_IMGCPTEN_SC		BIT(30)
176
+#define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE	BIT(25)
177
+#define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT		BIT(18)
179178 
180179 /* Frame capture sequence */
181180 #define FIMC_REG_CICPTSEQ			0xc4
182181 
183182 /* Image effect */
184183 #define FIMC_REG_CIIMGEFF			0xd0
185
-#define FIMC_REG_CIIMGEFF_IE_ENABLE		(1 << 30)
184
+#define FIMC_REG_CIIMGEFF_IE_ENABLE		BIT(30)
186185 #define FIMC_REG_CIIMGEFF_IE_SC_BEFORE		(0 << 29)
187186 #define FIMC_REG_CIIMGEFF_IE_SC_AFTER		(1 << 29)
188187 #define FIMC_REG_CIIMGEFF_FIN_BYPASS		(0 << 26)
....@@ -201,8 +200,8 @@
201200 
202201 /* Real input DMA image size */
203202 #define FIMC_REG_CIREAL_ISIZE			0xf8
204
-#define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN	(1 << 31)
205
-#define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS	(1 << 30)
203
+#define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN	BIT(31)
204
+#define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS	BIT(30)
206205 
207206 /* Input DMA control */
208207 #define FIMC_REG_MSCTRL				0xfc
....@@ -218,7 +217,7 @@
218217 #define FIMC_REG_MSCTRL_FLIP_X_MIRROR		(1 << 13)
219218 #define FIMC_REG_MSCTRL_FLIP_Y_MIRROR		(2 << 13)
220219 #define FIMC_REG_MSCTRL_FLIP_180		(3 << 13)
221
-#define FIMC_REG_MSCTRL_FIFO_CTRL_FULL		(1 << 12)
220
+#define FIMC_REG_MSCTRL_FIFO_CTRL_FULL		BIT(12)
222221 #define FIMC_REG_MSCTRL_ORDER422_SHIFT		4
223222 #define FIMC_REG_MSCTRL_ORDER422_CRYCBY		(0 << 4)
224223 #define FIMC_REG_MSCTRL_ORDER422_YCRYCB		(1 << 4)
....@@ -226,14 +225,14 @@
226225 #define FIMC_REG_MSCTRL_ORDER422_YCBYCR		(3 << 4)
227226 #define FIMC_REG_MSCTRL_ORDER422_MASK		(3 << 4)
228227 #define FIMC_REG_MSCTRL_INPUT_EXTCAM		(0 << 3)
229
-#define FIMC_REG_MSCTRL_INPUT_MEMORY		(1 << 3)
230
-#define FIMC_REG_MSCTRL_INPUT_MASK		(1 << 3)
228
+#define FIMC_REG_MSCTRL_INPUT_MEMORY		BIT(3)
229
+#define FIMC_REG_MSCTRL_INPUT_MASK		BIT(3)
231230 #define FIMC_REG_MSCTRL_INFORMAT_YCBCR420	(0 << 1)
232231 #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422	(1 << 1)
233232 #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P	(2 << 1)
234233 #define FIMC_REG_MSCTRL_INFORMAT_RGB		(3 << 1)
235234 #define FIMC_REG_MSCTRL_INFORMAT_MASK		(3 << 1)
236
-#define FIMC_REG_MSCTRL_ENVID			(1 << 0)
235
+#define FIMC_REG_MSCTRL_ENVID			BIT(0)
237236 #define FIMC_REG_MSCTRL_IN_BURST_COUNT(x)	((x) << 24)
238237 
239238 /* Output DMA Y/Cb/Cr offset */
....@@ -280,10 +279,10 @@
280279 
281280 /* SYSREG ISP Writeback register address offsets */
282281 #define SYSREG_ISPBLK				0x020c
283
-#define SYSREG_ISPBLK_FIFORST_CAM_BLK		(1 << 7)
282
+#define SYSREG_ISPBLK_FIFORST_CAM_BLK		BIT(7)
284283 
285284 #define SYSREG_CAMBLK				0x0218
286
-#define SYSREG_CAMBLK_FIFORST_ISP		(1 << 15)
285
+#define SYSREG_CAMBLK_FIFORST_ISP		BIT(15)
287286 #define SYSREG_CAMBLK_ISPWB_FULL_EN		(7 << 20)
288287 
289288 /*