hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/media/platform/atmel/atmel-isc-regs.h
....@@ -24,6 +24,8 @@
2424 #define ISC_PFE_CFG0_HPOL_LOW BIT(0)
2525 #define ISC_PFE_CFG0_VPOL_LOW BIT(1)
2626 #define ISC_PFE_CFG0_PPOL_LOW BIT(2)
27
+#define ISC_PFE_CFG0_CCIR656 BIT(9)
28
+#define ISC_PFE_CFG0_CCIR_CRC BIT(10)
2729
2830 #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4)
2931 #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)
....@@ -34,6 +36,25 @@
3436 #define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
3537 #define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
3638 #define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)
39
+
40
+#define ISC_PFE_CFG0_COLEN BIT(12)
41
+#define ISC_PFE_CFG0_ROWEN BIT(13)
42
+
43
+/* ISC Parallel Front End Configuration 1 Register */
44
+#define ISC_PFE_CFG1 0x00000010
45
+
46
+#define ISC_PFE_CFG1_COLMIN(v) ((v))
47
+#define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0)
48
+#define ISC_PFE_CFG1_COLMAX(v) ((v) << 16)
49
+#define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16)
50
+
51
+/* ISC Parallel Front End Configuration 2 Register */
52
+#define ISC_PFE_CFG2 0x00000014
53
+
54
+#define ISC_PFE_CFG2_ROWMIN(v) ((v))
55
+#define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0)
56
+#define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16)
57
+#define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16)
3758
3859 /* ISC Clock Enable Register */
3960 #define ISC_CLKEN 0x00000018
....@@ -79,13 +100,13 @@
79100 #define ISC_WB_O_RGR 0x00000060
80101
81102 /* ISC White Balance Offset for B, GB Register */
82
-#define ISC_WB_O_BGR 0x00000064
103
+#define ISC_WB_O_BGB 0x00000064
83104
84105 /* ISC White Balance Gain for R, GR Register */
85106 #define ISC_WB_G_RGR 0x00000068
86107
87108 /* ISC White Balance Gain for B, GB Register */
88
-#define ISC_WB_G_BGR 0x0000006c
109
+#define ISC_WB_G_BGB 0x0000006c
89110
90111 /* ISC Color Filter Array Control Register */
91112 #define ISC_CFA_CTRL 0x00000070