hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/media/pci/ivtv/ivtv-irq.h
....@@ -1,41 +1,29 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23 interrupt handling
34 Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
45 Copyright (C) 2004 Chris Kennedy <c@groovy.org>
56 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
67
7
- This program is free software; you can redistribute it and/or modify
8
- it under the terms of the GNU General Public License as published by
9
- the Free Software Foundation; either version 2 of the License, or
10
- (at your option) any later version.
11
-
12
- This program is distributed in the hope that it will be useful,
13
- but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
- GNU General Public License for more details.
16
-
17
- You should have received a copy of the GNU General Public License
18
- along with this program; if not, write to the Free Software
19
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
208 */
219
2210 #ifndef IVTV_IRQ_H
2311 #define IVTV_IRQ_H
2412
25
-#define IVTV_IRQ_ENC_START_CAP (0x1 << 31)
26
-#define IVTV_IRQ_ENC_EOS (0x1 << 30)
27
-#define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29)
28
-#define IVTV_IRQ_ENC_VIM_RST (0x1 << 28)
29
-#define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27)
30
-#define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25)
31
-#define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24)
32
-#define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22)
33
-#define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20)
34
-#define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19)
35
-#define IVTV_IRQ_DMA_ERR (0x1 << 18)
36
-#define IVTV_IRQ_DMA_WRITE (0x1 << 17)
37
-#define IVTV_IRQ_DMA_READ (0x1 << 16)
38
-#define IVTV_IRQ_DEC_VSYNC (0x1 << 10)
13
+#define IVTV_IRQ_ENC_START_CAP BIT(31)
14
+#define IVTV_IRQ_ENC_EOS BIT(30)
15
+#define IVTV_IRQ_ENC_VBI_CAP BIT(29)
16
+#define IVTV_IRQ_ENC_VIM_RST BIT(28)
17
+#define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27)
18
+#define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25)
19
+#define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24)
20
+#define IVTV_IRQ_DEC_DATA_REQ BIT(22)
21
+#define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20)
22
+#define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19)
23
+#define IVTV_IRQ_DMA_ERR BIT(18)
24
+#define IVTV_IRQ_DMA_WRITE BIT(17)
25
+#define IVTV_IRQ_DMA_READ BIT(16)
26
+#define IVTV_IRQ_DEC_VSYNC BIT(10)
3927
4028 /* IRQ Masks */
4129 #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\