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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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1 | 2 | /* |
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2 | 3 | interrupt handling |
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3 | 4 | Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com> |
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4 | 5 | Copyright (C) 2004 Chris Kennedy <c@groovy.org> |
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5 | 6 | Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> |
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6 | 7 | |
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7 | | - This program is free software; you can redistribute it and/or modify |
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8 | | - it under the terms of the GNU General Public License as published by |
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9 | | - the Free Software Foundation; either version 2 of the License, or |
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10 | | - (at your option) any later version. |
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11 | | - |
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12 | | - This program is distributed in the hope that it will be useful, |
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13 | | - but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | | - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | | - GNU General Public License for more details. |
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16 | | - |
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17 | | - You should have received a copy of the GNU General Public License |
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18 | | - along with this program; if not, write to the Free Software |
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19 | | - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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20 | 8 | */ |
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21 | 9 | |
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22 | 10 | #ifndef IVTV_IRQ_H |
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23 | 11 | #define IVTV_IRQ_H |
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24 | 12 | |
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25 | | -#define IVTV_IRQ_ENC_START_CAP (0x1 << 31) |
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26 | | -#define IVTV_IRQ_ENC_EOS (0x1 << 30) |
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27 | | -#define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) |
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28 | | -#define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) |
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29 | | -#define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) |
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30 | | -#define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) |
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31 | | -#define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) |
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32 | | -#define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) |
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33 | | -#define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) |
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34 | | -#define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19) |
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35 | | -#define IVTV_IRQ_DMA_ERR (0x1 << 18) |
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36 | | -#define IVTV_IRQ_DMA_WRITE (0x1 << 17) |
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37 | | -#define IVTV_IRQ_DMA_READ (0x1 << 16) |
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38 | | -#define IVTV_IRQ_DEC_VSYNC (0x1 << 10) |
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| 13 | +#define IVTV_IRQ_ENC_START_CAP BIT(31) |
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| 14 | +#define IVTV_IRQ_ENC_EOS BIT(30) |
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| 15 | +#define IVTV_IRQ_ENC_VBI_CAP BIT(29) |
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| 16 | +#define IVTV_IRQ_ENC_VIM_RST BIT(28) |
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| 17 | +#define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27) |
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| 18 | +#define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25) |
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| 19 | +#define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24) |
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| 20 | +#define IVTV_IRQ_DEC_DATA_REQ BIT(22) |
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| 21 | +#define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20) |
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| 22 | +#define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19) |
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| 23 | +#define IVTV_IRQ_DMA_ERR BIT(18) |
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| 24 | +#define IVTV_IRQ_DMA_WRITE BIT(17) |
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| 25 | +#define IVTV_IRQ_DMA_READ BIT(16) |
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| 26 | +#define IVTV_IRQ_DEC_VSYNC BIT(10) |
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39 | 27 | |
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40 | 28 | /* IRQ Masks */ |
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41 | 29 | #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ |
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