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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/media/i2c/ov5640.c
....@@ -1,11 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
34  * Copyright (C) 2014-2017 Mentor Graphics Inc.
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
95  */
106 
117 #include <linux/clk.h>
....@@ -25,6 +21,7 @@
2521 #include <media/v4l2-async.h>
2622 #include <media/v4l2-ctrls.h>
2723 #include <media/v4l2-device.h>
24
+#include <media/v4l2-event.h>
2825 #include <media/v4l2-fwnode.h>
2926 #include <media/v4l2-subdev.h>
3027 
....@@ -37,6 +34,8 @@
3734 #define OV5640_REG_SYS_RESET02		0x3002
3835 #define OV5640_REG_SYS_CLOCK_ENABLE02	0x3006
3936 #define OV5640_REG_SYS_CTRL0		0x3008
37
+#define OV5640_REG_SYS_CTRL0_SW_PWDN	0x42
38
+#define OV5640_REG_SYS_CTRL0_SW_PWUP	0x02
4039 #define OV5640_REG_CHIP_ID		0x300a
4140 #define OV5640_REG_IO_MIPI_CTRL00	0x300e
4241 #define OV5640_REG_PAD_OUTPUT_ENABLE01	0x3017
....@@ -82,6 +81,10 @@
8281 #define OV5640_REG_SIGMADELTA_CTRL0C	0x3c0c
8382 #define OV5640_REG_FRAME_CTRL01		0x4202
8483 #define OV5640_REG_FORMAT_CONTROL00	0x4300
84
+#define OV5640_REG_VFIFO_HSIZE		0x4602
85
+#define OV5640_REG_VFIFO_VSIZE		0x4604
86
+#define OV5640_REG_JPG_MODE_SELECT	0x4713
87
+#define OV5640_REG_CCIR656_CTRL00	0x4730
8588 #define OV5640_REG_POLARITY_CTRL00	0x4740
8689 #define OV5640_REG_MIPI_CTRL00		0x4800
8790 #define OV5640_REG_DEBUG_MODE		0x4814
....@@ -93,9 +96,6 @@
9396 #define OV5640_REG_SDE_CTRL4		0x5584
9497 #define OV5640_REG_SDE_CTRL5		0x5585
9598 #define OV5640_REG_AVG_READOUT		0x56a1
96
-
97
-#define OV5640_SCLK2X_ROOT_DIVIDER_DEFAULT	1
98
-#define OV5640_SCLK_ROOT_DIVIDER_DEFAULT	2
9999 
100100 enum ov5640_mode_id {
101101 	OV5640_MODE_QCIF_176_144 = 0,
....@@ -113,7 +113,17 @@
113113 enum ov5640_frame_rate {
114114 	OV5640_15_FPS = 0,
115115 	OV5640_30_FPS,
116
+	OV5640_60_FPS,
116117 	OV5640_NUM_FRAMERATES,
118
+};
119
+
120
+enum ov5640_format_mux {
121
+	OV5640_FMT_MUX_YUV422 = 0,
122
+	OV5640_FMT_MUX_RGB,
123
+	OV5640_FMT_MUX_DITHER,
124
+	OV5640_FMT_MUX_RAW_DPC,
125
+	OV5640_FMT_MUX_SNR_RAW,
126
+	OV5640_FMT_MUX_RAW_CIP,
117127 };
118128 
119129 struct ov5640_pixfmt {
....@@ -127,6 +137,10 @@
127137 	{ MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB, },
128138 	{ MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB, },
129139 	{ MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB, },
140
+	{ MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB, },
141
+	{ MEDIA_BUS_FMT_SGBRG8_1X8, V4L2_COLORSPACE_SRGB, },
142
+	{ MEDIA_BUS_FMT_SGRBG8_1X8, V4L2_COLORSPACE_SRGB, },
143
+	{ MEDIA_BUS_FMT_SRGGB8_1X8, V4L2_COLORSPACE_SRGB, },
130144 };
131145 
132146 /*
....@@ -141,13 +155,14 @@
141155 static const int ov5640_framerates[] = {
142156 	[OV5640_15_FPS] = 15,
143157 	[OV5640_30_FPS] = 30,
158
+	[OV5640_60_FPS] = 60,
144159 };
145160 
146161 /* regulator supplies */
147162 static const char * const ov5640_supply_name[] = {
148163 	"DOVDD", /* Digital I/O (1.8V) supply */
149
-	"DVDD",  /* Digital Core (1.5V) supply */
150164 	"AVDD",  /* Analog (2.8V) supply */
165
+	"DVDD",  /* Digital Core (1.5V) supply */
151166 };
152167 
153168 #define OV5640_NUM_SUPPLIES ARRAY_SIZE(ov5640_supply_name)
....@@ -177,10 +192,12 @@
177192 	u32 vtot;
178193 	const struct reg_value *reg_data;
179194 	u32 reg_data_size;
195
+	u32 max_fps;
180196 };
181197 
182198 struct ov5640_ctrls {
183199 	struct v4l2_ctrl_handler handler;
200
+	struct v4l2_ctrl *pixel_rate;
184201 	struct {
185202 		struct v4l2_ctrl *auto_exp;
186203 		struct v4l2_ctrl *exposure;
....@@ -260,9 +277,7 @@
260277 /* YUV422 UYVY VGA@30fps */
261278 static const struct reg_value ov5640_init_setting_30fps_VGA[] = {
262279 	{0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0},
263
-	{0x3103, 0x03, 0, 0}, {0x3017, 0x00, 0, 0}, {0x3018, 0x00, 0, 0},
264
-	{0x3034, 0x18, 0, 0}, {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0},
265
-	{0x3037, 0x13, 0, 0}, {0x3630, 0x36, 0, 0},
280
+	{0x3103, 0x03, 0, 0}, {0x3630, 0x36, 0, 0},
266281 	{0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
267282 	{0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
268283 	{0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
....@@ -289,7 +304,7 @@
289304 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
290305 	{0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
291306 	{0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0},
292
-	{0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
307
+	{0x501f, 0x00, 0, 0}, {0x4407, 0x04, 0, 0},
293308 	{0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
294309 	{0x4837, 0x0a, 0, 0}, {0x3824, 0x02, 0, 0},
295310 	{0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0},
....@@ -344,27 +359,8 @@
344359 	{0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300},
345360 };
346361 
347
-static const struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
348
-	{0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
349
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
350
-	{0x3814, 0x31, 0, 0},
351
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
352
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
353
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
354
-	{0x3810, 0x00, 0, 0},
355
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
356
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
357
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
358
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0},
359
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
360
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
361
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
362
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
363
-	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0},
364
-};
365
-
366
-static const struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
367
-	{0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
362
+static const struct reg_value ov5640_setting_VGA_640_480[] = {
363
+	{0x3c07, 0x08, 0, 0},
368364 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
369365 	{0x3814, 0x31, 0, 0},
370366 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -377,33 +373,13 @@
377373 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
378374 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
379375 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
380
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
376
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
381377 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
382378 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
383379 };
384380 
385
-static const struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
386
-	{0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
387
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
388
-	{0x3814, 0x31, 0, 0},
389
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
390
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
391
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
392
-	{0x3810, 0x00, 0, 0},
393
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
394
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
395
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
396
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0},
397
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
398
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
399
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
400
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
401
-	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0},
402
-	{0x3035, 0x12, 0, 0},
403
-};
404
-
405
-static const struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
406
-	{0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
381
+static const struct reg_value ov5640_setting_XGA_1024_768[] = {
382
+	{0x3c07, 0x08, 0, 0},
407383 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
408384 	{0x3814, 0x31, 0, 0},
409385 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -416,13 +392,13 @@
416392 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
417393 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
418394 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
419
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
395
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
420396 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
421397 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
422398 };
423399 
424
-static const struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {
425
-	{0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
400
+static const struct reg_value ov5640_setting_QVGA_320_240[] = {
401
+	{0x3c07, 0x08, 0, 0},
426402 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
427403 	{0x3814, 0x31, 0, 0},
428404 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -435,13 +411,13 @@
435411 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
436412 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
437413 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
438
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
414
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
439415 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
440416 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
441417 };
442418 
443
-static const struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
444
-	{0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
419
+static const struct reg_value ov5640_setting_QCIF_176_144[] = {
420
+	{0x3c07, 0x08, 0, 0},
445421 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
446422 	{0x3814, 0x31, 0, 0},
447423 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -454,51 +430,13 @@
454430 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
455431 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
456432 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
457
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
433
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
458434 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
459435 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
460436 };
461437 
462
-static const struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
463
-	{0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
464
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
465
-	{0x3814, 0x31, 0, 0},
466
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
467
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
468
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
469
-	{0x3810, 0x00, 0, 0},
470
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
471
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
472
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
473
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
474
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
475
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
476
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
477
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
478
-	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
479
-};
480
-
481
-static const struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
482
-	{0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
483
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
484
-	{0x3814, 0x31, 0, 0},
485
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
486
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
487
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
488
-	{0x3810, 0x00, 0, 0},
489
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
490
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
491
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
492
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
493
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
494
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
495
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
496
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
497
-	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
498
-};
499
-
500
-static const struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
501
-	{0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
438
+static const struct reg_value ov5640_setting_NTSC_720_480[] = {
439
+	{0x3c07, 0x08, 0, 0},
502440 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
503441 	{0x3814, 0x31, 0, 0},
504442 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -511,32 +449,13 @@
511449 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
512450 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
513451 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
514
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
452
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
515453 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
516454 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
517455 };
518456 
519
-static const struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
520
-	{0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
521
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
522
-	{0x3814, 0x31, 0, 0},
523
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
524
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
525
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
526
-	{0x3810, 0x00, 0, 0},
527
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
528
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
529
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
530
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
531
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
532
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
533
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
534
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
535
-	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
536
-};
537
-
538
-static const struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
539
-	{0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
457
+static const struct reg_value ov5640_setting_PAL_720_576[] = {
458
+	{0x3c07, 0x08, 0, 0},
540459 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
541460 	{0x3814, 0x31, 0, 0},
542461 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -549,33 +468,13 @@
549468 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
550469 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
551470 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
552
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
471
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
553472 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
554473 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
555474 };
556475 
557
-static const struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
558
-	{0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
559
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
560
-	{0x3814, 0x31, 0, 0},
561
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
562
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
563
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
564
-	{0x3810, 0x00, 0, 0},
565
-	{0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
566
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
567
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
568
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
569
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
570
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
571
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
572
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
573
-	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
574
-};
575
-
576
-static const struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
577
-	{0x3008, 0x42, 0, 0},
578
-	{0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0},
476
+static const struct reg_value ov5640_setting_720P_1280_720[] = {
477
+	{0x3c07, 0x07, 0, 0},
579478 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
580479 	{0x3814, 0x31, 0, 0},
581480 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -588,34 +487,13 @@
588487 	{0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
589488 	{0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
590489 	{0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
591
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0},
592
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
593
-	{0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, {0x4005, 0x1a, 0, 0},
594
-	{0x3008, 0x02, 0, 0}, {0x3503, 0,    0, 0},
595
-};
596
-
597
-static const struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
598
-	{0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0},
599
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
600
-	{0x3814, 0x31, 0, 0},
601
-	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
602
-	{0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
603
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
604
-	{0x3810, 0x00, 0, 0},
605
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
606
-	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
607
-	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
608
-	{0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
609
-	{0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
610
-	{0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
611
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0},
490
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
612491 	{0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
613492 	{0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
614493 };
615494 
616
-static const struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = {
617
-	{0x3008, 0x42, 0, 0},
618
-	{0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
495
+static const struct reg_value ov5640_setting_1080P_1920_1080[] = {
496
+	{0x3c07, 0x08, 0, 0},
619497 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
620498 	{0x3814, 0x11, 0, 0},
621499 	{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -628,10 +506,10 @@
628506 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
629507 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
630508 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
631
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
509
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0},
632510 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
633
-	{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x11, 0, 0},
634
-	{0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
511
+	{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0},
512
+	{0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
635513 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
636514 	{0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
637515 	{0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
....@@ -640,15 +518,13 @@
640518 	{0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
641519 	{0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
642520 	{0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
643
-	{0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
521
+	{0x3a15, 0x60, 0, 0}, {0x4407, 0x04, 0, 0},
644522 	{0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
645
-	{0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0},
646
-	{0x3503, 0, 0, 0},
523
+	{0x4005, 0x1a, 0, 0},
647524 };
648525 
649
-static const struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
650
-	{0x3008, 0x42, 0, 0},
651
-	{0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
526
+static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {
527
+	{0x3c07, 0x08, 0, 0},
652528 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
653529 	{0x3814, 0x11, 0, 0},
654530 	{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
....@@ -661,38 +537,7 @@
661537 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
662538 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
663539 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
664
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
665
-	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
666
-	{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0},
667
-	{0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
668
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
669
-	{0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
670
-	{0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
671
-	{0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0},
672
-	{0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
673
-	{0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
674
-	{0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
675
-	{0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
676
-	{0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
677
-	{0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
678
-	{0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0},
679
-};
680
-
681
-static const struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
682
-	{0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
683
-	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
684
-	{0x3814, 0x11, 0, 0},
685
-	{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
686
-	{0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
687
-	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
688
-	{0x3810, 0x00, 0, 0},
689
-	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
690
-	{0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
691
-	{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
692
-	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
693
-	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
694
-	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
695
-	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
540
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0},
696541 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
697542 	{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70},
698543 };
....@@ -702,82 +547,56 @@
702547 	0, SUBSAMPLING, 640, 1896, 480, 984,
703548 	ov5640_init_setting_30fps_VGA,
704549 	ARRAY_SIZE(ov5640_init_setting_30fps_VGA),
550
+	OV5640_30_FPS,
705551 };
706552 
707553 static const struct ov5640_mode_info
708
-ov5640_mode_data[OV5640_NUM_FRAMERATES][OV5640_NUM_MODES] = {
709
-	{
710
-		{OV5640_MODE_QCIF_176_144, SUBSAMPLING,
711
-		 176, 1896, 144, 984,
712
-		 ov5640_setting_15fps_QCIF_176_144,
713
-		 ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
714
-		{OV5640_MODE_QVGA_320_240, SUBSAMPLING,
715
-		 320, 1896, 240, 984,
716
-		 ov5640_setting_15fps_QVGA_320_240,
717
-		 ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
718
-		{OV5640_MODE_VGA_640_480, SUBSAMPLING,
719
-		 640, 1896, 480, 1080,
720
-		 ov5640_setting_15fps_VGA_640_480,
721
-		 ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
722
-		{OV5640_MODE_NTSC_720_480, SUBSAMPLING,
723
-		 720, 1896, 480, 984,
724
-		 ov5640_setting_15fps_NTSC_720_480,
725
-		 ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
726
-		{OV5640_MODE_PAL_720_576, SUBSAMPLING,
727
-		 720, 1896, 576, 984,
728
-		 ov5640_setting_15fps_PAL_720_576,
729
-		 ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
730
-		{OV5640_MODE_XGA_1024_768, SUBSAMPLING,
731
-		 1024, 1896, 768, 1080,
732
-		 ov5640_setting_15fps_XGA_1024_768,
733
-		 ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
734
-		{OV5640_MODE_720P_1280_720, SUBSAMPLING,
735
-		 1280, 1892, 720, 740,
736
-		 ov5640_setting_15fps_720P_1280_720,
737
-		 ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
738
-		{OV5640_MODE_1080P_1920_1080, SCALING,
739
-		 1920, 2500, 1080, 1120,
740
-		 ov5640_setting_15fps_1080P_1920_1080,
741
-		 ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
742
-		{OV5640_MODE_QSXGA_2592_1944, SCALING,
743
-		 2592, 2844, 1944, 1968,
744
-		 ov5640_setting_15fps_QSXGA_2592_1944,
745
-		 ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
746
-	}, {
747
-		{OV5640_MODE_QCIF_176_144, SUBSAMPLING,
748
-		 176, 1896, 144, 984,
749
-		 ov5640_setting_30fps_QCIF_176_144,
750
-		 ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
751
-		{OV5640_MODE_QVGA_320_240, SUBSAMPLING,
752
-		 320, 1896, 240, 984,
753
-		 ov5640_setting_30fps_QVGA_320_240,
754
-		 ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
755
-		{OV5640_MODE_VGA_640_480, SUBSAMPLING,
756
-		 640, 1896, 480, 1080,
757
-		 ov5640_setting_30fps_VGA_640_480,
758
-		 ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
759
-		{OV5640_MODE_NTSC_720_480, SUBSAMPLING,
760
-		 720, 1896, 480, 984,
761
-		 ov5640_setting_30fps_NTSC_720_480,
762
-		 ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
763
-		{OV5640_MODE_PAL_720_576, SUBSAMPLING,
764
-		 720, 1896, 576, 984,
765
-		 ov5640_setting_30fps_PAL_720_576,
766
-		 ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
767
-		{OV5640_MODE_XGA_1024_768, SUBSAMPLING,
768
-		 1024, 1896, 768, 1080,
769
-		 ov5640_setting_30fps_XGA_1024_768,
770
-		 ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
771
-		{OV5640_MODE_720P_1280_720, SUBSAMPLING,
772
-		 1280, 1892, 720, 740,
773
-		 ov5640_setting_30fps_720P_1280_720,
774
-		 ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
775
-		{OV5640_MODE_1080P_1920_1080, SCALING,
776
-		 1920, 2500, 1080, 1120,
777
-		 ov5640_setting_30fps_1080P_1920_1080,
778
-		 ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)},
779
-		{OV5640_MODE_QSXGA_2592_1944, -1, 0, 0, 0, 0, NULL, 0},
780
-	},
554
+ov5640_mode_data[OV5640_NUM_MODES] = {
555
+	{OV5640_MODE_QCIF_176_144, SUBSAMPLING,
556
+	 176, 1896, 144, 984,
557
+	 ov5640_setting_QCIF_176_144,
558
+	 ARRAY_SIZE(ov5640_setting_QCIF_176_144),
559
+	 OV5640_30_FPS},
560
+	{OV5640_MODE_QVGA_320_240, SUBSAMPLING,
561
+	 320, 1896, 240, 984,
562
+	 ov5640_setting_QVGA_320_240,
563
+	 ARRAY_SIZE(ov5640_setting_QVGA_320_240),
564
+	 OV5640_30_FPS},
565
+	{OV5640_MODE_VGA_640_480, SUBSAMPLING,
566
+	 640, 1896, 480, 1080,
567
+	 ov5640_setting_VGA_640_480,
568
+	 ARRAY_SIZE(ov5640_setting_VGA_640_480),
569
+	 OV5640_60_FPS},
570
+	{OV5640_MODE_NTSC_720_480, SUBSAMPLING,
571
+	 720, 1896, 480, 984,
572
+	 ov5640_setting_NTSC_720_480,
573
+	 ARRAY_SIZE(ov5640_setting_NTSC_720_480),
574
+	OV5640_30_FPS},
575
+	{OV5640_MODE_PAL_720_576, SUBSAMPLING,
576
+	 720, 1896, 576, 984,
577
+	 ov5640_setting_PAL_720_576,
578
+	 ARRAY_SIZE(ov5640_setting_PAL_720_576),
579
+	 OV5640_30_FPS},
580
+	{OV5640_MODE_XGA_1024_768, SUBSAMPLING,
581
+	 1024, 1896, 768, 1080,
582
+	 ov5640_setting_XGA_1024_768,
583
+	 ARRAY_SIZE(ov5640_setting_XGA_1024_768),
584
+	 OV5640_30_FPS},
585
+	{OV5640_MODE_720P_1280_720, SUBSAMPLING,
586
+	 1280, 1892, 720, 740,
587
+	 ov5640_setting_720P_1280_720,
588
+	 ARRAY_SIZE(ov5640_setting_720P_1280_720),
589
+	 OV5640_30_FPS},
590
+	{OV5640_MODE_1080P_1920_1080, SCALING,
591
+	 1920, 2500, 1080, 1120,
592
+	 ov5640_setting_1080P_1920_1080,
593
+	 ARRAY_SIZE(ov5640_setting_1080P_1920_1080),
594
+	 OV5640_30_FPS},
595
+	{OV5640_MODE_QSXGA_2592_1944, SCALING,
596
+	 2592, 2844, 1944, 1968,
597
+	 ov5640_setting_QSXGA_2592_1944,
598
+	 ARRAY_SIZE(ov5640_setting_QSXGA_2592_1944),
599
+	 OV5640_15_FPS},
781600 };
782601 
783602 static int ov5640_init_slave_id(struct ov5640_dev *sensor)
....@@ -909,11 +728,368 @@
909728 	return ov5640_write_reg(sensor, reg, val);
910729 }
911730 
731
+/*
732
+ * After trying the various combinations, reading various
733
+ * documentations spread around the net, and from the various
734
+ * feedback, the clock tree is probably as follows:
735
+ *
736
+ *   +--------------+
737
+ *   |  Ext. Clock  |
738
+ *   +-+------------+
739
+ *     |  +----------+
740
+ *     +->|   PLL1   | - reg 0x3036, for the multiplier
741
+ *        +-+--------+ - reg 0x3037, bits 0-3 for the pre-divider
742
+ *          |  +--------------+
743
+ *          +->| System Clock |  - reg 0x3035, bits 4-7
744
+ *             +-+------------+
745
+ *               |  +--------------+
746
+ *               +->| MIPI Divider | - reg 0x3035, bits 0-3
747
+ *               |  +-+------------+
748
+ *               |    +----------------> MIPI SCLK
749
+ *               |    +  +-----+
750
+ *               |    +->| / 2 |-------> MIPI BIT CLK
751
+ *               |       +-----+
752
+ *               |  +--------------+
753
+ *               +->| PLL Root Div | - reg 0x3037, bit 4
754
+ *                  +-+------------+
755
+ *                    |  +---------+
756
+ *                    +->| Bit Div | - reg 0x3034, bits 0-3
757
+ *                       +-+-------+
758
+ *                         |  +-------------+
759
+ *                         +->| SCLK Div    | - reg 0x3108, bits 0-1
760
+ *                         |  +-+-----------+
761
+ *                         |    +---------------> SCLK
762
+ *                         |  +-------------+
763
+ *                         +->| SCLK 2X Div | - reg 0x3108, bits 2-3
764
+ *                         |  +-+-----------+
765
+ *                         |    +---------------> SCLK 2X
766
+ *                         |  +-------------+
767
+ *                         +->| PCLK Div    | - reg 0x3108, bits 4-5
768
+ *                            ++------------+
769
+ *                             +  +-----------+
770
+ *                             +->|   P_DIV   | - reg 0x3035, bits 0-3
771
+ *                                +-----+-----+
772
+ *                                       +------------> PCLK
773
+ *
774
+ * This is deviating from the datasheet at least for the register
775
+ * 0x3108, since it's said here that the PCLK would be clocked from
776
+ * the PLL.
777
+ *
778
+ * There seems to be also (unverified) constraints:
779
+ *  - the PLL pre-divider output rate should be in the 4-27MHz range
780
+ *  - the PLL multiplier output rate should be in the 500-1000MHz range
781
+ *  - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG
782
+ *
783
+ * In the two latter cases, these constraints are met since our
784
+ * factors are hardcoded. If we were to change that, we would need to
785
+ * take this into account. The only varying parts are the PLL
786
+ * multiplier and the system clock divider, which are shared between
787
+ * all these clocks so won't cause any issue.
788
+ */
789
+
790
+/*
791
+ * This is supposed to be ranging from 1 to 8, but the value is always
792
+ * set to 3 in the vendor kernels.
793
+ */
794
+#define OV5640_PLL_PREDIV	3
795
+
796
+#define OV5640_PLL_MULT_MIN	4
797
+#define OV5640_PLL_MULT_MAX	252
798
+
799
+/*
800
+ * This is supposed to be ranging from 1 to 16, but the value is
801
+ * always set to either 1 or 2 in the vendor kernels.
802
+ */
803
+#define OV5640_SYSDIV_MIN	1
804
+#define OV5640_SYSDIV_MAX	16
805
+
806
+/*
807
+ * Hardcode these values for scaler and non-scaler modes.
808
+ * FIXME: to be re-calcualted for 1 data lanes setups
809
+ */
810
+#define OV5640_MIPI_DIV_PCLK	2
811
+#define OV5640_MIPI_DIV_SCLK	1
812
+
813
+/*
814
+ * This is supposed to be ranging from 1 to 2, but the value is always
815
+ * set to 2 in the vendor kernels.
816
+ */
817
+#define OV5640_PLL_ROOT_DIV			2
818
+#define OV5640_PLL_CTRL3_PLL_ROOT_DIV_2		BIT(4)
819
+
820
+/*
821
+ * We only supports 8-bit formats at the moment
822
+ */
823
+#define OV5640_BIT_DIV				2
824
+#define OV5640_PLL_CTRL0_MIPI_MODE_8BIT		0x08
825
+
826
+/*
827
+ * This is supposed to be ranging from 1 to 8, but the value is always
828
+ * set to 2 in the vendor kernels.
829
+ */
830
+#define OV5640_SCLK_ROOT_DIV	2
831
+
832
+/*
833
+ * This is hardcoded so that the consistency is maintained between SCLK and
834
+ * SCLK 2x.
835
+ */
836
+#define OV5640_SCLK2X_ROOT_DIV (OV5640_SCLK_ROOT_DIV / 2)
837
+
838
+/*
839
+ * This is supposed to be ranging from 1 to 8, but the value is always
840
+ * set to 1 in the vendor kernels.
841
+ */
842
+#define OV5640_PCLK_ROOT_DIV			1
843
+#define OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS	0x00
844
+
845
+static unsigned long ov5640_compute_sys_clk(struct ov5640_dev *sensor,
846
+					    u8 pll_prediv, u8 pll_mult,
847
+					    u8 sysdiv)
848
+{
849
+	unsigned long sysclk = sensor->xclk_freq / pll_prediv * pll_mult;
850
+
851
+	/* PLL1 output cannot exceed 1GHz. */
852
+	if (sysclk / 1000000 > 1000)
853
+		return 0;
854
+
855
+	return sysclk / sysdiv;
856
+}
857
+
858
+static unsigned long ov5640_calc_sys_clk(struct ov5640_dev *sensor,
859
+					 unsigned long rate,
860
+					 u8 *pll_prediv, u8 *pll_mult,
861
+					 u8 *sysdiv)
862
+{
863
+	unsigned long best = ~0;
864
+	u8 best_sysdiv = 1, best_mult = 1;
865
+	u8 _sysdiv, _pll_mult;
866
+
867
+	for (_sysdiv = OV5640_SYSDIV_MIN;
868
+	     _sysdiv <= OV5640_SYSDIV_MAX;
869
+	     _sysdiv++) {
870
+		for (_pll_mult = OV5640_PLL_MULT_MIN;
871
+		     _pll_mult <= OV5640_PLL_MULT_MAX;
872
+		     _pll_mult++) {
873
+			unsigned long _rate;
874
+
875
+			/*
876
+			 * The PLL multiplier cannot be odd if above
877
+			 * 127.
878
+			 */
879
+			if (_pll_mult > 127 && (_pll_mult % 2))
880
+				continue;
881
+
882
+			_rate = ov5640_compute_sys_clk(sensor,
883
+						       OV5640_PLL_PREDIV,
884
+						       _pll_mult, _sysdiv);
885
+
886
+			/*
887
+			 * We have reached the maximum allowed PLL1 output,
888
+			 * increase sysdiv.
889
+			 */
890
+			if (!_rate)
891
+				break;
892
+
893
+			/*
894
+			 * Prefer rates above the expected clock rate than
895
+			 * below, even if that means being less precise.
896
+			 */
897
+			if (_rate < rate)
898
+				continue;
899
+
900
+			if (abs(rate - _rate) < abs(rate - best)) {
901
+				best = _rate;
902
+				best_sysdiv = _sysdiv;
903
+				best_mult = _pll_mult;
904
+			}
905
+
906
+			if (_rate == rate)
907
+				goto out;
908
+		}
909
+	}
910
+
911
+out:
912
+	*sysdiv = best_sysdiv;
913
+	*pll_prediv = OV5640_PLL_PREDIV;
914
+	*pll_mult = best_mult;
915
+
916
+	return best;
917
+}
918
+
919
+/*
920
+ * ov5640_set_mipi_pclk() - Calculate the clock tree configuration values
921
+ *			    for the MIPI CSI-2 output.
922
+ *
923
+ * @rate: The requested bandwidth per lane in bytes per second.
924
+ *	  'Bandwidth Per Lane' is calculated as:
925
+ *	  bpl = HTOT * VTOT * FPS * bpp / num_lanes;
926
+ *
927
+ * This function use the requested bandwidth to calculate:
928
+ * - sample_rate = bpl / (bpp / num_lanes);
929
+ *	         = bpl / (PLL_RDIV * BIT_DIV * PCLK_DIV * MIPI_DIV / num_lanes);
930
+ *
931
+ * - mipi_sclk   = bpl / MIPI_DIV / 2; ( / 2 is for CSI-2 DDR)
932
+ *
933
+ * with these fixed parameters:
934
+ *	PLL_RDIV	= 2;
935
+ *	BIT_DIVIDER	= 2; (MIPI_BIT_MODE == 8 ? 2 : 2,5);
936
+ *	PCLK_DIV	= 1;
937
+ *
938
+ * The MIPI clock generation differs for modes that use the scaler and modes
939
+ * that do not. In case the scaler is in use, the MIPI_SCLK generates the MIPI
940
+ * BIT CLk, and thus:
941
+ *
942
+ * - mipi_sclk = bpl / MIPI_DIV / 2;
943
+ *   MIPI_DIV = 1;
944
+ *
945
+ * For modes that do not go through the scaler, the MIPI BIT CLOCK is generated
946
+ * from the pixel clock, and thus:
947
+ *
948
+ * - sample_rate = bpl / (bpp / num_lanes);
949
+ *	         = bpl / (2 * 2 * 1 * MIPI_DIV / num_lanes);
950
+ *		 = bpl / (4 * MIPI_DIV / num_lanes);
951
+ * - MIPI_DIV	 = bpp / (4 * num_lanes);
952
+ *
953
+ * FIXME: this have been tested with 16bpp and 2 lanes setup only.
954
+ * MIPI_DIV is fixed to value 2, but it -might- be changed according to the
955
+ * above formula for setups with 1 lane or image formats with different bpp.
956
+ *
957
+ * FIXME: this deviates from the sensor manual documentation which is quite
958
+ * thin on the MIPI clock tree generation part.
959
+ */
960
+static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor,
961
+				unsigned long rate)
962
+{
963
+	const struct ov5640_mode_info *mode = sensor->current_mode;
964
+	u8 prediv, mult, sysdiv;
965
+	u8 mipi_div;
966
+	int ret;
967
+
968
+	/*
969
+	 * 1280x720 is reported to use 'SUBSAMPLING' only,
970
+	 * but according to the sensor manual it goes through the
971
+	 * scaler before subsampling.
972
+	 */
973
+	if (mode->dn_mode == SCALING ||
974
+	   (mode->id == OV5640_MODE_720P_1280_720))
975
+		mipi_div = OV5640_MIPI_DIV_SCLK;
976
+	else
977
+		mipi_div = OV5640_MIPI_DIV_PCLK;
978
+
979
+	ov5640_calc_sys_clk(sensor, rate, &prediv, &mult, &sysdiv);
980
+
981
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
982
+			     0x0f, OV5640_PLL_CTRL0_MIPI_MODE_8BIT);
983
+
984
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
985
+			     0xff, sysdiv << 4 | mipi_div);
986
+	if (ret)
987
+		return ret;
988
+
989
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2, 0xff, mult);
990
+	if (ret)
991
+		return ret;
992
+
993
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
994
+			     0x1f, OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 | prediv);
995
+	if (ret)
996
+		return ret;
997
+
998
+	return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER,
999
+			      0x30, OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS);
1000
+}
1001
+
1002
+static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor,
1003
+				      unsigned long rate,
1004
+				      u8 *pll_prediv, u8 *pll_mult, u8 *sysdiv,
1005
+				      u8 *pll_rdiv, u8 *bit_div, u8 *pclk_div)
1006
+{
1007
+	unsigned long _rate = rate * OV5640_PLL_ROOT_DIV * OV5640_BIT_DIV *
1008
+				OV5640_PCLK_ROOT_DIV;
1009
+
1010
+	_rate = ov5640_calc_sys_clk(sensor, _rate, pll_prediv, pll_mult,
1011
+				    sysdiv);
1012
+	*pll_rdiv = OV5640_PLL_ROOT_DIV;
1013
+	*bit_div = OV5640_BIT_DIV;
1014
+	*pclk_div = OV5640_PCLK_ROOT_DIV;
1015
+
1016
+	return _rate / *pll_rdiv / *bit_div / *pclk_div;
1017
+}
1018
+
1019
+static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, unsigned long rate)
1020
+{
1021
+	u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div;
1022
+	int ret;
1023
+
1024
+	ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv,
1025
+			 &bit_div, &pclk_div);
1026
+
1027
+	if (bit_div == 2)
1028
+		bit_div = 8;
1029
+
1030
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
1031
+			     0x0f, bit_div);
1032
+	if (ret)
1033
+		return ret;
1034
+
1035
+	/*
1036
+	 * We need to set sysdiv according to the clock, and to clear
1037
+	 * the MIPI divider.
1038
+	 */
1039
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
1040
+			     0xff, sysdiv << 4);
1041
+	if (ret)
1042
+		return ret;
1043
+
1044
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2,
1045
+			     0xff, mult);
1046
+	if (ret)
1047
+		return ret;
1048
+
1049
+	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
1050
+			     0x1f, prediv | ((pll_rdiv - 1) << 4));
1051
+	if (ret)
1052
+		return ret;
1053
+
1054
+	return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x30,
1055
+			      (ilog2(pclk_div) << 4));
1056
+}
1057
+
1058
+/* set JPEG framing sizes */
1059
+static int ov5640_set_jpeg_timings(struct ov5640_dev *sensor,
1060
+				   const struct ov5640_mode_info *mode)
1061
+{
1062
+	int ret;
1063
+
1064
+	/*
1065
+	 * compression mode 3 timing
1066
+	 *
1067
+	 * Data is transmitted with programmable width (VFIFO_HSIZE).
1068
+	 * No padding done. Last line may have less data. Varying
1069
+	 * number of lines per frame, depending on amount of data.
1070
+	 */
1071
+	ret = ov5640_mod_reg(sensor, OV5640_REG_JPG_MODE_SELECT, 0x7, 0x3);
1072
+	if (ret < 0)
1073
+		return ret;
1074
+
1075
+	ret = ov5640_write_reg16(sensor, OV5640_REG_VFIFO_HSIZE, mode->hact);
1076
+	if (ret < 0)
1077
+		return ret;
1078
+
1079
+	return ov5640_write_reg16(sensor, OV5640_REG_VFIFO_VSIZE, mode->vact);
1080
+}
1081
+
9121082 /* download ov5640 settings to sensor through i2c */
9131083 static int ov5640_set_timings(struct ov5640_dev *sensor,
9141084 			      const struct ov5640_mode_info *mode)
9151085 {
9161086 	int ret;
1087
+
1088
+	if (sensor->fmt.code == MEDIA_BUS_FMT_JPEG_1X8) {
1089
+		ret = ov5640_set_jpeg_timings(sensor, mode);
1090
+		if (ret < 0)
1091
+			return ret;
1092
+	}
9171093 
9181094 	ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPHO, mode->hact);
9191095 	if (ret < 0)
....@@ -945,6 +1121,12 @@
9451121 		reg_addr = regs->reg_addr;
9461122 		val = regs->val;
9471123 		mask = regs->mask;
1124
+
1125
+		/* remain in power down mode for DVP */
1126
+		if (regs->reg_addr == OV5640_REG_SYS_CTRL0 &&
1127
+		    val == OV5640_REG_SYS_CTRL0_SW_PWUP &&
1128
+		    sensor->ep.bus_type != V4L2_MBUS_CSI2_DPHY)
1129
+			continue;
9481130 
9491131 		if (mask)
9501132 			ret = ov5640_mod_reg(sensor, reg_addr, mask, val);
....@@ -1036,106 +1218,9 @@
10361218 
10371219 static int ov5640_set_stream_dvp(struct ov5640_dev *sensor, bool on)
10381220 {
1039
-	int ret;
1040
-	unsigned int flags = sensor->ep.bus.parallel.flags;
1041
-	u8 pclk_pol = 0;
1042
-	u8 hsync_pol = 0;
1043
-	u8 vsync_pol = 0;
1044
-
1045
-	/*
1046
-	 * Note about parallel port configuration.
1047
-	 *
1048
-	 * When configured in parallel mode, the OV5640 will
1049
-	 * output 10 bits data on DVP data lines [9:0].
1050
-	 * If only 8 bits data are wanted, the 8 bits data lines
1051
-	 * of the camera interface must be physically connected
1052
-	 * on the DVP data lines [9:2].
1053
-	 *
1054
-	 * Control lines polarity can be configured through
1055
-	 * devicetree endpoint control lines properties.
1056
-	 * If no endpoint control lines properties are set,
1057
-	 * polarity will be as below:
1058
-	 * - VSYNC:	active high
1059
-	 * - HREF:	active low
1060
-	 * - PCLK:	active low
1061
-	 */
1062
-
1063
-	if (on) {
1064
-		/*
1065
-		 * reset MIPI PCLK/SERCLK divider
1066
-		 *
1067
-		 * SC PLL CONTRL1 0
1068
-		 * - [3..0]:	MIPI PCLK/SERCLK divider
1069
-		 */
1070
-		ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1, 0x0f, 0);
1071
-		if (ret)
1072
-			return ret;
1073
-
1074
-		/*
1075
-		 * configure parallel port control lines polarity
1076
-		 *
1077
-		 * POLARITY CTRL0
1078
-		 * - [5]:	PCLK polarity (0: active low, 1: active high)
1079
-		 * - [1]:	HREF polarity (0: active low, 1: active high)
1080
-		 * - [0]:	VSYNC polarity (mismatch here between
1081
-		 *		datasheet and hardware, 0 is active high
1082
-		 *		and 1 is active low...)
1083
-		 */
1084
-		if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1085
-			pclk_pol = 1;
1086
-		if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1087
-			hsync_pol = 1;
1088
-		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1089
-			vsync_pol = 1;
1090
-
1091
-		ret = ov5640_write_reg(sensor,
1092
-				       OV5640_REG_POLARITY_CTRL00,
1093
-				       (pclk_pol << 5) |
1094
-				       (hsync_pol << 1) |
1095
-				       vsync_pol);
1096
-
1097
-		if (ret)
1098
-			return ret;
1099
-	}
1100
-
1101
-	/*
1102
-	 * powerdown MIPI TX/RX PHY & disable MIPI
1103
-	 *
1104
-	 * MIPI CONTROL 00
1105
-	 * 4:	 PWDN PHY TX
1106
-	 * 3:	 PWDN PHY RX
1107
-	 * 2:	 MIPI enable
1108
-	 */
1109
-	ret = ov5640_write_reg(sensor,
1110
-			       OV5640_REG_IO_MIPI_CTRL00, on ? 0x18 : 0);
1111
-	if (ret)
1112
-		return ret;
1113
-
1114
-	/*
1115
-	 * enable VSYNC/HREF/PCLK DVP control lines
1116
-	 * & D[9:6] DVP data lines
1117
-	 *
1118
-	 * PAD OUTPUT ENABLE 01
1119
-	 * - 6:		VSYNC output enable
1120
-	 * - 5:		HREF output enable
1121
-	 * - 4:		PCLK output enable
1122
-	 * - [3:0]:	D[9:6] output enable
1123
-	 */
1124
-	ret = ov5640_write_reg(sensor,
1125
-			       OV5640_REG_PAD_OUTPUT_ENABLE01,
1126
-			       on ? 0x7f : 0);
1127
-	if (ret)
1128
-		return ret;
1129
-
1130
-	/*
1131
-	 * enable D[5:0] DVP data lines
1132
-	 *
1133
-	 * PAD OUTPUT ENABLE 02
1134
-	 * - [7:2]:	D[5:0] output enable
1135
-	 */
1136
-	return ov5640_write_reg(sensor,
1137
-				OV5640_REG_PAD_OUTPUT_ENABLE02,
1138
-				on ? 0xfc : 0);
1221
+	return ov5640_write_reg(sensor, OV5640_REG_SYS_CTRL0, on ?
1222
+				OV5640_REG_SYS_CTRL0_SW_PWUP :
1223
+				OV5640_REG_SYS_CTRL0_SW_PWDN);
11391224 }
11401225 
11411226 static int ov5640_set_stream_mipi(struct ov5640_dev *sensor, bool on)
....@@ -1444,8 +1529,8 @@
14441529 {
14451530 	const struct ov5640_mode_info *mode;
14461531 
1447
-	mode = v4l2_find_nearest_size(ov5640_mode_data[fr],
1448
-				      ARRAY_SIZE(ov5640_mode_data[fr]),
1532
+	mode = v4l2_find_nearest_size(ov5640_mode_data,
1533
+				      ARRAY_SIZE(ov5640_mode_data),
14491534 				      hact, vact,
14501535 				      width, height);
14511536 
....@@ -1453,7 +1538,21 @@
14531538 	    (!nearest && (mode->hact != width || mode->vact != height)))
14541539 		return NULL;
14551540 
1541
+	/* Check to see if the current mode exceeds the max frame rate */
1542
+	if (ov5640_framerates[fr] > ov5640_framerates[mode->max_fps])
1543
+		return NULL;
1544
+
14561545 	return mode;
1546
+}
1547
+
1548
+static u64 ov5640_calc_pixel_rate(struct ov5640_dev *sensor)
1549
+{
1550
+	u64 rate;
1551
+
1552
+	rate = sensor->current_mode->vtot * sensor->current_mode->htot;
1553
+	rate *= ov5640_framerates[sensor->current_fr];
1554
+
1555
+	return rate;
14571556 }
14581557 
14591558 /*
....@@ -1637,6 +1736,7 @@
16371736 	enum ov5640_downsize_mode dn_mode, orig_dn_mode;
16381737 	bool auto_gain = sensor->ctrls.auto_gain->val == 1;
16391738 	bool auto_exp =  sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
1739
+	unsigned long rate;
16401740 	int ret;
16411741 
16421742 	dn_mode = mode->dn_mode;
....@@ -1654,6 +1754,22 @@
16541754 		if (ret)
16551755 			goto restore_auto_gain;
16561756 	}
1757
+
1758
+	/*
1759
+	 * All the formats we support have 16 bits per pixel, seems to require
1760
+	 * the same rate than YUV, so we can just use 16 bpp all the time.
1761
+	 */
1762
+	rate = ov5640_calc_pixel_rate(sensor) * 16;
1763
+	if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) {
1764
+		rate = rate / sensor->ep.bus.mipi_csi2.num_data_lanes;
1765
+		ret = ov5640_set_mipi_pclk(sensor, rate);
1766
+	} else {
1767
+		rate = rate / sensor->ep.bus.parallel.bus_width;
1768
+		ret = ov5640_set_dvp_pclk(sensor, rate);
1769
+	}
1770
+
1771
+	if (ret < 0)
1772
+		return 0;
16571773 
16581774 	if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
16591775 	    (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
....@@ -1724,8 +1840,8 @@
17241840 	sensor->last_mode = &ov5640_mode_init_data;
17251841 
17261842 	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x3f,
1727
-			     (ilog2(OV5640_SCLK2X_ROOT_DIVIDER_DEFAULT) << 2) |
1728
-			     ilog2(OV5640_SCLK_ROOT_DIVIDER_DEFAULT));
1843
+			     (ilog2(OV5640_SCLK2X_ROOT_DIV) << 2) |
1844
+			     ilog2(OV5640_SCLK_ROOT_DIV));
17291845 	if (ret)
17301846 		return ret;
17311847 
....@@ -1806,6 +1922,182 @@
18061922 	clk_disable_unprepare(sensor->xclk);
18071923 }
18081924 
1925
+static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
1926
+{
1927
+	int ret;
1928
+
1929
+	if (!on) {
1930
+		/* Reset MIPI bus settings to their default values. */
1931
+		ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
1932
+		ov5640_write_reg(sensor, OV5640_REG_MIPI_CTRL00, 0x04);
1933
+		ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT00, 0x00);
1934
+		return 0;
1935
+	}
1936
+
1937
+	/*
1938
+	 * Power up MIPI HS Tx and LS Rx; 2 data lanes mode
1939
+	 *
1940
+	 * 0x300e = 0x40
1941
+	 * [7:5] = 010	: 2 data lanes mode (see FIXME note in
1942
+	 *		  "ov5640_set_stream_mipi()")
1943
+	 * [4] = 0	: Power up MIPI HS Tx
1944
+	 * [3] = 0	: Power up MIPI LS Rx
1945
+	 * [2] = 0	: MIPI interface disabled
1946
+	 */
1947
+	ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x40);
1948
+	if (ret)
1949
+		return ret;
1950
+
1951
+	/*
1952
+	 * Gate clock and set LP11 in 'no packets mode' (idle)
1953
+	 *
1954
+	 * 0x4800 = 0x24
1955
+	 * [5] = 1	: Gate clock when 'no packets'
1956
+	 * [2] = 1	: MIPI bus in LP11 when 'no packets'
1957
+	 */
1958
+	ret = ov5640_write_reg(sensor, OV5640_REG_MIPI_CTRL00, 0x24);
1959
+	if (ret)
1960
+		return ret;
1961
+
1962
+	/*
1963
+	 * Set data lanes and clock in LP11 when 'sleeping'
1964
+	 *
1965
+	 * 0x3019 = 0x70
1966
+	 * [6] = 1	: MIPI data lane 2 in LP11 when 'sleeping'
1967
+	 * [5] = 1	: MIPI data lane 1 in LP11 when 'sleeping'
1968
+	 * [4] = 1	: MIPI clock lane in LP11 when 'sleeping'
1969
+	 */
1970
+	ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT00, 0x70);
1971
+	if (ret)
1972
+		return ret;
1973
+
1974
+	/* Give lanes some time to coax into LP11 state. */
1975
+	usleep_range(500, 1000);
1976
+
1977
+	return 0;
1978
+}
1979
+
1980
+static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
1981
+{
1982
+	unsigned int flags = sensor->ep.bus.parallel.flags;
1983
+	bool bt656 = sensor->ep.bus_type == V4L2_MBUS_BT656;
1984
+	u8 polarities = 0;
1985
+	int ret;
1986
+
1987
+	if (!on) {
1988
+		/* Reset settings to their default values. */
1989
+		ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00, 0x00);
1990
+		ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
1991
+		ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, 0x20);
1992
+		ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01, 0x00);
1993
+		ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE02, 0x00);
1994
+		return 0;
1995
+	}
1996
+
1997
+	/*
1998
+	 * Note about parallel port configuration.
1999
+	 *
2000
+	 * When configured in parallel mode, the OV5640 will
2001
+	 * output 10 bits data on DVP data lines [9:0].
2002
+	 * If only 8 bits data are wanted, the 8 bits data lines
2003
+	 * of the camera interface must be physically connected
2004
+	 * on the DVP data lines [9:2].
2005
+	 *
2006
+	 * Control lines polarity can be configured through
2007
+	 * devicetree endpoint control lines properties.
2008
+	 * If no endpoint control lines properties are set,
2009
+	 * polarity will be as below:
2010
+	 * - VSYNC:	active high
2011
+	 * - HREF:	active low
2012
+	 * - PCLK:	active low
2013
+	 *
2014
+	 * VSYNC & HREF are not configured if BT656 bus mode is selected
2015
+	 */
2016
+
2017
+	/*
2018
+	 * BT656 embedded synchronization configuration
2019
+	 *
2020
+	 * CCIR656 CTRL00
2021
+	 * - [7]:	SYNC code selection (0: auto generate sync code,
2022
+	 *		1: sync code from regs 0x4732-0x4735)
2023
+	 * - [6]:	f value in CCIR656 SYNC code when fixed f value
2024
+	 * - [5]:	Fixed f value
2025
+	 * - [4:3]:	Blank toggle data options (00: data=1'h040/1'h200,
2026
+	 *		01: data from regs 0x4736-0x4738, 10: always keep 0)
2027
+	 * - [1]:	Clip data disable
2028
+	 * - [0]:	CCIR656 mode enable
2029
+	 *
2030
+	 * Default CCIR656 SAV/EAV mode with default codes
2031
+	 * SAV=0xff000080 & EAV=0xff00009d is enabled here with settings:
2032
+	 * - CCIR656 mode enable
2033
+	 * - auto generation of sync codes
2034
+	 * - blank toggle data 1'h040/1'h200
2035
+	 * - clip reserved data (0x00 & 0xff changed to 0x01 & 0xfe)
2036
+	 */
2037
+	ret = ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00,
2038
+			       bt656 ? 0x01 : 0x00);
2039
+	if (ret)
2040
+		return ret;
2041
+
2042
+	/*
2043
+	 * configure parallel port control lines polarity
2044
+	 *
2045
+	 * POLARITY CTRL0
2046
+	 * - [5]:	PCLK polarity (0: active low, 1: active high)
2047
+	 * - [1]:	HREF polarity (0: active low, 1: active high)
2048
+	 * - [0]:	VSYNC polarity (mismatch here between
2049
+	 *		datasheet and hardware, 0 is active high
2050
+	 *		and 1 is active low...)
2051
+	 */
2052
+	if (!bt656) {
2053
+		if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2054
+			polarities |= BIT(1);
2055
+		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
2056
+			polarities |= BIT(0);
2057
+	}
2058
+	if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2059
+		polarities |= BIT(5);
2060
+
2061
+	ret = ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, polarities);
2062
+	if (ret)
2063
+		return ret;
2064
+
2065
+	/*
2066
+	 * powerdown MIPI TX/RX PHY & enable DVP
2067
+	 *
2068
+	 * MIPI CONTROL 00
2069
+	 * [4] = 1	: Power down MIPI HS Tx
2070
+	 * [3] = 1	: Power down MIPI LS Rx
2071
+	 * [2] = 0	: DVP enable (MIPI disable)
2072
+	 */
2073
+	ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x18);
2074
+	if (ret)
2075
+		return ret;
2076
+
2077
+	/*
2078
+	 * enable VSYNC/HREF/PCLK DVP control lines
2079
+	 * & D[9:6] DVP data lines
2080
+	 *
2081
+	 * PAD OUTPUT ENABLE 01
2082
+	 * - 6:		VSYNC output enable
2083
+	 * - 5:		HREF output enable
2084
+	 * - 4:		PCLK output enable
2085
+	 * - [3:0]:	D[9:6] output enable
2086
+	 */
2087
+	ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01,
2088
+			       bt656 ? 0x1f : 0x7f);
2089
+	if (ret)
2090
+		return ret;
2091
+
2092
+	/*
2093
+	 * enable D[5:0] DVP data lines
2094
+	 *
2095
+	 * PAD OUTPUT ENABLE 02
2096
+	 * - [7:2]:	D[5:0] output enable
2097
+	 */
2098
+	return ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE02, 0xfc);
2099
+}
2100
+
18092101 static int ov5640_set_power(struct ov5640_dev *sensor, bool on)
18102102 {
18112103 	int ret = 0;
....@@ -1818,67 +2110,17 @@
18182110 		ret = ov5640_restore_mode(sensor);
18192111 		if (ret)
18202112 			goto power_off;
1821
-
1822
-		/* We're done here for DVP bus, while CSI-2 needs setup. */
1823
-		if (sensor->ep.bus_type != V4L2_MBUS_CSI2)
1824
-			return 0;
1825
-
1826
-		/*
1827
-		 * Power up MIPI HS Tx and LS Rx; 2 data lanes mode
1828
-		 *
1829
-		 * 0x300e = 0x40
1830
-		 * [7:5] = 010	: 2 data lanes mode (see FIXME note in
1831
-		 *		  "ov5640_set_stream_mipi()")
1832
-		 * [4] = 0	: Power up MIPI HS Tx
1833
-		 * [3] = 0	: Power up MIPI LS Rx
1834
-		 * [2] = 0	: MIPI interface disabled
1835
-		 */
1836
-		ret = ov5640_write_reg(sensor,
1837
-				       OV5640_REG_IO_MIPI_CTRL00, 0x40);
1838
-		if (ret)
1839
-			goto power_off;
1840
-
1841
-		/*
1842
-		 * Gate clock and set LP11 in 'no packets mode' (idle)
1843
-		 *
1844
-		 * 0x4800 = 0x24
1845
-		 * [5] = 1	: Gate clock when 'no packets'
1846
-		 * [2] = 1	: MIPI bus in LP11 when 'no packets'
1847
-		 */
1848
-		ret = ov5640_write_reg(sensor,
1849
-				       OV5640_REG_MIPI_CTRL00, 0x24);
1850
-		if (ret)
1851
-			goto power_off;
1852
-
1853
-		/*
1854
-		 * Set data lanes and clock in LP11 when 'sleeping'
1855
-		 *
1856
-		 * 0x3019 = 0x70
1857
-		 * [6] = 1	: MIPI data lane 2 in LP11 when 'sleeping'
1858
-		 * [5] = 1	: MIPI data lane 1 in LP11 when 'sleeping'
1859
-		 * [4] = 1	: MIPI clock lane in LP11 when 'sleeping'
1860
-		 */
1861
-		ret = ov5640_write_reg(sensor,
1862
-				       OV5640_REG_PAD_OUTPUT00, 0x70);
1863
-		if (ret)
1864
-			goto power_off;
1865
-
1866
-		/* Give lanes some time to coax into LP11 state. */
1867
-		usleep_range(500, 1000);
1868
-
1869
-	} else {
1870
-		if (sensor->ep.bus_type == V4L2_MBUS_CSI2) {
1871
-			/* Reset MIPI bus settings to their default values. */
1872
-			ov5640_write_reg(sensor,
1873
-					 OV5640_REG_IO_MIPI_CTRL00, 0x58);
1874
-			ov5640_write_reg(sensor,
1875
-					 OV5640_REG_MIPI_CTRL00, 0x04);
1876
-			ov5640_write_reg(sensor,
1877
-					 OV5640_REG_PAD_OUTPUT00, 0x00);
1878
-		}
1879
-
1880
-		ov5640_set_power_off(sensor);
18812113 	}
2114
+
2115
+	if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
2116
+		ret = ov5640_set_power_mipi(sensor, on);
2117
+	else
2118
+		ret = ov5640_set_power_dvp(sensor, on);
2119
+	if (ret)
2120
+		goto power_off;
2121
+
2122
+	if (!on)
2123
+		ov5640_set_power_off(sensor);
18822124 
18832125 	return 0;
18842126 
....@@ -1925,34 +2167,39 @@
19252167 				     u32 width, u32 height)
19262168 {
19272169 	const struct ov5640_mode_info *mode;
1928
-	u32 minfps, maxfps, fps;
1929
-	int ret;
2170
+	enum ov5640_frame_rate rate = OV5640_15_FPS;
2171
+	int minfps, maxfps, best_fps, fps;
2172
+	int i;
19302173 
19312174 	minfps = ov5640_framerates[OV5640_15_FPS];
1932
-	maxfps = ov5640_framerates[OV5640_30_FPS];
2175
+	maxfps = ov5640_framerates[OV5640_60_FPS];
19332176 
19342177 	if (fi->numerator == 0) {
19352178 		fi->denominator = maxfps;
19362179 		fi->numerator = 1;
1937
-		return OV5640_30_FPS;
2180
+		rate = OV5640_60_FPS;
2181
+		goto find_mode;
19382182 	}
19392183 
1940
-	fps = DIV_ROUND_CLOSEST(fi->denominator, fi->numerator);
2184
+	fps = clamp_val(DIV_ROUND_CLOSEST(fi->denominator, fi->numerator),
2185
+			minfps, maxfps);
2186
+
2187
+	best_fps = minfps;
2188
+	for (i = 0; i < ARRAY_SIZE(ov5640_framerates); i++) {
2189
+		int curr_fps = ov5640_framerates[i];
2190
+
2191
+		if (abs(curr_fps - fps) < abs(best_fps - fps)) {
2192
+			best_fps = curr_fps;
2193
+			rate = i;
2194
+		}
2195
+	}
19412196 
19422197 	fi->numerator = 1;
1943
-	if (fps > maxfps)
1944
-		fi->denominator = maxfps;
1945
-	else if (fps < minfps)
1946
-		fi->denominator = minfps;
1947
-	else if (2 * fps >= 2 * minfps + (maxfps - minfps))
1948
-		fi->denominator = maxfps;
1949
-	else
1950
-		fi->denominator = minfps;
2198
+	fi->denominator = best_fps;
19512199 
1952
-	ret = (fi->denominator == minfps) ? OV5640_15_FPS : OV5640_30_FPS;
1953
-
1954
-	mode = ov5640_find_mode(sensor, ret, width, height, false);
1955
-	return mode ? ret : -EINVAL;
2200
+find_mode:
2201
+	mode = ov5640_find_mode(sensor, rate, width, height, false);
2202
+	return mode ? rate : -EINVAL;
19562203 }
19572204 
19582205 static int ov5640_get_fmt(struct v4l2_subdev *sd,
....@@ -2052,6 +2299,8 @@
20522299 	if (mbus_fmt->code != sensor->fmt.code)
20532300 		sensor->pending_fmt_change = true;
20542301 
2302
+	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
2303
+				 ov5640_calc_pixel_rate(sensor));
20552304 out:
20562305 	mutex_unlock(&sensor->lock);
20572306 	return ret;
....@@ -2061,46 +2310,67 @@
20612310 			       struct v4l2_mbus_framefmt *format)
20622311 {
20632312 	int ret = 0;
2064
-	bool is_rgb = false;
20652313 	bool is_jpeg = false;
2066
-	u8 val;
2314
+	u8 fmt, mux;
20672315 
20682316 	switch (format->code) {
20692317 	case MEDIA_BUS_FMT_UYVY8_2X8:
20702318 		/* YUV422, UYVY */
2071
-		val = 0x3f;
2319
+		fmt = 0x3f;
2320
+		mux = OV5640_FMT_MUX_YUV422;
20722321 		break;
20732322 	case MEDIA_BUS_FMT_YUYV8_2X8:
20742323 		/* YUV422, YUYV */
2075
-		val = 0x30;
2324
+		fmt = 0x30;
2325
+		mux = OV5640_FMT_MUX_YUV422;
20762326 		break;
20772327 	case MEDIA_BUS_FMT_RGB565_2X8_LE:
20782328 		/* RGB565 {g[2:0],b[4:0]},{r[4:0],g[5:3]} */
2079
-		val = 0x6F;
2080
-		is_rgb = true;
2329
+		fmt = 0x6F;
2330
+		mux = OV5640_FMT_MUX_RGB;
20812331 		break;
20822332 	case MEDIA_BUS_FMT_RGB565_2X8_BE:
20832333 		/* RGB565 {r[4:0],g[5:3]},{g[2:0],b[4:0]} */
2084
-		val = 0x61;
2085
-		is_rgb = true;
2334
+		fmt = 0x61;
2335
+		mux = OV5640_FMT_MUX_RGB;
20862336 		break;
20872337 	case MEDIA_BUS_FMT_JPEG_1X8:
20882338 		/* YUV422, YUYV */
2089
-		val = 0x30;
2339
+		fmt = 0x30;
2340
+		mux = OV5640_FMT_MUX_YUV422;
20902341 		is_jpeg = true;
2342
+		break;
2343
+	case MEDIA_BUS_FMT_SBGGR8_1X8:
2344
+		/* Raw, BGBG... / GRGR... */
2345
+		fmt = 0x00;
2346
+		mux = OV5640_FMT_MUX_RAW_DPC;
2347
+		break;
2348
+	case MEDIA_BUS_FMT_SGBRG8_1X8:
2349
+		/* Raw bayer, GBGB... / RGRG... */
2350
+		fmt = 0x01;
2351
+		mux = OV5640_FMT_MUX_RAW_DPC;
2352
+		break;
2353
+	case MEDIA_BUS_FMT_SGRBG8_1X8:
2354
+		/* Raw bayer, GRGR... / BGBG... */
2355
+		fmt = 0x02;
2356
+		mux = OV5640_FMT_MUX_RAW_DPC;
2357
+		break;
2358
+	case MEDIA_BUS_FMT_SRGGB8_1X8:
2359
+		/* Raw bayer, RGRG... / GBGB... */
2360
+		fmt = 0x03;
2361
+		mux = OV5640_FMT_MUX_RAW_DPC;
20912362 		break;
20922363 	default:
20932364 		return -EINVAL;
20942365 	}
20952366 
20962367 	/* FORMAT CONTROL00: YUV and RGB formatting */
2097
-	ret = ov5640_write_reg(sensor, OV5640_REG_FORMAT_CONTROL00, val);
2368
+	ret = ov5640_write_reg(sensor, OV5640_REG_FORMAT_CONTROL00, fmt);
20982369 	if (ret)
20992370 		return ret;
21002371 
21012372 	/* FORMAT MUX CONTROL: ISP YUV or RGB */
2102
-	ret = ov5640_write_reg(sensor, OV5640_REG_ISP_FORMAT_MUX_CTRL,
2103
-			       is_rgb ? 0x01 : 0x00);
2373
+	ret = ov5640_write_reg(sensor, OV5640_REG_ISP_FORMAT_MUX_CTRL, mux);
21042374 	if (ret)
21052375 		return ret;
21062376 
....@@ -2268,10 +2538,41 @@
22682538 	return ret;
22692539 }
22702540 
2541
+static const char * const test_pattern_menu[] = {
2542
+	"Disabled",
2543
+	"Color bars",
2544
+	"Color bars w/ rolling bar",
2545
+	"Color squares",
2546
+	"Color squares w/ rolling bar",
2547
+};
2548
+
2549
+#define OV5640_TEST_ENABLE		BIT(7)
2550
+#define OV5640_TEST_ROLLING		BIT(6)	/* rolling horizontal bar */
2551
+#define OV5640_TEST_TRANSPARENT		BIT(5)
2552
+#define OV5640_TEST_SQUARE_BW		BIT(4)	/* black & white squares */
2553
+#define OV5640_TEST_BAR_STANDARD	(0 << 2)
2554
+#define OV5640_TEST_BAR_VERT_CHANGE_1	(1 << 2)
2555
+#define OV5640_TEST_BAR_HOR_CHANGE	(2 << 2)
2556
+#define OV5640_TEST_BAR_VERT_CHANGE_2	(3 << 2)
2557
+#define OV5640_TEST_BAR			(0 << 0)
2558
+#define OV5640_TEST_RANDOM		(1 << 0)
2559
+#define OV5640_TEST_SQUARE		(2 << 0)
2560
+#define OV5640_TEST_BLACK		(3 << 0)
2561
+
2562
+static const u8 test_pattern_val[] = {
2563
+	0,
2564
+	OV5640_TEST_ENABLE | OV5640_TEST_BAR_VERT_CHANGE_1 |
2565
+		OV5640_TEST_BAR,
2566
+	OV5640_TEST_ENABLE | OV5640_TEST_ROLLING |
2567
+		OV5640_TEST_BAR_VERT_CHANGE_1 | OV5640_TEST_BAR,
2568
+	OV5640_TEST_ENABLE | OV5640_TEST_SQUARE,
2569
+	OV5640_TEST_ENABLE | OV5640_TEST_ROLLING | OV5640_TEST_SQUARE,
2570
+};
2571
+
22712572 static int ov5640_set_ctrl_test_pattern(struct ov5640_dev *sensor, int value)
22722573 {
2273
-	return ov5640_mod_reg(sensor, OV5640_REG_PRE_ISP_TEST_SET1,
2274
-			      0xa4, value ? 0xa4 : 0);
2574
+	return ov5640_write_reg(sensor, OV5640_REG_PRE_ISP_TEST_SET1,
2575
+				test_pattern_val[value]);
22752576 }
22762577 
22772578 static int ov5640_set_ctrl_light_freq(struct ov5640_dev *sensor, int value)
....@@ -2412,11 +2713,6 @@
24122713 	.s_ctrl = ov5640_s_ctrl,
24132714 };
24142715 
2415
-static const char * const test_pattern_menu[] = {
2416
-	"Disabled",
2417
-	"Color bars",
2418
-};
2419
-
24202716 static int ov5640_init_controls(struct ov5640_dev *sensor)
24212717 {
24222718 	const struct v4l2_ctrl_ops *ops = &ov5640_ctrl_ops;
....@@ -2428,6 +2724,11 @@
24282724 
24292725 	/* we can use our own mutex for the ctrl lock */
24302726 	hdl->lock = &sensor->lock;
2727
+
2728
+	/* Clock related controls */
2729
+	ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
2730
+					      0, INT_MAX, 1,
2731
+					      ov5640_calc_pixel_rate(sensor));
24312732 
24322733 	/* Auto/manual white balance */
24332734 	ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
....@@ -2476,6 +2777,7 @@
24762777 		goto free_ctrls;
24772778 	}
24782779 
2780
+	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
24792781 	ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
24802782 	ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
24812783 
....@@ -2501,10 +2803,10 @@
25012803 		return -EINVAL;
25022804 
25032805 	fse->min_width =
2504
-		ov5640_mode_data[0][fse->index].hact;
2806
+		ov5640_mode_data[fse->index].hact;
25052807 	fse->max_width = fse->min_width;
25062808 	fse->min_height =
2507
-		ov5640_mode_data[0][fse->index].vact;
2809
+		ov5640_mode_data[fse->index].vact;
25082810 	fse->max_height = fse->min_height;
25092811 
25102812 	return 0;
....@@ -2569,8 +2871,11 @@
25692871 
25702872 	frame_rate = ov5640_try_frame_interval(sensor, &fi->interval,
25712873 					       mode->hact, mode->vact);
2572
-	if (frame_rate < 0)
2573
-		frame_rate = OV5640_15_FPS;
2874
+	if (frame_rate < 0) {
2875
+		/* Always return a valid frame interval value */
2876
+		fi->interval = sensor->frame_interval;
2877
+		goto out;
2878
+	}
25742879 
25752880 	mode = ov5640_find_mode(sensor, frame_rate, mode->hact,
25762881 				mode->vact, true);
....@@ -2585,6 +2890,9 @@
25852890 		sensor->frame_interval = fi->interval;
25862891 		sensor->current_mode = mode;
25872892 		sensor->pending_mode_change = true;
2893
+
2894
+		__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
2895
+					 ov5640_calc_pixel_rate(sensor));
25882896 	}
25892897 out:
25902898 	mutex_unlock(&sensor->lock);
....@@ -2625,7 +2933,7 @@
26252933 			sensor->pending_fmt_change = false;
26262934 		}
26272935 
2628
-		if (sensor->ep.bus_type == V4L2_MBUS_CSI2)
2936
+		if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
26292937 			ret = ov5640_set_stream_mipi(sensor, enable);
26302938 		else
26312939 			ret = ov5640_set_stream_dvp(sensor, enable);
....@@ -2640,6 +2948,9 @@
26402948 
26412949 static const struct v4l2_subdev_core_ops ov5640_core_ops = {
26422950 	.s_power = ov5640_s_power,
2951
+	.log_status = v4l2_ctrl_subdev_log_status,
2952
+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
2953
+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
26432954 };
26442955 
26452956 static const struct v4l2_subdev_video_ops ov5640_video_ops = {
....@@ -2702,8 +3013,7 @@
27023013 	return ret;
27033014 }
27043015 
2705
-static int ov5640_probe(struct i2c_client *client,
2706
-			const struct i2c_device_id *id)
3016
+static int ov5640_probe(struct i2c_client *client)
27073017 {
27083018 	struct device *dev = &client->dev;
27093019 	struct fwnode_handle *endpoint;
....@@ -2735,7 +3045,7 @@
27353045 	sensor->frame_interval.denominator = ov5640_framerates[OV5640_30_FPS];
27363046 	sensor->current_fr = OV5640_30_FPS;
27373047 	sensor->current_mode =
2738
-		&ov5640_mode_data[OV5640_30_FPS][OV5640_MODE_VGA_640_480];
3048
+		&ov5640_mode_data[OV5640_MODE_VGA_640_480];
27393049 	sensor->last_mode = sensor->current_mode;
27403050 
27413051 	sensor->ae_target = 52;
....@@ -2747,7 +3057,7 @@
27473057 		switch (rotation) {
27483058 		case 180:
27493059 			sensor->upside_down = true;
2750
-			/* fall through */
3060
+			fallthrough;
27513061 		case 0:
27523062 			break;
27533063 		default:
....@@ -2768,6 +3078,13 @@
27683078 	if (ret) {
27693079 		dev_err(dev, "Could not parse endpoint\n");
27703080 		return ret;
3081
+	}
3082
+
3083
+	if (sensor->ep.bus_type != V4L2_MBUS_PARALLEL &&
3084
+	    sensor->ep.bus_type != V4L2_MBUS_CSI2_DPHY &&
3085
+	    sensor->ep.bus_type != V4L2_MBUS_BT656) {
3086
+		dev_err(dev, "Unsupported bus type %d\n", sensor->ep.bus_type);
3087
+		return -EINVAL;
27713088 	}
27723089 
27733090 	/* get system clock (xclk) */
....@@ -2799,7 +3116,8 @@
27993116 
28003117 	v4l2_i2c_subdev_init(&sensor->sd, client, &ov5640_subdev_ops);
28013118 
2802
-	sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
3119
+	sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
3120
+			    V4L2_SUBDEV_FL_HAS_EVENTS;
28033121 	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
28043122 	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
28053123 	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
....@@ -2820,7 +3138,7 @@
28203138 	if (ret)
28213139 		goto entity_cleanup;
28223140 
2823
-	ret = v4l2_async_register_subdev(&sensor->sd);
3141
+	ret = v4l2_async_register_subdev_sensor_common(&sensor->sd);
28243142 	if (ret)
28253143 		goto free_ctrls;
28263144 
....@@ -2865,7 +3183,7 @@
28653183 		.of_match_table	= ov5640_dt_ids,
28663184 	},
28673185 	.id_table = ov5640_id,
2868
-	.probe    = ov5640_probe,
3186
+	.probe_new = ov5640_probe,
28693187 	.remove   = ov5640_remove,
28703188 };
28713189