.. | .. |
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117 | 117 | #define MIRROR_BIT_MASK BIT(2) |
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118 | 118 | #define FLIP_BIT_MASK BIT(2) |
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119 | 119 | |
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120 | | -enum ov12d2q_max_pad { |
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121 | | - PAD0, |
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122 | | - PAD1, |
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123 | | - PAD2, |
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124 | | - PAD3, |
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125 | | - PAD_MAX, |
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126 | | -}; |
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127 | | - |
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128 | 120 | struct regval { |
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129 | 121 | u16 addr; |
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130 | 122 | u8 val; |
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.. | .. |
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2224 | 2216 | struct ov12d2q *ov12d2q = to_ov12d2q(sd); |
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2225 | 2217 | const struct ov12d2q_mode *mode = ov12d2q->cur_mode; |
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2226 | 2218 | |
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2227 | | - mutex_lock(&ov12d2q->mutex); |
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2228 | 2219 | fi->interval = mode->max_fps; |
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2229 | | - mutex_unlock(&ov12d2q->mutex); |
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2230 | 2220 | |
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2231 | 2221 | return 0; |
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2232 | 2222 | } |
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2233 | 2223 | |
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2234 | | -static int ov12d2q_g_mbus_config(struct v4l2_subdev *sd, |
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| 2224 | +static int ov12d2q_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, |
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2235 | 2225 | struct v4l2_mbus_config *config) |
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2236 | 2226 | { |
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2237 | 2227 | struct ov12d2q *ov12d2q = to_ov12d2q(sd); |
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.. | .. |
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2248 | 2238 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | |
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2249 | 2239 | V4L2_MBUS_CSI2_CHANNEL_1; |
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2250 | 2240 | |
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2251 | | - config->type = V4L2_MBUS_CSI2; |
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| 2241 | + config->type = V4L2_MBUS_CSI2_DPHY; |
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2252 | 2242 | config->flags = val; |
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2253 | 2243 | |
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2254 | 2244 | return 0; |
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.. | .. |
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2724 | 2714 | static const struct v4l2_subdev_video_ops ov12d2q_video_ops = { |
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2725 | 2715 | .s_stream = ov12d2q_s_stream, |
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2726 | 2716 | .g_frame_interval = ov12d2q_g_frame_interval, |
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2727 | | - .g_mbus_config = ov12d2q_g_mbus_config, |
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2728 | 2717 | }; |
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2729 | 2718 | |
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2730 | 2719 | static const struct v4l2_subdev_pad_ops ov12d2q_pad_ops = { |
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.. | .. |
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2733 | 2722 | .enum_frame_interval = ov12d2q_enum_frame_interval, |
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2734 | 2723 | .get_fmt = ov12d2q_get_fmt, |
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2735 | 2724 | .set_fmt = ov12d2q_set_fmt, |
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| 2725 | + .get_mbus_config = ov12d2q_g_mbus_config, |
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2736 | 2726 | }; |
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2737 | 2727 | |
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2738 | 2728 | static const struct v4l2_subdev_ops ov12d2q_subdev_ops = { |
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.. | .. |
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2769 | 2759 | switch (ctrl->id) { |
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2770 | 2760 | case V4L2_CID_EXPOSURE: |
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2771 | 2761 | if (ov12d2q->cur_mode->hdr_mode != NO_HDR) |
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2772 | | - return 0; |
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| 2762 | + goto ctrl_end; |
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2773 | 2763 | ret = ov12d2q_write_reg(ov12d2q->client, |
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2774 | 2764 | OV12D2Q_REG_EXP_L_H, |
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2775 | 2765 | OV12D2Q_REG_VALUE_16BIT, |
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.. | .. |
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2779 | 2769 | break; |
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2780 | 2770 | case V4L2_CID_ANALOGUE_GAIN: |
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2781 | 2771 | if (ov12d2q->cur_mode->hdr_mode != NO_HDR) |
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2782 | | - return 0; |
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| 2772 | + goto ctrl_end; |
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2783 | 2773 | if (ctrl->val > 1984) {// >15.5x |
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2784 | 2774 | dgain = ctrl->val * 10 / 155; |
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2785 | 2775 | again = 1984; |
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.. | .. |
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2896 | 2886 | break; |
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2897 | 2887 | } |
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2898 | 2888 | |
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| 2889 | +ctrl_end: |
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2899 | 2890 | pm_runtime_put(&client->dev); |
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2900 | 2891 | |
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2901 | 2892 | return ret; |
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