hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/media/i2c/os04a10.c
....@@ -30,6 +30,8 @@
3030 #include <media/v4l2-subdev.h>
3131 #include <linux/pinctrl/consumer.h>
3232 #include <linux/rk-preisp.h>
33
+#include <media/v4l2-fwnode.h>
34
+#include <linux/of_graph.h>
3335 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
3436
3537 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
....@@ -40,9 +42,11 @@
4042
4143 #define MIPI_FREQ_360M 360000000
4244 #define MIPI_FREQ_648M 648000000
45
+#define MIPI_FREQ_720M 720000000
4346
4447 #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10 * 4)
45
-#define PIXEL_RATE_WITH_648M (MIPI_FREQ_648M * 2 / 12 * 4)
48
+#define PIXEL_RATE_WITH_648M (MIPI_FREQ_648M * 2 / 10 * 4)
49
+#define PIXEL_RATE_WITH_720M (MIPI_FREQ_720M * 2 / 10 * 4)
4650
4751 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
4852
....@@ -100,16 +104,12 @@
100104 #define OS04A10_REG_VALUE_16BIT 2
101105 #define OS04A10_REG_VALUE_24BIT 3
102106
103
-#define OS04A10_LANES 4
104
-
105107 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
106108 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
107109
108110 #define OS04A10_NAME "os04a10"
109111
110112 #define USED_SYS_DEBUG
111
-
112
-struct preisp_hdrae_exp_s init_hdrae_exp;
113113
114114 static const char * const os04a10_supply_names[] = {
115115 "avdd", /* Analog power */
....@@ -122,14 +122,6 @@
122122 #define OS04A10_FLIP_REG 0x3820
123123 #define MIRROR_BIT_MASK BIT(1)
124124 #define FLIP_BIT_MASK BIT(2)
125
-
126
-enum os04a10_max_pad {
127
- PAD0,
128
- PAD1,
129
- PAD2,
130
- PAD3,
131
- PAD_MAX,
132
-};
133125
134126 struct regval {
135127 u16 addr;
....@@ -144,8 +136,11 @@
144136 u32 hts_def;
145137 u32 vts_def;
146138 u32 exp_def;
139
+ const struct regval *global_reg_list;
147140 const struct regval *reg_list;
148141 u32 hdr_mode;
142
+ u32 link_freq_idx;
143
+ u32 bpp;
149144 u32 vc[PAD_MAX];
150145 };
151146
....@@ -176,6 +171,7 @@
176171 struct mutex mutex;
177172 bool streaming;
178173 bool power_on;
174
+ const struct os04a10_mode *supported_modes;
179175 const struct os04a10_mode *cur_mode;
180176 u32 cfg_num;
181177 u32 module_index;
....@@ -192,6 +188,7 @@
192188 bool is_first_streamoff;
193189 u8 flip;
194190 u32 dcg_ratio;
191
+ struct v4l2_fwnode_endpoint bus_cfg;
195192 };
196193
197194 #define to_os04a10(sd) container_of(sd, struct os04a10, subdev)
....@@ -793,6 +790,367 @@
793790 {REG_NULL, 0x00},
794791 };
795792
793
+static const struct regval os04a10_global_regs_2lane[] = {
794
+ {0x0109, 0x01},
795
+ {0x0104, 0x02},
796
+ {0x0102, 0x00},
797
+ {0x0306, 0x00},
798
+ {0x0307, 0x00},
799
+ {0x0308, 0x04},
800
+ {0x030a, 0x01},
801
+ {0x0317, 0x09},
802
+ {0x0322, 0x01},
803
+ {0x0323, 0x02},
804
+ {0x0324, 0x00},
805
+ {0x0327, 0x05},
806
+ {0x0329, 0x02},
807
+ {0x032c, 0x02},
808
+ {0x032d, 0x02},
809
+ {0x032e, 0x02},
810
+ {0x300f, 0x11},
811
+ {0x3012, 0x21},
812
+ {0x3026, 0x10},
813
+ {0x3027, 0x08},
814
+ {0x302d, 0x24},
815
+ {0x3104, 0x01},
816
+ {0x3106, 0x11},
817
+ {0x3400, 0x00},
818
+ {0x3408, 0x05},
819
+ {0x340c, 0x0c},
820
+ {0x340d, 0xb0},
821
+ {0x3425, 0x51},
822
+ {0x3426, 0x10},
823
+ {0x3427, 0x14},
824
+ {0x3428, 0x10},
825
+ {0x3429, 0x10},
826
+ {0x342a, 0x10},
827
+ {0x342b, 0x04},
828
+ {0x3501, 0x02},
829
+ {0x3504, 0x08},
830
+ {0x3508, 0x01},
831
+ {0x3509, 0x00},
832
+ {0x350a, 0x01},
833
+ {0x3544, 0x08},
834
+ {0x3548, 0x01},
835
+ {0x3549, 0x00},
836
+ {0x3584, 0x08},
837
+ {0x3588, 0x01},
838
+ {0x3589, 0x00},
839
+ {0x3601, 0x70},
840
+ {0x3604, 0xe3},
841
+ {0x3605, 0x7f},
842
+ {0x3606, 0x80},
843
+ {0x3608, 0xa8},
844
+ {0x360a, 0xd0},
845
+ {0x360b, 0x08},
846
+ {0x360e, 0xc8},
847
+ {0x360f, 0x66},
848
+ {0x3610, 0x89},
849
+ {0x3611, 0x8a},
850
+ {0x3612, 0x4e},
851
+ {0x3613, 0xbd},
852
+ {0x3614, 0x9b},
853
+ {0x362a, 0x0e},
854
+ {0x362b, 0x0e},
855
+ {0x362c, 0x0e},
856
+ {0x362d, 0x0e},
857
+ {0x362e, 0x1a},
858
+ {0x362f, 0x34},
859
+ {0x3630, 0x67},
860
+ {0x3631, 0x7f},
861
+ {0x3638, 0x00},
862
+ {0x3643, 0x00},
863
+ {0x3644, 0x00},
864
+ {0x3645, 0x00},
865
+ {0x3646, 0x00},
866
+ {0x3647, 0x00},
867
+ {0x3648, 0x00},
868
+ {0x3649, 0x00},
869
+ {0x364a, 0x04},
870
+ {0x364c, 0x0e},
871
+ {0x364d, 0x0e},
872
+ {0x364e, 0x0e},
873
+ {0x364f, 0x0e},
874
+ {0x3650, 0xff},
875
+ {0x3651, 0xff},
876
+ {0x365a, 0x00},
877
+ {0x365b, 0x00},
878
+ {0x365c, 0x00},
879
+ {0x365d, 0x00},
880
+ {0x3661, 0x07},
881
+ {0x3662, 0x02},
882
+ {0x3663, 0x20},
883
+ {0x3665, 0x12},
884
+ {0x3668, 0x80},
885
+ {0x366c, 0x00},
886
+ {0x366d, 0x00},
887
+ {0x366e, 0x00},
888
+ {0x366f, 0x00},
889
+ {0x3673, 0x2a},
890
+ {0x3681, 0x80},
891
+ {0x3700, 0x2d},
892
+ {0x3701, 0x22},
893
+ {0x3702, 0x25},
894
+ {0x3703, 0x20},
895
+ {0x3705, 0x00},
896
+ {0x3706, 0x72},
897
+ {0x3707, 0x0a},
898
+ {0x3708, 0x36},
899
+ {0x3709, 0x57},
900
+ {0x370a, 0x01},
901
+ {0x370b, 0x14},
902
+ {0x3714, 0x01},
903
+ {0x3719, 0x1f},
904
+ {0x371b, 0x16},
905
+ {0x371c, 0x00},
906
+ {0x371d, 0x08},
907
+ {0x373f, 0x63},
908
+ {0x3740, 0x63},
909
+ {0x3741, 0x63},
910
+ {0x3742, 0x63},
911
+ {0x3743, 0x01},
912
+ {0x3756, 0x9d},
913
+ {0x3757, 0x9d},
914
+ {0x3762, 0x1c},
915
+ {0x3673, 0x2a},
916
+ {0x3681, 0x80},
917
+ {0x3700, 0x2d},
918
+ {0x3701, 0x22},
919
+ {0x3702, 0x25},
920
+ {0x3703, 0x20},
921
+ {0x3705, 0x00},
922
+ {0x3706, 0x72},
923
+ {0x3707, 0x0a},
924
+ {0x3708, 0x36},
925
+ {0x3709, 0x57},
926
+ {0x370a, 0x01},
927
+ {0x370b, 0x14},
928
+ {0x3714, 0x01},
929
+ {0x3719, 0x1f},
930
+ {0x371b, 0x16},
931
+ {0x371c, 0x00},
932
+ {0x371d, 0x08},
933
+ {0x373f, 0x63},
934
+ {0x3740, 0x63},
935
+ {0x3741, 0x63},
936
+ {0x3742, 0x63},
937
+ {0x3743, 0x01},
938
+ {0x3756, 0x9d},
939
+ {0x3757, 0x9d},
940
+ {0x3762, 0x1c},
941
+ {0x3776, 0x05},
942
+ {0x3777, 0x22},
943
+ {0x3779, 0x60},
944
+ {0x377c, 0x48},
945
+ {0x3784, 0x06},
946
+ {0x3785, 0x0a},
947
+ {0x3790, 0x10},
948
+ {0x3793, 0x04},
949
+ {0x3794, 0x07},
950
+ {0x3796, 0x00},
951
+ {0x3797, 0x02},
952
+ {0x379c, 0x4d},
953
+ {0x37a1, 0x80},
954
+ {0x37bb, 0x88},
955
+ {0x37be, 0x48},
956
+ {0x37bf, 0x01},
957
+ {0x37c0, 0x01},
958
+ {0x37c4, 0x72},
959
+ {0x37c5, 0x72},
960
+ {0x37c6, 0x72},
961
+ {0x37ca, 0x21},
962
+ {0x37cc, 0x13},
963
+ {0x37cd, 0x90},
964
+ {0x37cf, 0x02},
965
+ {0x37d0, 0x00},
966
+ {0x37d1, 0x72},
967
+ {0x37d2, 0x01},
968
+ {0x37d3, 0x14},
969
+ {0x37d4, 0x00},
970
+ {0x37d5, 0x6c},
971
+ {0x37d6, 0x00},
972
+ {0x37d7, 0xf7},
973
+ {0x37d8, 0x01},
974
+ {0x37dc, 0x00},
975
+ {0x37dd, 0x00},
976
+ {0x37da, 0x00},
977
+ {0x37db, 0x00},
978
+ {0x3800, 0x00},
979
+ {0x3801, 0x00},
980
+ {0x3802, 0x00},
981
+ {0x3803, 0x00},
982
+ {0x3804, 0x0a},
983
+ {0x3805, 0x8f},
984
+ {0x3806, 0x05},
985
+ {0x3807, 0xff},
986
+ {0x3808, 0x0a},
987
+ {0x3809, 0x80},
988
+ {0x380a, 0x05},
989
+ {0x380b, 0xf0},
990
+ {0x380e, 0x06},
991
+ {0x380f, 0x58},
992
+ {0x3811, 0x08},
993
+ {0x3813, 0x08},
994
+ {0x3814, 0x01},
995
+ {0x3815, 0x01},
996
+ {0x3816, 0x01},
997
+ {0x3817, 0x01},
998
+ {0x3821, 0x00},
999
+ {0x3822, 0x14},
1000
+ {0x3823, 0x18},
1001
+ {0x3826, 0x00},
1002
+ {0x3827, 0x00},
1003
+ {0x384c, 0x02},
1004
+ {0x384d, 0xdc},
1005
+ {0x3858, 0x3c},
1006
+ {0x3865, 0x02},
1007
+ {0x3866, 0x00},
1008
+ {0x3867, 0x00},
1009
+ {0x3868, 0x02},
1010
+ {0x3900, 0x13},
1011
+ {0x3940, 0x13},
1012
+ {0x3980, 0x13},
1013
+ {0x3c01, 0x11},
1014
+ {0x3c05, 0x00},
1015
+ {0x3c0f, 0x1c},
1016
+ {0x3c12, 0x0d},
1017
+ {0x3c19, 0x00},
1018
+ {0x3c21, 0x00},
1019
+ {0x3c3a, 0x10},
1020
+ {0x3c3b, 0x18},
1021
+ {0x3c3d, 0xc6},
1022
+ {0x3c5a, 0x55},
1023
+ {0x3c5d, 0xcf},
1024
+ {0x3c5e, 0xcf},
1025
+ {0x3d8c, 0x70},
1026
+ {0x3d8d, 0x10},
1027
+ {0x4000, 0xf9},
1028
+ {0x4004, 0x00},
1029
+ {0x4005, 0x40},
1030
+ {0x4008, 0x02},
1031
+ {0x4009, 0x11},
1032
+ {0x400a, 0x06},
1033
+ {0x400b, 0x40},
1034
+ {0x400e, 0x40},
1035
+ {0x402e, 0x00},
1036
+ {0x402f, 0x40},
1037
+ {0x4030, 0x00},
1038
+ {0x4031, 0x40},
1039
+ {0x4032, 0x0f},
1040
+ {0x4033, 0x80},
1041
+ {0x4050, 0x00},
1042
+ {0x4051, 0x07},
1043
+ {0x4011, 0xbb},
1044
+ {0x410f, 0x01},
1045
+ {0x4289, 0x00},
1046
+ {0x428a, 0x46},
1047
+ {0x430b, 0x0f},
1048
+ {0x430c, 0xfc},
1049
+ {0x430d, 0x00},
1050
+ {0x430e, 0x00},
1051
+ {0x4314, 0x04},
1052
+ {0x4500, 0x18},
1053
+ {0x4501, 0x18},
1054
+ {0x4503, 0x10},
1055
+ {0x4504, 0x00},
1056
+ {0x4506, 0x32},
1057
+ {0x4601, 0x30},
1058
+ {0x4603, 0x00},
1059
+ {0x460a, 0x50},
1060
+ {0x460c, 0x60},
1061
+ {0x4640, 0x62},
1062
+ {0x4646, 0xaa},
1063
+ {0x4647, 0x55},
1064
+ {0x4648, 0x99},
1065
+ {0x4649, 0x66},
1066
+ {0x464d, 0x00},
1067
+ {0x4654, 0x11},
1068
+ {0x4655, 0x22},
1069
+ {0x4800, 0x44},
1070
+ {0x4810, 0xff},
1071
+ {0x4811, 0xff},
1072
+ {0x481f, 0x30},
1073
+ {0x4d00, 0x4d},
1074
+ {0x4d01, 0x9d},
1075
+ {0x4d02, 0xb9},
1076
+ {0x4d03, 0x2e},
1077
+ {0x4d04, 0x4a},
1078
+ {0x4d05, 0x3d},
1079
+ {0x4d09, 0x4f},
1080
+ {0x5000, 0x1f},
1081
+ {0x5080, 0x00},
1082
+ {0x50c0, 0x00},
1083
+ {0x5100, 0x00},
1084
+ {0x5200, 0x00},
1085
+ {0x5201, 0x00},
1086
+ {0x5202, 0x03},
1087
+ {0x5203, 0xff},
1088
+ {0x5780, 0x53},
1089
+ {0x5782, 0x18},
1090
+ {0x5783, 0x3c},
1091
+ {0x5786, 0x01},
1092
+ {0x5788, 0x18},
1093
+ {0x5789, 0x3c},
1094
+ {0x5792, 0x11},
1095
+ {0x5793, 0x33},
1096
+ {0x5857, 0xff},
1097
+ {0x5858, 0xff},
1098
+ {0x5859, 0xff},
1099
+ {0x58d7, 0xff},
1100
+ {0x58d8, 0xff},
1101
+ {0x58d9, 0xff},
1102
+ {REG_NULL, 0x00},
1103
+};
1104
+
1105
+static const struct regval os04a10_linear10bit_2688x1520_regs_2lane[] = {
1106
+ {0x0305, 0x5c},
1107
+ {0x0325, 0xd8},
1108
+ {0x3667, 0xd4},
1109
+ {0x3671, 0x08},
1110
+ {0x376c, 0x14},
1111
+ {0x380c, 0x08},
1112
+ {0x380d, 0x94},
1113
+ {0x381c, 0x00},
1114
+ {0x3820, 0x02},
1115
+ {0x3833, 0x40},
1116
+ {0x3c55, 0x08},
1117
+ {0x4001, 0x2f},
1118
+ {0x4288, 0xcf},
1119
+ {0x4507, 0x02},
1120
+ {0x480e, 0x00},
1121
+ {0x4813, 0x00},
1122
+ {0x4837, 0x0e},
1123
+ {0x484b, 0x27},
1124
+ {0x5001, 0x0d},
1125
+ {REG_NULL, 0x00},
1126
+};
1127
+
1128
+static const struct regval os04a10_hdr10bit_2688x1520_regs_2lane[] = {
1129
+ {0x0305, 0x78},
1130
+ {0x0325, 0x90},
1131
+ {0x3667, 0x54},
1132
+ {0x3671, 0x09},
1133
+ {0x376c, 0x04},
1134
+ {0x380c, 0x02},
1135
+ {0x380d, 0xdc},
1136
+ {0x381c, 0x08},
1137
+ {0x3820, 0x03},
1138
+ {0x3833, 0x41},
1139
+ {0x3c55, 0xcb},
1140
+ {0x4001, 0xef},
1141
+ {0x4288, 0xce},
1142
+ {0x4507, 0x03},
1143
+ {0x480e, 0x04},
1144
+ {0x4813, 0x84},
1145
+ {0x4837, 0x07},
1146
+ {0x484b, 0x67},
1147
+ {0x4883, 0x05},
1148
+ {0x4884, 0x08},
1149
+ {0x4885, 0x03},
1150
+ {0x5001, 0x0c},
1151
+ {REG_NULL, 0x00},
1152
+};
1153
+
7961154 /*
7971155 * The width and height must be configured to be
7981156 * the same as the current output resolution of the sensor.
....@@ -817,8 +1175,11 @@
8171175 .exp_def = 0x0240,
8181176 .hts_def = 0x02dc * 4,
8191177 .vts_def = 0x0cb0,
1178
+ .global_reg_list = os04a10_global_regs,
8201179 .reg_list = os04a10_linear10bit_2688x1520_regs,
8211180 .hdr_mode = NO_HDR,
1181
+ .link_freq_idx = 0,
1182
+ .bpp = 10,
8221183 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
8231184 },
8241185 {
....@@ -834,8 +1195,11 @@
8341195 .hts_def = 0x02dc * 4,
8351196 .vts_def = 0x0658,
8361197 /*.vts_def = 0x0cb0,*/
1198
+ .global_reg_list = os04a10_global_regs,
8371199 .reg_list = os04a10_hdr10bit_2688x1520_regs,
8381200 .hdr_mode = HDR_X2,
1201
+ .link_freq_idx = 0,
1202
+ .bpp = 10,
8391203 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
8401204 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
8411205 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
....@@ -852,8 +1216,11 @@
8521216 .exp_def = 0x0240,
8531217 .hts_def = 0x05c4 * 2,
8541218 .vts_def = 0x0984,
1219
+ .global_reg_list = os04a10_global_regs,
8551220 .reg_list = os04a10_linear12bit_2688x1520_regs,
8561221 .hdr_mode = NO_HDR,
1222
+ .link_freq_idx = 1,
1223
+ .bpp = 12,
8571224 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
8581225 },
8591226 {
....@@ -867,8 +1234,11 @@
8671234 .exp_def = 0x0240,
8681235 .hts_def = 0x05c4 * 2,
8691236 .vts_def = 0x0658,
1237
+ .global_reg_list = os04a10_global_regs,
8701238 .reg_list = os04a10_hdr12bit_2688x1520_regs,
8711239 .hdr_mode = HDR_X2,
1240
+ .link_freq_idx = 1,
1241
+ .bpp = 12,
8721242 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
8731243 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
8741244 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
....@@ -885,8 +1255,55 @@
8851255 .exp_def = 0x0200,
8861256 .hts_def = 0x05a0 * 2,
8871257 .vts_def = 0x05dc,
1258
+ .global_reg_list = os04a10_global_regs,
8881259 .reg_list = os04a10_hdr12bit_2560x1440_regs,
8891260 .hdr_mode = HDR_X2,
1261
+ .link_freq_idx = 1,
1262
+ .bpp = 12,
1263
+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
1264
+ .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
1265
+ .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
1266
+ .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
1267
+ },
1268
+};
1269
+
1270
+static const struct os04a10_mode supported_modes_2lane[] = {
1271
+ {
1272
+ .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
1273
+ .width = 2688,
1274
+ .height = 1520,
1275
+ .max_fps = {
1276
+ .numerator = 10000,
1277
+ .denominator = 302834,
1278
+ },
1279
+ .exp_def = 0x0640,
1280
+ .hts_def = 0x0894,
1281
+ .vts_def = 0x0658,
1282
+ .global_reg_list = os04a10_global_regs_2lane,
1283
+ .reg_list = os04a10_linear10bit_2688x1520_regs_2lane,
1284
+ .hdr_mode = NO_HDR,
1285
+ .link_freq_idx = 0,
1286
+ .bpp = 10,
1287
+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
1288
+ },
1289
+ {
1290
+ .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
1291
+ .width = 2688,
1292
+ .height = 1520,
1293
+ .max_fps = {
1294
+ .numerator = 10000,
1295
+ .denominator = 302834,
1296
+ /*.denominator = 151417,*/
1297
+ },
1298
+ .exp_def = 0x0640,
1299
+ .hts_def = 0x02dc * 4,
1300
+ .vts_def = 0x0658,
1301
+ /*.vts_def = 0x0cb0,*/
1302
+ .global_reg_list = os04a10_global_regs_2lane,
1303
+ .reg_list = os04a10_hdr10bit_2688x1520_regs_2lane,
1304
+ .hdr_mode = HDR_X2,
1305
+ .link_freq_idx = 2,
1306
+ .bpp = 10,
8901307 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
8911308 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
8921309 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
....@@ -897,6 +1314,7 @@
8971314 static const s64 link_freq_menu_items[] = {
8981315 MIPI_FREQ_360M,
8991316 MIPI_FREQ_648M,
1317
+ MIPI_FREQ_720M,
9001318 };
9011319
9021320 static const char * const os04a10_test_pattern_menu[] = {
....@@ -1005,15 +1423,15 @@
10051423 unsigned int i;
10061424
10071425 for (i = 0; i < os04a10->cfg_num; i++) {
1008
- dist = os04a10_get_reso_dist(&supported_modes[i], framefmt);
1009
- if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
1010
- (supported_modes[i].bus_fmt == framefmt->code)) {
1426
+ dist = os04a10_get_reso_dist(&os04a10->supported_modes[i], framefmt);
1427
+ if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
1428
+ (os04a10->supported_modes[i].bus_fmt == framefmt->code)) {
10111429 cur_best_fit_dist = dist;
10121430 cur_best_fit = i;
10131431 }
10141432 }
10151433
1016
- return &supported_modes[cur_best_fit];
1434
+ return &os04a10->supported_modes[cur_best_fit];
10171435 }
10181436
10191437 static int os04a10_set_fmt(struct v4l2_subdev *sd,
....@@ -1025,6 +1443,7 @@
10251443 s64 h_blank, vblank_def;
10261444 u64 dst_link_freq = 0;
10271445 u64 dst_pixel_rate = 0;
1446
+ u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
10281447
10291448 mutex_lock(&os04a10->mutex);
10301449
....@@ -1049,28 +1468,9 @@
10491468 __v4l2_ctrl_modify_range(os04a10->vblank, vblank_def,
10501469 OS04A10_VTS_MAX - mode->height,
10511470 1, vblank_def);
1052
- if (mode->hdr_mode == NO_HDR) {
1053
- if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
1054
- dst_link_freq = 0;
1055
- dst_pixel_rate = PIXEL_RATE_WITH_360M;
1056
- } else {
1057
- dst_link_freq = 1;
1058
- dst_pixel_rate = PIXEL_RATE_WITH_648M;
1059
- }
1060
- } else if (mode->hdr_mode == HDR_X2) {
1061
- if (mode->width == 2560 && mode->height == 1440) {
1062
- dst_link_freq = 1;
1063
- dst_pixel_rate = PIXEL_RATE_WITH_648M;
1064
- } else {
1065
- if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
1066
- dst_link_freq = 0;
1067
- dst_pixel_rate = PIXEL_RATE_WITH_360M;
1068
- } else {
1069
- dst_link_freq = 1;
1070
- dst_pixel_rate = PIXEL_RATE_WITH_648M;
1071
- }
1072
- }
1073
- }
1471
+ dst_link_freq = mode->link_freq_idx;
1472
+ dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
1473
+ mode->bpp * 2 * lanes;
10741474 __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate,
10751475 dst_pixel_rate);
10761476 __v4l2_ctrl_s_ctrl(os04a10->link_freq,
....@@ -1134,13 +1534,13 @@
11341534 if (fse->index >= os04a10->cfg_num)
11351535 return -EINVAL;
11361536
1137
- if (fse->code != supported_modes[fse->index].bus_fmt)
1537
+ if (fse->code != os04a10->supported_modes[fse->index].bus_fmt)
11381538 return -EINVAL;
11391539
1140
- fse->min_width = supported_modes[fse->index].width;
1141
- fse->max_width = supported_modes[fse->index].width;
1142
- fse->max_height = supported_modes[fse->index].height;
1143
- fse->min_height = supported_modes[fse->index].height;
1540
+ fse->min_width = os04a10->supported_modes[fse->index].width;
1541
+ fse->max_width = os04a10->supported_modes[fse->index].width;
1542
+ fse->max_height = os04a10->supported_modes[fse->index].height;
1543
+ fse->min_height = os04a10->supported_modes[fse->index].height;
11441544
11451545 return 0;
11461546 }
....@@ -1167,31 +1567,30 @@
11671567 struct os04a10 *os04a10 = to_os04a10(sd);
11681568 const struct os04a10_mode *mode = os04a10->cur_mode;
11691569
1170
- mutex_lock(&os04a10->mutex);
11711570 fi->interval = mode->max_fps;
1172
- mutex_unlock(&os04a10->mutex);
11731571
11741572 return 0;
11751573 }
11761574
1177
-static int os04a10_g_mbus_config(struct v4l2_subdev *sd,
1575
+static int os04a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
11781576 struct v4l2_mbus_config *config)
11791577 {
11801578 struct os04a10 *os04a10 = to_os04a10(sd);
11811579 const struct os04a10_mode *mode = os04a10->cur_mode;
11821580 u32 val = 0;
1581
+ u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
11831582
11841583 if (mode->hdr_mode == NO_HDR)
1185
- val = 1 << (OS04A10_LANES - 1) |
1584
+ val = 1 << (lanes - 1) |
11861585 V4L2_MBUS_CSI2_CHANNEL_0 |
11871586 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
11881587 if (mode->hdr_mode == HDR_X2)
1189
- val = 1 << (OS04A10_LANES - 1) |
1588
+ val = 1 << (lanes - 1) |
11901589 V4L2_MBUS_CSI2_CHANNEL_0 |
11911590 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
11921591 V4L2_MBUS_CSI2_CHANNEL_1;
11931592
1194
- config->type = V4L2_MBUS_CSI2;
1593
+ config->type = V4L2_MBUS_CSI2_DPHY;
11951594 config->flags = val;
11961595
11971596 return 0;
....@@ -1201,10 +1600,10 @@
12011600 struct rkmodule_inf *inf)
12021601 {
12031602 memset(inf, 0, sizeof(*inf));
1204
- strlcpy(inf->base.sensor, OS04A10_NAME, sizeof(inf->base.sensor));
1205
- strlcpy(inf->base.module, os04a10->module_name,
1603
+ strscpy(inf->base.sensor, OS04A10_NAME, sizeof(inf->base.sensor));
1604
+ strscpy(inf->base.module, os04a10->module_name,
12061605 sizeof(inf->base.module));
1207
- strlcpy(inf->base.lens, os04a10->len_name, sizeof(inf->base.lens));
1606
+ strscpy(inf->base.lens, os04a10->len_name, sizeof(inf->base.lens));
12081607 }
12091608
12101609 static int os04a10_set_hdrae(struct os04a10 *os04a10,
....@@ -1455,6 +1854,10 @@
14551854 long ret = 0;
14561855 u32 i, h, w;
14571856 u32 stream = 0;
1857
+ u64 dst_link_freq = 0;
1858
+ u64 dst_pixel_rate = 0;
1859
+ u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
1860
+ const struct os04a10_mode *mode;
14581861
14591862 switch (cmd) {
14601863 case PREISP_CMD_SET_HDRAE_EXP:
....@@ -1464,10 +1867,10 @@
14641867 w = os04a10->cur_mode->width;
14651868 h = os04a10->cur_mode->height;
14661869 for (i = 0; i < os04a10->cfg_num; i++) {
1467
- if (w == supported_modes[i].width &&
1468
- h == supported_modes[i].height &&
1469
- supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1470
- os04a10->cur_mode = &supported_modes[i];
1870
+ if (w == os04a10->supported_modes[i].width &&
1871
+ h == os04a10->supported_modes[i].height &&
1872
+ os04a10->supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
1873
+ os04a10->cur_mode = &os04a10->supported_modes[i];
14711874 break;
14721875 }
14731876 }
....@@ -1477,12 +1880,20 @@
14771880 hdr_cfg->hdr_mode, w, h);
14781881 ret = -EINVAL;
14791882 } else {
1480
- w = os04a10->cur_mode->hts_def - os04a10->cur_mode->width;
1481
- h = os04a10->cur_mode->vts_def - os04a10->cur_mode->height;
1883
+ mode = os04a10->cur_mode;
1884
+ w = mode->hts_def - mode->width;
1885
+ h = mode->vts_def - mode->height;
14821886 __v4l2_ctrl_modify_range(os04a10->hblank, w, w, 1, w);
14831887 __v4l2_ctrl_modify_range(os04a10->vblank, h,
14841888 OS04A10_VTS_MAX - os04a10->cur_mode->height,
14851889 1, h);
1890
+ dst_link_freq = mode->link_freq_idx;
1891
+ dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
1892
+ mode->bpp * 2 * lanes;
1893
+ __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate,
1894
+ dst_pixel_rate);
1895
+ __v4l2_ctrl_s_ctrl(os04a10->link_freq,
1896
+ dst_link_freq);
14861897 dev_info(&os04a10->client->dev,
14871898 "sensor mode: %d\n",
14881899 os04a10->cur_mode->hdr_mode);
....@@ -1535,7 +1946,6 @@
15351946 {
15361947 void __user *up = compat_ptr(arg);
15371948 struct rkmodule_inf *inf;
1538
- struct rkmodule_awb_cfg *cfg;
15391949 struct rkmodule_hdr_cfg *hdr;
15401950 struct preisp_hdrae_exp_s *hdrae;
15411951 struct rkmodule_dcg_ratio *dcg;
....@@ -1552,21 +1962,12 @@
15521962 }
15531963
15541964 ret = os04a10_ioctl(sd, cmd, inf);
1555
- if (!ret)
1965
+ if (!ret) {
15561966 ret = copy_to_user(up, inf, sizeof(*inf));
1557
- kfree(inf);
1558
- break;
1559
- case RKMODULE_AWB_CFG:
1560
- cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1561
- if (!cfg) {
1562
- ret = -ENOMEM;
1563
- return ret;
1967
+ if (ret)
1968
+ ret = -EFAULT;
15641969 }
1565
-
1566
- ret = copy_from_user(cfg, up, sizeof(*cfg));
1567
- if (!ret)
1568
- ret = os04a10_ioctl(sd, cmd, cfg);
1569
- kfree(cfg);
1970
+ kfree(inf);
15701971 break;
15711972 case RKMODULE_GET_HDR_CFG:
15721973 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
....@@ -1576,8 +1977,11 @@
15761977 }
15771978
15781979 ret = os04a10_ioctl(sd, cmd, hdr);
1579
- if (!ret)
1980
+ if (!ret) {
15801981 ret = copy_to_user(up, hdr, sizeof(*hdr));
1982
+ if (ret)
1983
+ ret = -EFAULT;
1984
+ }
15811985 kfree(hdr);
15821986 break;
15831987 case RKMODULE_SET_HDR_CFG:
....@@ -1587,9 +1991,10 @@
15871991 return ret;
15881992 }
15891993
1590
- ret = copy_from_user(hdr, up, sizeof(*hdr));
1591
- if (!ret)
1592
- ret = os04a10_ioctl(sd, cmd, hdr);
1994
+ if (copy_from_user(hdr, up, sizeof(*hdr)))
1995
+ return -EFAULT;
1996
+
1997
+ ret = os04a10_ioctl(sd, cmd, hdr);
15931998 kfree(hdr);
15941999 break;
15952000 case PREISP_CMD_SET_HDRAE_EXP:
....@@ -1599,20 +2004,23 @@
15992004 return ret;
16002005 }
16012006
1602
- ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1603
- if (!ret)
1604
- ret = os04a10_ioctl(sd, cmd, hdrae);
2007
+ if (copy_from_user(hdrae, up, sizeof(*hdrae)))
2008
+ return -EFAULT;
2009
+
2010
+ ret = os04a10_ioctl(sd, cmd, hdrae);
16052011 kfree(hdrae);
16062012 break;
16072013 case RKMODULE_SET_CONVERSION_GAIN:
1608
- ret = copy_from_user(&cg, up, sizeof(cg));
1609
- if (!ret)
1610
- ret = os04a10_ioctl(sd, cmd, &cg);
2014
+ if (copy_from_user(&cg, up, sizeof(cg)))
2015
+ return -EFAULT;
2016
+
2017
+ ret = os04a10_ioctl(sd, cmd, &cg);
16112018 break;
16122019 case RKMODULE_SET_QUICK_STREAM:
1613
- ret = copy_from_user(&stream, up, sizeof(u32));
1614
- if (!ret)
1615
- ret = os04a10_ioctl(sd, cmd, &stream);
2020
+ if (copy_from_user(&stream, up, sizeof(u32)))
2021
+ return -EFAULT;
2022
+
2023
+ ret = os04a10_ioctl(sd, cmd, &stream);
16162024 break;
16172025 case RKMODULE_GET_DCG_RATIO:
16182026 dcg = kzalloc(sizeof(*dcg), GFP_KERNEL);
....@@ -1622,8 +2030,11 @@
16222030 }
16232031
16242032 ret = os04a10_ioctl(sd, cmd, dcg);
1625
- if (!ret)
2033
+ if (!ret) {
16262034 ret = copy_to_user(up, dcg, sizeof(*dcg));
2035
+ if (ret)
2036
+ return -EFAULT;
2037
+ }
16272038 kfree(dcg);
16282039 break;
16292040 default:
....@@ -1645,14 +2056,17 @@
16452056 OS04A10_REG_HCG_SWITCH,
16462057 OS04A10_REG_VALUE_08BIT,
16472058 &val);
1648
- val |= 0x70;
2059
+ val &= ~0x70;
2060
+ if (!os04a10->long_hcg)
2061
+ val |= 0x10;
2062
+ if (!os04a10->middle_hcg)
2063
+ val |= 0x20;
2064
+ if (!os04a10->short_hcg)
2065
+ val |= 0x40;
16492066 ret |= os04a10_write_reg(client,
16502067 OS04A10_REG_HCG_SWITCH,
16512068 OS04A10_REG_VALUE_08BIT,
16522069 val);
1653
- os04a10->long_hcg = false;
1654
- os04a10->middle_hcg = false;
1655
- os04a10->short_hcg = false;
16562070 return ret;
16572071 }
16582072
....@@ -1661,13 +2075,6 @@
16612075 int ret;
16622076
16632077 if (!os04a10->is_thunderboot) {
1664
- ret = os04a10_write_array(os04a10->client, os04a10_global_regs);
1665
- if (ret) {
1666
- dev_err(&os04a10->client->dev,
1667
- "could not set init registers\n");
1668
- return ret;
1669
- }
1670
-
16712078 ret = os04a10_write_array(os04a10->client, os04a10->cur_mode->reg_list);
16722079 if (ret)
16732080 return ret;
....@@ -1768,6 +2175,13 @@
17682175 OS04A10_REG_VALUE_08BIT,
17692176 0x01);
17702177 usleep_range(100, 200);
2178
+ ret |= os04a10_write_array(os04a10->client,
2179
+ os04a10->cur_mode->global_reg_list);
2180
+ if (ret) {
2181
+ dev_err(&os04a10->client->dev,
2182
+ "could not set init registers\n");
2183
+ goto unlock_and_return;
2184
+ }
17712185 }
17722186
17732187 os04a10->power_on = true;
....@@ -1821,7 +2235,7 @@
18212235 dev_err(dev, "Failed to enable regulators\n");
18222236 goto disable_clk;
18232237 }
1824
-
2238
+ usleep_range(25000, 30000);
18252239 if (!IS_ERR(os04a10->reset_gpio))
18262240 gpiod_direction_output(os04a10->reset_gpio, 0);
18272241
....@@ -1881,9 +2295,10 @@
18812295 os04a10->is_thunderboot_ng = false;
18822296 regulator_bulk_disable(OS04A10_NUM_SUPPLIES, os04a10->supplies);
18832297 }
2298
+ usleep_range(30000, 31000);
18842299 }
18852300
1886
-static int os04a10_runtime_resume(struct device *dev)
2301
+static int __maybe_unused os04a10_runtime_resume(struct device *dev)
18872302 {
18882303 struct i2c_client *client = to_i2c_client(dev);
18892304 struct v4l2_subdev *sd = i2c_get_clientdata(client);
....@@ -1892,7 +2307,7 @@
18922307 return __os04a10_power_on(os04a10);
18932308 }
18942309
1895
-static int os04a10_runtime_suspend(struct device *dev)
2310
+static int __maybe_unused os04a10_runtime_suspend(struct device *dev)
18962311 {
18972312 struct i2c_client *client = to_i2c_client(dev);
18982313 struct v4l2_subdev *sd = i2c_get_clientdata(client);
....@@ -1909,7 +2324,7 @@
19092324 struct os04a10 *os04a10 = to_os04a10(sd);
19102325 struct v4l2_mbus_framefmt *try_fmt =
19112326 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1912
- const struct os04a10_mode *def_mode = &supported_modes[0];
2327
+ const struct os04a10_mode *def_mode = &os04a10->supported_modes[0];
19132328
19142329 mutex_lock(&os04a10->mutex);
19152330 /* Initialize try_fmt */
....@@ -1934,11 +2349,11 @@
19342349 if (fie->index >= os04a10->cfg_num)
19352350 return -EINVAL;
19362351
1937
- fie->code = supported_modes[fie->index].bus_fmt;
1938
- fie->width = supported_modes[fie->index].width;
1939
- fie->height = supported_modes[fie->index].height;
1940
- fie->interval = supported_modes[fie->index].max_fps;
1941
- fie->reserved[0] = supported_modes[fie->index].hdr_mode;
2352
+ fie->code = os04a10->supported_modes[fie->index].bus_fmt;
2353
+ fie->width = os04a10->supported_modes[fie->index].width;
2354
+ fie->height = os04a10->supported_modes[fie->index].height;
2355
+ fie->interval = os04a10->supported_modes[fie->index].max_fps;
2356
+ fie->reserved[0] = os04a10->supported_modes[fie->index].hdr_mode;
19422357 return 0;
19432358 }
19442359
....@@ -1964,7 +2379,6 @@
19642379 static const struct v4l2_subdev_video_ops os04a10_video_ops = {
19652380 .s_stream = os04a10_s_stream,
19662381 .g_frame_interval = os04a10_g_frame_interval,
1967
- .g_mbus_config = os04a10_g_mbus_config,
19682382 };
19692383
19702384 static const struct v4l2_subdev_pad_ops os04a10_pad_ops = {
....@@ -1973,6 +2387,7 @@
19732387 .enum_frame_interval = os04a10_enum_frame_interval,
19742388 .get_fmt = os04a10_get_fmt,
19752389 .set_fmt = os04a10_set_fmt,
2390
+ .get_mbus_config = os04a10_g_mbus_config,
19762391 };
19772392
19782393 static const struct v4l2_subdev_ops os04a10_subdev_ops = {
....@@ -2052,7 +2467,7 @@
20522467 val |= MIRROR_BIT_MASK;
20532468 else
20542469 val &= ~MIRROR_BIT_MASK;
2055
- ret = os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
2470
+ ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
20562471 OS04A10_REG_VALUE_08BIT,
20572472 val);
20582473 if (ret == 0)
....@@ -2066,7 +2481,7 @@
20662481 val |= FLIP_BIT_MASK;
20672482 else
20682483 val &= ~FLIP_BIT_MASK;
2069
- ret = os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
2484
+ ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
20702485 OS04A10_REG_VALUE_08BIT,
20712486 val);
20722487 if (ret == 0)
....@@ -2096,6 +2511,7 @@
20962511 int ret;
20972512 u64 dst_link_freq = 0;
20982513 u64 dst_pixel_rate = 0;
2514
+ u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
20992515
21002516 handler = &os04a10->ctrl_handler;
21012517 mode = os04a10->cur_mode;
....@@ -2106,23 +2522,18 @@
21062522
21072523 os04a10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
21082524 V4L2_CID_LINK_FREQ,
2109
- 1, 0, link_freq_menu_items);
2525
+ ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
21102526
2111
- if (os04a10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
2112
- dst_link_freq = 0;
2113
- dst_pixel_rate = PIXEL_RATE_WITH_360M;
2114
- } else {
2115
- dst_link_freq = 1;
2116
- dst_pixel_rate = PIXEL_RATE_WITH_648M;
2117
- }
2527
+ dst_link_freq = mode->link_freq_idx;
2528
+ dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
2529
+ mode->bpp * 2 * lanes;
21182530 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
21192531 os04a10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
21202532 V4L2_CID_PIXEL_RATE,
21212533 0, PIXEL_RATE_WITH_648M,
21222534 1, dst_pixel_rate);
21232535
2124
- __v4l2_ctrl_s_ctrl(os04a10->link_freq,
2125
- dst_link_freq);
2536
+ __v4l2_ctrl_s_ctrl(os04a10->link_freq, dst_link_freq);
21262537
21272538 h_blank = mode->hts_def - mode->width;
21282539 os04a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
....@@ -2170,6 +2581,8 @@
21702581 os04a10->long_hcg = false;
21712582 os04a10->middle_hcg = false;
21722583 os04a10->short_hcg = false;
2584
+ if (!os04a10->is_thunderboot)
2585
+ os04a10->is_thunderboot_ng = true;
21732586
21742587 return 0;
21752588
....@@ -2252,6 +2665,7 @@
22522665 struct device_node *node = dev->of_node;
22532666 struct os04a10 *os04a10;
22542667 struct v4l2_subdev *sd;
2668
+ struct device_node *endpoint;
22552669 char facing[2];
22562670 int ret;
22572671 u32 i, hdr_mode = 0;
....@@ -2285,10 +2699,33 @@
22852699 hdr_mode = NO_HDR;
22862700 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
22872701 }
2288
- os04a10->cfg_num = ARRAY_SIZE(supported_modes);
2702
+ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
2703
+ if (!endpoint) {
2704
+ dev_err(dev, "Failed to get endpoint\n");
2705
+ return -EINVAL;
2706
+ }
2707
+
2708
+ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
2709
+ &os04a10->bus_cfg);
2710
+ if (ret) {
2711
+ dev_err(dev, "Failed to get bus config\n");
2712
+ return -EINVAL;
2713
+ }
2714
+ if (os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) {
2715
+ os04a10->supported_modes = supported_modes;
2716
+ os04a10->cfg_num = ARRAY_SIZE(supported_modes);
2717
+ dev_info(dev, "detect os04a10 lane %d\n",
2718
+ os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes);
2719
+ } else {
2720
+ os04a10->supported_modes = supported_modes_2lane;
2721
+ os04a10->cfg_num = ARRAY_SIZE(supported_modes_2lane);
2722
+ dev_info(dev, "detect os04a10 lane %d\n",
2723
+ os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes);
2724
+ }
2725
+
22892726 for (i = 0; i < os04a10->cfg_num; i++) {
22902727 if (hdr_mode == supported_modes[i].hdr_mode) {
2291
- os04a10->cur_mode = &supported_modes[i];
2728
+ os04a10->cur_mode = &os04a10->supported_modes[i];
22922729 break;
22932730 }
22942731 }
....@@ -2346,7 +2783,10 @@
23462783 ret = os04a10_check_sensor_id(os04a10, client);
23472784 if (ret)
23482785 goto err_power_off;
2786
+
23492787 ret = os04a10_get_dcg_ratio(os04a10);
2788
+ if (ret)
2789
+ dev_warn(dev, "get dcg ratio failed\n");
23502790
23512791 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
23522792 sd->internal_ops = &os04a10_internal_ops;