.. | .. |
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30 | 30 | #include <media/v4l2-subdev.h> |
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31 | 31 | #include <linux/pinctrl/consumer.h> |
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32 | 32 | #include <linux/rk-preisp.h> |
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| 33 | +#include <media/v4l2-fwnode.h> |
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| 34 | +#include <linux/of_graph.h> |
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33 | 35 | #include "../platform/rockchip/isp/rkisp_tb_helper.h" |
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34 | 36 | |
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35 | 37 | #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05) |
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.. | .. |
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40 | 42 | |
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41 | 43 | #define MIPI_FREQ_360M 360000000 |
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42 | 44 | #define MIPI_FREQ_648M 648000000 |
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| 45 | +#define MIPI_FREQ_720M 720000000 |
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43 | 46 | |
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44 | 47 | #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10 * 4) |
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45 | | -#define PIXEL_RATE_WITH_648M (MIPI_FREQ_648M * 2 / 12 * 4) |
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| 48 | +#define PIXEL_RATE_WITH_648M (MIPI_FREQ_648M * 2 / 10 * 4) |
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| 49 | +#define PIXEL_RATE_WITH_720M (MIPI_FREQ_720M * 2 / 10 * 4) |
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46 | 50 | |
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47 | 51 | #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" |
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48 | 52 | |
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.. | .. |
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100 | 104 | #define OS04A10_REG_VALUE_16BIT 2 |
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101 | 105 | #define OS04A10_REG_VALUE_24BIT 3 |
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102 | 106 | |
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103 | | -#define OS04A10_LANES 4 |
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104 | | - |
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105 | 107 | #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" |
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106 | 108 | #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" |
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107 | 109 | |
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108 | 110 | #define OS04A10_NAME "os04a10" |
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109 | 111 | |
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110 | 112 | #define USED_SYS_DEBUG |
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111 | | - |
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112 | | -struct preisp_hdrae_exp_s init_hdrae_exp; |
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113 | 113 | |
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114 | 114 | static const char * const os04a10_supply_names[] = { |
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115 | 115 | "avdd", /* Analog power */ |
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.. | .. |
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122 | 122 | #define OS04A10_FLIP_REG 0x3820 |
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123 | 123 | #define MIRROR_BIT_MASK BIT(1) |
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124 | 124 | #define FLIP_BIT_MASK BIT(2) |
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125 | | - |
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126 | | -enum os04a10_max_pad { |
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127 | | - PAD0, |
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128 | | - PAD1, |
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129 | | - PAD2, |
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130 | | - PAD3, |
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131 | | - PAD_MAX, |
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132 | | -}; |
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133 | 125 | |
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134 | 126 | struct regval { |
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135 | 127 | u16 addr; |
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.. | .. |
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144 | 136 | u32 hts_def; |
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145 | 137 | u32 vts_def; |
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146 | 138 | u32 exp_def; |
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| 139 | + const struct regval *global_reg_list; |
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147 | 140 | const struct regval *reg_list; |
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148 | 141 | u32 hdr_mode; |
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| 142 | + u32 link_freq_idx; |
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| 143 | + u32 bpp; |
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149 | 144 | u32 vc[PAD_MAX]; |
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150 | 145 | }; |
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151 | 146 | |
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.. | .. |
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176 | 171 | struct mutex mutex; |
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177 | 172 | bool streaming; |
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178 | 173 | bool power_on; |
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| 174 | + const struct os04a10_mode *supported_modes; |
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179 | 175 | const struct os04a10_mode *cur_mode; |
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180 | 176 | u32 cfg_num; |
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181 | 177 | u32 module_index; |
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.. | .. |
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192 | 188 | bool is_first_streamoff; |
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193 | 189 | u8 flip; |
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194 | 190 | u32 dcg_ratio; |
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| 191 | + struct v4l2_fwnode_endpoint bus_cfg; |
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195 | 192 | }; |
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196 | 193 | |
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197 | 194 | #define to_os04a10(sd) container_of(sd, struct os04a10, subdev) |
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.. | .. |
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793 | 790 | {REG_NULL, 0x00}, |
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794 | 791 | }; |
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795 | 792 | |
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| 793 | +static const struct regval os04a10_global_regs_2lane[] = { |
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| 794 | + {0x0109, 0x01}, |
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| 795 | + {0x0104, 0x02}, |
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| 796 | + {0x0102, 0x00}, |
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| 797 | + {0x0306, 0x00}, |
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| 798 | + {0x0307, 0x00}, |
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| 799 | + {0x0308, 0x04}, |
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| 800 | + {0x030a, 0x01}, |
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| 801 | + {0x0317, 0x09}, |
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| 802 | + {0x0322, 0x01}, |
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| 803 | + {0x0323, 0x02}, |
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| 804 | + {0x0324, 0x00}, |
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| 805 | + {0x0327, 0x05}, |
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| 806 | + {0x0329, 0x02}, |
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| 807 | + {0x032c, 0x02}, |
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| 808 | + {0x032d, 0x02}, |
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| 809 | + {0x032e, 0x02}, |
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| 810 | + {0x300f, 0x11}, |
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| 811 | + {0x3012, 0x21}, |
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| 812 | + {0x3026, 0x10}, |
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| 813 | + {0x3027, 0x08}, |
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| 814 | + {0x302d, 0x24}, |
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| 815 | + {0x3104, 0x01}, |
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| 816 | + {0x3106, 0x11}, |
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| 817 | + {0x3400, 0x00}, |
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| 818 | + {0x3408, 0x05}, |
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| 819 | + {0x340c, 0x0c}, |
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| 820 | + {0x340d, 0xb0}, |
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| 821 | + {0x3425, 0x51}, |
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| 822 | + {0x3426, 0x10}, |
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| 823 | + {0x3427, 0x14}, |
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| 824 | + {0x3428, 0x10}, |
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| 825 | + {0x3429, 0x10}, |
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| 826 | + {0x342a, 0x10}, |
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| 827 | + {0x342b, 0x04}, |
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| 828 | + {0x3501, 0x02}, |
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| 829 | + {0x3504, 0x08}, |
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| 830 | + {0x3508, 0x01}, |
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| 831 | + {0x3509, 0x00}, |
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| 832 | + {0x350a, 0x01}, |
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| 833 | + {0x3544, 0x08}, |
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| 834 | + {0x3548, 0x01}, |
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| 835 | + {0x3549, 0x00}, |
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| 836 | + {0x3584, 0x08}, |
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| 837 | + {0x3588, 0x01}, |
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| 838 | + {0x3589, 0x00}, |
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| 839 | + {0x3601, 0x70}, |
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| 840 | + {0x3604, 0xe3}, |
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| 841 | + {0x3605, 0x7f}, |
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| 842 | + {0x3606, 0x80}, |
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| 843 | + {0x3608, 0xa8}, |
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| 844 | + {0x360a, 0xd0}, |
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| 845 | + {0x360b, 0x08}, |
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| 846 | + {0x360e, 0xc8}, |
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| 847 | + {0x360f, 0x66}, |
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| 848 | + {0x3610, 0x89}, |
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| 849 | + {0x3611, 0x8a}, |
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| 850 | + {0x3612, 0x4e}, |
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| 851 | + {0x3613, 0xbd}, |
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| 852 | + {0x3614, 0x9b}, |
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| 853 | + {0x362a, 0x0e}, |
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| 854 | + {0x362b, 0x0e}, |
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| 855 | + {0x362c, 0x0e}, |
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| 856 | + {0x362d, 0x0e}, |
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| 857 | + {0x362e, 0x1a}, |
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| 858 | + {0x362f, 0x34}, |
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| 859 | + {0x3630, 0x67}, |
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| 860 | + {0x3631, 0x7f}, |
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| 861 | + {0x3638, 0x00}, |
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| 862 | + {0x3643, 0x00}, |
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| 863 | + {0x3644, 0x00}, |
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| 864 | + {0x3645, 0x00}, |
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| 865 | + {0x3646, 0x00}, |
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| 866 | + {0x3647, 0x00}, |
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| 867 | + {0x3648, 0x00}, |
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| 868 | + {0x3649, 0x00}, |
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| 869 | + {0x364a, 0x04}, |
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| 870 | + {0x364c, 0x0e}, |
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| 871 | + {0x364d, 0x0e}, |
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| 872 | + {0x364e, 0x0e}, |
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| 873 | + {0x364f, 0x0e}, |
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| 874 | + {0x3650, 0xff}, |
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| 875 | + {0x3651, 0xff}, |
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| 876 | + {0x365a, 0x00}, |
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| 877 | + {0x365b, 0x00}, |
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| 878 | + {0x365c, 0x00}, |
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| 879 | + {0x365d, 0x00}, |
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| 880 | + {0x3661, 0x07}, |
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| 881 | + {0x3662, 0x02}, |
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| 882 | + {0x3663, 0x20}, |
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| 883 | + {0x3665, 0x12}, |
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| 884 | + {0x3668, 0x80}, |
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| 885 | + {0x366c, 0x00}, |
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| 886 | + {0x366d, 0x00}, |
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| 887 | + {0x366e, 0x00}, |
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| 888 | + {0x366f, 0x00}, |
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| 889 | + {0x3673, 0x2a}, |
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| 890 | + {0x3681, 0x80}, |
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| 891 | + {0x3700, 0x2d}, |
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| 892 | + {0x3701, 0x22}, |
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| 893 | + {0x3702, 0x25}, |
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| 894 | + {0x3703, 0x20}, |
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| 895 | + {0x3705, 0x00}, |
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| 896 | + {0x3706, 0x72}, |
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| 897 | + {0x3707, 0x0a}, |
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| 898 | + {0x3708, 0x36}, |
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| 899 | + {0x3709, 0x57}, |
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| 900 | + {0x370a, 0x01}, |
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| 901 | + {0x370b, 0x14}, |
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| 902 | + {0x3714, 0x01}, |
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| 903 | + {0x3719, 0x1f}, |
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| 904 | + {0x371b, 0x16}, |
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| 905 | + {0x371c, 0x00}, |
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| 906 | + {0x371d, 0x08}, |
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| 907 | + {0x373f, 0x63}, |
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| 908 | + {0x3740, 0x63}, |
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| 909 | + {0x3741, 0x63}, |
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| 910 | + {0x3742, 0x63}, |
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| 911 | + {0x3743, 0x01}, |
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| 912 | + {0x3756, 0x9d}, |
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| 913 | + {0x3757, 0x9d}, |
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| 914 | + {0x3762, 0x1c}, |
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| 915 | + {0x3673, 0x2a}, |
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| 916 | + {0x3681, 0x80}, |
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| 917 | + {0x3700, 0x2d}, |
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| 918 | + {0x3701, 0x22}, |
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| 919 | + {0x3702, 0x25}, |
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| 920 | + {0x3703, 0x20}, |
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| 921 | + {0x3705, 0x00}, |
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| 922 | + {0x3706, 0x72}, |
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| 923 | + {0x3707, 0x0a}, |
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| 924 | + {0x3708, 0x36}, |
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| 925 | + {0x3709, 0x57}, |
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| 926 | + {0x370a, 0x01}, |
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| 927 | + {0x370b, 0x14}, |
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| 928 | + {0x3714, 0x01}, |
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| 929 | + {0x3719, 0x1f}, |
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| 930 | + {0x371b, 0x16}, |
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| 931 | + {0x371c, 0x00}, |
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| 932 | + {0x371d, 0x08}, |
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| 933 | + {0x373f, 0x63}, |
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| 934 | + {0x3740, 0x63}, |
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| 935 | + {0x3741, 0x63}, |
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| 936 | + {0x3742, 0x63}, |
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| 937 | + {0x3743, 0x01}, |
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| 938 | + {0x3756, 0x9d}, |
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| 939 | + {0x3757, 0x9d}, |
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| 940 | + {0x3762, 0x1c}, |
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| 941 | + {0x3776, 0x05}, |
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| 942 | + {0x3777, 0x22}, |
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| 943 | + {0x3779, 0x60}, |
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| 944 | + {0x377c, 0x48}, |
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| 945 | + {0x3784, 0x06}, |
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| 946 | + {0x3785, 0x0a}, |
---|
| 947 | + {0x3790, 0x10}, |
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| 948 | + {0x3793, 0x04}, |
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| 949 | + {0x3794, 0x07}, |
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| 950 | + {0x3796, 0x00}, |
---|
| 951 | + {0x3797, 0x02}, |
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| 952 | + {0x379c, 0x4d}, |
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| 953 | + {0x37a1, 0x80}, |
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| 954 | + {0x37bb, 0x88}, |
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| 955 | + {0x37be, 0x48}, |
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| 956 | + {0x37bf, 0x01}, |
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| 957 | + {0x37c0, 0x01}, |
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| 958 | + {0x37c4, 0x72}, |
---|
| 959 | + {0x37c5, 0x72}, |
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| 960 | + {0x37c6, 0x72}, |
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| 961 | + {0x37ca, 0x21}, |
---|
| 962 | + {0x37cc, 0x13}, |
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| 963 | + {0x37cd, 0x90}, |
---|
| 964 | + {0x37cf, 0x02}, |
---|
| 965 | + {0x37d0, 0x00}, |
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| 966 | + {0x37d1, 0x72}, |
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| 967 | + {0x37d2, 0x01}, |
---|
| 968 | + {0x37d3, 0x14}, |
---|
| 969 | + {0x37d4, 0x00}, |
---|
| 970 | + {0x37d5, 0x6c}, |
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| 971 | + {0x37d6, 0x00}, |
---|
| 972 | + {0x37d7, 0xf7}, |
---|
| 973 | + {0x37d8, 0x01}, |
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| 974 | + {0x37dc, 0x00}, |
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| 975 | + {0x37dd, 0x00}, |
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| 976 | + {0x37da, 0x00}, |
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| 977 | + {0x37db, 0x00}, |
---|
| 978 | + {0x3800, 0x00}, |
---|
| 979 | + {0x3801, 0x00}, |
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| 980 | + {0x3802, 0x00}, |
---|
| 981 | + {0x3803, 0x00}, |
---|
| 982 | + {0x3804, 0x0a}, |
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| 983 | + {0x3805, 0x8f}, |
---|
| 984 | + {0x3806, 0x05}, |
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| 985 | + {0x3807, 0xff}, |
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| 986 | + {0x3808, 0x0a}, |
---|
| 987 | + {0x3809, 0x80}, |
---|
| 988 | + {0x380a, 0x05}, |
---|
| 989 | + {0x380b, 0xf0}, |
---|
| 990 | + {0x380e, 0x06}, |
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| 991 | + {0x380f, 0x58}, |
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| 992 | + {0x3811, 0x08}, |
---|
| 993 | + {0x3813, 0x08}, |
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| 994 | + {0x3814, 0x01}, |
---|
| 995 | + {0x3815, 0x01}, |
---|
| 996 | + {0x3816, 0x01}, |
---|
| 997 | + {0x3817, 0x01}, |
---|
| 998 | + {0x3821, 0x00}, |
---|
| 999 | + {0x3822, 0x14}, |
---|
| 1000 | + {0x3823, 0x18}, |
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| 1001 | + {0x3826, 0x00}, |
---|
| 1002 | + {0x3827, 0x00}, |
---|
| 1003 | + {0x384c, 0x02}, |
---|
| 1004 | + {0x384d, 0xdc}, |
---|
| 1005 | + {0x3858, 0x3c}, |
---|
| 1006 | + {0x3865, 0x02}, |
---|
| 1007 | + {0x3866, 0x00}, |
---|
| 1008 | + {0x3867, 0x00}, |
---|
| 1009 | + {0x3868, 0x02}, |
---|
| 1010 | + {0x3900, 0x13}, |
---|
| 1011 | + {0x3940, 0x13}, |
---|
| 1012 | + {0x3980, 0x13}, |
---|
| 1013 | + {0x3c01, 0x11}, |
---|
| 1014 | + {0x3c05, 0x00}, |
---|
| 1015 | + {0x3c0f, 0x1c}, |
---|
| 1016 | + {0x3c12, 0x0d}, |
---|
| 1017 | + {0x3c19, 0x00}, |
---|
| 1018 | + {0x3c21, 0x00}, |
---|
| 1019 | + {0x3c3a, 0x10}, |
---|
| 1020 | + {0x3c3b, 0x18}, |
---|
| 1021 | + {0x3c3d, 0xc6}, |
---|
| 1022 | + {0x3c5a, 0x55}, |
---|
| 1023 | + {0x3c5d, 0xcf}, |
---|
| 1024 | + {0x3c5e, 0xcf}, |
---|
| 1025 | + {0x3d8c, 0x70}, |
---|
| 1026 | + {0x3d8d, 0x10}, |
---|
| 1027 | + {0x4000, 0xf9}, |
---|
| 1028 | + {0x4004, 0x00}, |
---|
| 1029 | + {0x4005, 0x40}, |
---|
| 1030 | + {0x4008, 0x02}, |
---|
| 1031 | + {0x4009, 0x11}, |
---|
| 1032 | + {0x400a, 0x06}, |
---|
| 1033 | + {0x400b, 0x40}, |
---|
| 1034 | + {0x400e, 0x40}, |
---|
| 1035 | + {0x402e, 0x00}, |
---|
| 1036 | + {0x402f, 0x40}, |
---|
| 1037 | + {0x4030, 0x00}, |
---|
| 1038 | + {0x4031, 0x40}, |
---|
| 1039 | + {0x4032, 0x0f}, |
---|
| 1040 | + {0x4033, 0x80}, |
---|
| 1041 | + {0x4050, 0x00}, |
---|
| 1042 | + {0x4051, 0x07}, |
---|
| 1043 | + {0x4011, 0xbb}, |
---|
| 1044 | + {0x410f, 0x01}, |
---|
| 1045 | + {0x4289, 0x00}, |
---|
| 1046 | + {0x428a, 0x46}, |
---|
| 1047 | + {0x430b, 0x0f}, |
---|
| 1048 | + {0x430c, 0xfc}, |
---|
| 1049 | + {0x430d, 0x00}, |
---|
| 1050 | + {0x430e, 0x00}, |
---|
| 1051 | + {0x4314, 0x04}, |
---|
| 1052 | + {0x4500, 0x18}, |
---|
| 1053 | + {0x4501, 0x18}, |
---|
| 1054 | + {0x4503, 0x10}, |
---|
| 1055 | + {0x4504, 0x00}, |
---|
| 1056 | + {0x4506, 0x32}, |
---|
| 1057 | + {0x4601, 0x30}, |
---|
| 1058 | + {0x4603, 0x00}, |
---|
| 1059 | + {0x460a, 0x50}, |
---|
| 1060 | + {0x460c, 0x60}, |
---|
| 1061 | + {0x4640, 0x62}, |
---|
| 1062 | + {0x4646, 0xaa}, |
---|
| 1063 | + {0x4647, 0x55}, |
---|
| 1064 | + {0x4648, 0x99}, |
---|
| 1065 | + {0x4649, 0x66}, |
---|
| 1066 | + {0x464d, 0x00}, |
---|
| 1067 | + {0x4654, 0x11}, |
---|
| 1068 | + {0x4655, 0x22}, |
---|
| 1069 | + {0x4800, 0x44}, |
---|
| 1070 | + {0x4810, 0xff}, |
---|
| 1071 | + {0x4811, 0xff}, |
---|
| 1072 | + {0x481f, 0x30}, |
---|
| 1073 | + {0x4d00, 0x4d}, |
---|
| 1074 | + {0x4d01, 0x9d}, |
---|
| 1075 | + {0x4d02, 0xb9}, |
---|
| 1076 | + {0x4d03, 0x2e}, |
---|
| 1077 | + {0x4d04, 0x4a}, |
---|
| 1078 | + {0x4d05, 0x3d}, |
---|
| 1079 | + {0x4d09, 0x4f}, |
---|
| 1080 | + {0x5000, 0x1f}, |
---|
| 1081 | + {0x5080, 0x00}, |
---|
| 1082 | + {0x50c0, 0x00}, |
---|
| 1083 | + {0x5100, 0x00}, |
---|
| 1084 | + {0x5200, 0x00}, |
---|
| 1085 | + {0x5201, 0x00}, |
---|
| 1086 | + {0x5202, 0x03}, |
---|
| 1087 | + {0x5203, 0xff}, |
---|
| 1088 | + {0x5780, 0x53}, |
---|
| 1089 | + {0x5782, 0x18}, |
---|
| 1090 | + {0x5783, 0x3c}, |
---|
| 1091 | + {0x5786, 0x01}, |
---|
| 1092 | + {0x5788, 0x18}, |
---|
| 1093 | + {0x5789, 0x3c}, |
---|
| 1094 | + {0x5792, 0x11}, |
---|
| 1095 | + {0x5793, 0x33}, |
---|
| 1096 | + {0x5857, 0xff}, |
---|
| 1097 | + {0x5858, 0xff}, |
---|
| 1098 | + {0x5859, 0xff}, |
---|
| 1099 | + {0x58d7, 0xff}, |
---|
| 1100 | + {0x58d8, 0xff}, |
---|
| 1101 | + {0x58d9, 0xff}, |
---|
| 1102 | + {REG_NULL, 0x00}, |
---|
| 1103 | +}; |
---|
| 1104 | + |
---|
| 1105 | +static const struct regval os04a10_linear10bit_2688x1520_regs_2lane[] = { |
---|
| 1106 | + {0x0305, 0x5c}, |
---|
| 1107 | + {0x0325, 0xd8}, |
---|
| 1108 | + {0x3667, 0xd4}, |
---|
| 1109 | + {0x3671, 0x08}, |
---|
| 1110 | + {0x376c, 0x14}, |
---|
| 1111 | + {0x380c, 0x08}, |
---|
| 1112 | + {0x380d, 0x94}, |
---|
| 1113 | + {0x381c, 0x00}, |
---|
| 1114 | + {0x3820, 0x02}, |
---|
| 1115 | + {0x3833, 0x40}, |
---|
| 1116 | + {0x3c55, 0x08}, |
---|
| 1117 | + {0x4001, 0x2f}, |
---|
| 1118 | + {0x4288, 0xcf}, |
---|
| 1119 | + {0x4507, 0x02}, |
---|
| 1120 | + {0x480e, 0x00}, |
---|
| 1121 | + {0x4813, 0x00}, |
---|
| 1122 | + {0x4837, 0x0e}, |
---|
| 1123 | + {0x484b, 0x27}, |
---|
| 1124 | + {0x5001, 0x0d}, |
---|
| 1125 | + {REG_NULL, 0x00}, |
---|
| 1126 | +}; |
---|
| 1127 | + |
---|
| 1128 | +static const struct regval os04a10_hdr10bit_2688x1520_regs_2lane[] = { |
---|
| 1129 | + {0x0305, 0x78}, |
---|
| 1130 | + {0x0325, 0x90}, |
---|
| 1131 | + {0x3667, 0x54}, |
---|
| 1132 | + {0x3671, 0x09}, |
---|
| 1133 | + {0x376c, 0x04}, |
---|
| 1134 | + {0x380c, 0x02}, |
---|
| 1135 | + {0x380d, 0xdc}, |
---|
| 1136 | + {0x381c, 0x08}, |
---|
| 1137 | + {0x3820, 0x03}, |
---|
| 1138 | + {0x3833, 0x41}, |
---|
| 1139 | + {0x3c55, 0xcb}, |
---|
| 1140 | + {0x4001, 0xef}, |
---|
| 1141 | + {0x4288, 0xce}, |
---|
| 1142 | + {0x4507, 0x03}, |
---|
| 1143 | + {0x480e, 0x04}, |
---|
| 1144 | + {0x4813, 0x84}, |
---|
| 1145 | + {0x4837, 0x07}, |
---|
| 1146 | + {0x484b, 0x67}, |
---|
| 1147 | + {0x4883, 0x05}, |
---|
| 1148 | + {0x4884, 0x08}, |
---|
| 1149 | + {0x4885, 0x03}, |
---|
| 1150 | + {0x5001, 0x0c}, |
---|
| 1151 | + {REG_NULL, 0x00}, |
---|
| 1152 | +}; |
---|
| 1153 | + |
---|
796 | 1154 | /* |
---|
797 | 1155 | * The width and height must be configured to be |
---|
798 | 1156 | * the same as the current output resolution of the sensor. |
---|
.. | .. |
---|
817 | 1175 | .exp_def = 0x0240, |
---|
818 | 1176 | .hts_def = 0x02dc * 4, |
---|
819 | 1177 | .vts_def = 0x0cb0, |
---|
| 1178 | + .global_reg_list = os04a10_global_regs, |
---|
820 | 1179 | .reg_list = os04a10_linear10bit_2688x1520_regs, |
---|
821 | 1180 | .hdr_mode = NO_HDR, |
---|
| 1181 | + .link_freq_idx = 0, |
---|
| 1182 | + .bpp = 10, |
---|
822 | 1183 | .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, |
---|
823 | 1184 | }, |
---|
824 | 1185 | { |
---|
.. | .. |
---|
834 | 1195 | .hts_def = 0x02dc * 4, |
---|
835 | 1196 | .vts_def = 0x0658, |
---|
836 | 1197 | /*.vts_def = 0x0cb0,*/ |
---|
| 1198 | + .global_reg_list = os04a10_global_regs, |
---|
837 | 1199 | .reg_list = os04a10_hdr10bit_2688x1520_regs, |
---|
838 | 1200 | .hdr_mode = HDR_X2, |
---|
| 1201 | + .link_freq_idx = 0, |
---|
| 1202 | + .bpp = 10, |
---|
839 | 1203 | .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
840 | 1204 | .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 |
---|
841 | 1205 | .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
.. | .. |
---|
852 | 1216 | .exp_def = 0x0240, |
---|
853 | 1217 | .hts_def = 0x05c4 * 2, |
---|
854 | 1218 | .vts_def = 0x0984, |
---|
| 1219 | + .global_reg_list = os04a10_global_regs, |
---|
855 | 1220 | .reg_list = os04a10_linear12bit_2688x1520_regs, |
---|
856 | 1221 | .hdr_mode = NO_HDR, |
---|
| 1222 | + .link_freq_idx = 1, |
---|
| 1223 | + .bpp = 12, |
---|
857 | 1224 | .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, |
---|
858 | 1225 | }, |
---|
859 | 1226 | { |
---|
.. | .. |
---|
867 | 1234 | .exp_def = 0x0240, |
---|
868 | 1235 | .hts_def = 0x05c4 * 2, |
---|
869 | 1236 | .vts_def = 0x0658, |
---|
| 1237 | + .global_reg_list = os04a10_global_regs, |
---|
870 | 1238 | .reg_list = os04a10_hdr12bit_2688x1520_regs, |
---|
871 | 1239 | .hdr_mode = HDR_X2, |
---|
| 1240 | + .link_freq_idx = 1, |
---|
| 1241 | + .bpp = 12, |
---|
872 | 1242 | .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
873 | 1243 | .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 |
---|
874 | 1244 | .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
.. | .. |
---|
885 | 1255 | .exp_def = 0x0200, |
---|
886 | 1256 | .hts_def = 0x05a0 * 2, |
---|
887 | 1257 | .vts_def = 0x05dc, |
---|
| 1258 | + .global_reg_list = os04a10_global_regs, |
---|
888 | 1259 | .reg_list = os04a10_hdr12bit_2560x1440_regs, |
---|
889 | 1260 | .hdr_mode = HDR_X2, |
---|
| 1261 | + .link_freq_idx = 1, |
---|
| 1262 | + .bpp = 12, |
---|
| 1263 | + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
| 1264 | + .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 |
---|
| 1265 | + .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
| 1266 | + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2 |
---|
| 1267 | + }, |
---|
| 1268 | +}; |
---|
| 1269 | + |
---|
| 1270 | +static const struct os04a10_mode supported_modes_2lane[] = { |
---|
| 1271 | + { |
---|
| 1272 | + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, |
---|
| 1273 | + .width = 2688, |
---|
| 1274 | + .height = 1520, |
---|
| 1275 | + .max_fps = { |
---|
| 1276 | + .numerator = 10000, |
---|
| 1277 | + .denominator = 302834, |
---|
| 1278 | + }, |
---|
| 1279 | + .exp_def = 0x0640, |
---|
| 1280 | + .hts_def = 0x0894, |
---|
| 1281 | + .vts_def = 0x0658, |
---|
| 1282 | + .global_reg_list = os04a10_global_regs_2lane, |
---|
| 1283 | + .reg_list = os04a10_linear10bit_2688x1520_regs_2lane, |
---|
| 1284 | + .hdr_mode = NO_HDR, |
---|
| 1285 | + .link_freq_idx = 0, |
---|
| 1286 | + .bpp = 10, |
---|
| 1287 | + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, |
---|
| 1288 | + }, |
---|
| 1289 | + { |
---|
| 1290 | + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, |
---|
| 1291 | + .width = 2688, |
---|
| 1292 | + .height = 1520, |
---|
| 1293 | + .max_fps = { |
---|
| 1294 | + .numerator = 10000, |
---|
| 1295 | + .denominator = 302834, |
---|
| 1296 | + /*.denominator = 151417,*/ |
---|
| 1297 | + }, |
---|
| 1298 | + .exp_def = 0x0640, |
---|
| 1299 | + .hts_def = 0x02dc * 4, |
---|
| 1300 | + .vts_def = 0x0658, |
---|
| 1301 | + /*.vts_def = 0x0cb0,*/ |
---|
| 1302 | + .global_reg_list = os04a10_global_regs_2lane, |
---|
| 1303 | + .reg_list = os04a10_hdr10bit_2688x1520_regs_2lane, |
---|
| 1304 | + .hdr_mode = HDR_X2, |
---|
| 1305 | + .link_freq_idx = 2, |
---|
| 1306 | + .bpp = 10, |
---|
890 | 1307 | .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
891 | 1308 | .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 |
---|
892 | 1309 | .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, |
---|
.. | .. |
---|
897 | 1314 | static const s64 link_freq_menu_items[] = { |
---|
898 | 1315 | MIPI_FREQ_360M, |
---|
899 | 1316 | MIPI_FREQ_648M, |
---|
| 1317 | + MIPI_FREQ_720M, |
---|
900 | 1318 | }; |
---|
901 | 1319 | |
---|
902 | 1320 | static const char * const os04a10_test_pattern_menu[] = { |
---|
.. | .. |
---|
1005 | 1423 | unsigned int i; |
---|
1006 | 1424 | |
---|
1007 | 1425 | for (i = 0; i < os04a10->cfg_num; i++) { |
---|
1008 | | - dist = os04a10_get_reso_dist(&supported_modes[i], framefmt); |
---|
1009 | | - if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) && |
---|
1010 | | - (supported_modes[i].bus_fmt == framefmt->code)) { |
---|
| 1426 | + dist = os04a10_get_reso_dist(&os04a10->supported_modes[i], framefmt); |
---|
| 1427 | + if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) && |
---|
| 1428 | + (os04a10->supported_modes[i].bus_fmt == framefmt->code)) { |
---|
1011 | 1429 | cur_best_fit_dist = dist; |
---|
1012 | 1430 | cur_best_fit = i; |
---|
1013 | 1431 | } |
---|
1014 | 1432 | } |
---|
1015 | 1433 | |
---|
1016 | | - return &supported_modes[cur_best_fit]; |
---|
| 1434 | + return &os04a10->supported_modes[cur_best_fit]; |
---|
1017 | 1435 | } |
---|
1018 | 1436 | |
---|
1019 | 1437 | static int os04a10_set_fmt(struct v4l2_subdev *sd, |
---|
.. | .. |
---|
1025 | 1443 | s64 h_blank, vblank_def; |
---|
1026 | 1444 | u64 dst_link_freq = 0; |
---|
1027 | 1445 | u64 dst_pixel_rate = 0; |
---|
| 1446 | + u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes; |
---|
1028 | 1447 | |
---|
1029 | 1448 | mutex_lock(&os04a10->mutex); |
---|
1030 | 1449 | |
---|
.. | .. |
---|
1049 | 1468 | __v4l2_ctrl_modify_range(os04a10->vblank, vblank_def, |
---|
1050 | 1469 | OS04A10_VTS_MAX - mode->height, |
---|
1051 | 1470 | 1, vblank_def); |
---|
1052 | | - if (mode->hdr_mode == NO_HDR) { |
---|
1053 | | - if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) { |
---|
1054 | | - dst_link_freq = 0; |
---|
1055 | | - dst_pixel_rate = PIXEL_RATE_WITH_360M; |
---|
1056 | | - } else { |
---|
1057 | | - dst_link_freq = 1; |
---|
1058 | | - dst_pixel_rate = PIXEL_RATE_WITH_648M; |
---|
1059 | | - } |
---|
1060 | | - } else if (mode->hdr_mode == HDR_X2) { |
---|
1061 | | - if (mode->width == 2560 && mode->height == 1440) { |
---|
1062 | | - dst_link_freq = 1; |
---|
1063 | | - dst_pixel_rate = PIXEL_RATE_WITH_648M; |
---|
1064 | | - } else { |
---|
1065 | | - if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) { |
---|
1066 | | - dst_link_freq = 0; |
---|
1067 | | - dst_pixel_rate = PIXEL_RATE_WITH_360M; |
---|
1068 | | - } else { |
---|
1069 | | - dst_link_freq = 1; |
---|
1070 | | - dst_pixel_rate = PIXEL_RATE_WITH_648M; |
---|
1071 | | - } |
---|
1072 | | - } |
---|
1073 | | - } |
---|
| 1471 | + dst_link_freq = mode->link_freq_idx; |
---|
| 1472 | + dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] / |
---|
| 1473 | + mode->bpp * 2 * lanes; |
---|
1074 | 1474 | __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate, |
---|
1075 | 1475 | dst_pixel_rate); |
---|
1076 | 1476 | __v4l2_ctrl_s_ctrl(os04a10->link_freq, |
---|
.. | .. |
---|
1134 | 1534 | if (fse->index >= os04a10->cfg_num) |
---|
1135 | 1535 | return -EINVAL; |
---|
1136 | 1536 | |
---|
1137 | | - if (fse->code != supported_modes[fse->index].bus_fmt) |
---|
| 1537 | + if (fse->code != os04a10->supported_modes[fse->index].bus_fmt) |
---|
1138 | 1538 | return -EINVAL; |
---|
1139 | 1539 | |
---|
1140 | | - fse->min_width = supported_modes[fse->index].width; |
---|
1141 | | - fse->max_width = supported_modes[fse->index].width; |
---|
1142 | | - fse->max_height = supported_modes[fse->index].height; |
---|
1143 | | - fse->min_height = supported_modes[fse->index].height; |
---|
| 1540 | + fse->min_width = os04a10->supported_modes[fse->index].width; |
---|
| 1541 | + fse->max_width = os04a10->supported_modes[fse->index].width; |
---|
| 1542 | + fse->max_height = os04a10->supported_modes[fse->index].height; |
---|
| 1543 | + fse->min_height = os04a10->supported_modes[fse->index].height; |
---|
1144 | 1544 | |
---|
1145 | 1545 | return 0; |
---|
1146 | 1546 | } |
---|
.. | .. |
---|
1167 | 1567 | struct os04a10 *os04a10 = to_os04a10(sd); |
---|
1168 | 1568 | const struct os04a10_mode *mode = os04a10->cur_mode; |
---|
1169 | 1569 | |
---|
1170 | | - mutex_lock(&os04a10->mutex); |
---|
1171 | 1570 | fi->interval = mode->max_fps; |
---|
1172 | | - mutex_unlock(&os04a10->mutex); |
---|
1173 | 1571 | |
---|
1174 | 1572 | return 0; |
---|
1175 | 1573 | } |
---|
1176 | 1574 | |
---|
1177 | | -static int os04a10_g_mbus_config(struct v4l2_subdev *sd, |
---|
| 1575 | +static int os04a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, |
---|
1178 | 1576 | struct v4l2_mbus_config *config) |
---|
1179 | 1577 | { |
---|
1180 | 1578 | struct os04a10 *os04a10 = to_os04a10(sd); |
---|
1181 | 1579 | const struct os04a10_mode *mode = os04a10->cur_mode; |
---|
1182 | 1580 | u32 val = 0; |
---|
| 1581 | + u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes; |
---|
1183 | 1582 | |
---|
1184 | 1583 | if (mode->hdr_mode == NO_HDR) |
---|
1185 | | - val = 1 << (OS04A10_LANES - 1) | |
---|
| 1584 | + val = 1 << (lanes - 1) | |
---|
1186 | 1585 | V4L2_MBUS_CSI2_CHANNEL_0 | |
---|
1187 | 1586 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; |
---|
1188 | 1587 | if (mode->hdr_mode == HDR_X2) |
---|
1189 | | - val = 1 << (OS04A10_LANES - 1) | |
---|
| 1588 | + val = 1 << (lanes - 1) | |
---|
1190 | 1589 | V4L2_MBUS_CSI2_CHANNEL_0 | |
---|
1191 | 1590 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | |
---|
1192 | 1591 | V4L2_MBUS_CSI2_CHANNEL_1; |
---|
1193 | 1592 | |
---|
1194 | | - config->type = V4L2_MBUS_CSI2; |
---|
| 1593 | + config->type = V4L2_MBUS_CSI2_DPHY; |
---|
1195 | 1594 | config->flags = val; |
---|
1196 | 1595 | |
---|
1197 | 1596 | return 0; |
---|
.. | .. |
---|
1201 | 1600 | struct rkmodule_inf *inf) |
---|
1202 | 1601 | { |
---|
1203 | 1602 | memset(inf, 0, sizeof(*inf)); |
---|
1204 | | - strlcpy(inf->base.sensor, OS04A10_NAME, sizeof(inf->base.sensor)); |
---|
1205 | | - strlcpy(inf->base.module, os04a10->module_name, |
---|
| 1603 | + strscpy(inf->base.sensor, OS04A10_NAME, sizeof(inf->base.sensor)); |
---|
| 1604 | + strscpy(inf->base.module, os04a10->module_name, |
---|
1206 | 1605 | sizeof(inf->base.module)); |
---|
1207 | | - strlcpy(inf->base.lens, os04a10->len_name, sizeof(inf->base.lens)); |
---|
| 1606 | + strscpy(inf->base.lens, os04a10->len_name, sizeof(inf->base.lens)); |
---|
1208 | 1607 | } |
---|
1209 | 1608 | |
---|
1210 | 1609 | static int os04a10_set_hdrae(struct os04a10 *os04a10, |
---|
.. | .. |
---|
1455 | 1854 | long ret = 0; |
---|
1456 | 1855 | u32 i, h, w; |
---|
1457 | 1856 | u32 stream = 0; |
---|
| 1857 | + u64 dst_link_freq = 0; |
---|
| 1858 | + u64 dst_pixel_rate = 0; |
---|
| 1859 | + u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes; |
---|
| 1860 | + const struct os04a10_mode *mode; |
---|
1458 | 1861 | |
---|
1459 | 1862 | switch (cmd) { |
---|
1460 | 1863 | case PREISP_CMD_SET_HDRAE_EXP: |
---|
.. | .. |
---|
1464 | 1867 | w = os04a10->cur_mode->width; |
---|
1465 | 1868 | h = os04a10->cur_mode->height; |
---|
1466 | 1869 | for (i = 0; i < os04a10->cfg_num; i++) { |
---|
1467 | | - if (w == supported_modes[i].width && |
---|
1468 | | - h == supported_modes[i].height && |
---|
1469 | | - supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) { |
---|
1470 | | - os04a10->cur_mode = &supported_modes[i]; |
---|
| 1870 | + if (w == os04a10->supported_modes[i].width && |
---|
| 1871 | + h == os04a10->supported_modes[i].height && |
---|
| 1872 | + os04a10->supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) { |
---|
| 1873 | + os04a10->cur_mode = &os04a10->supported_modes[i]; |
---|
1471 | 1874 | break; |
---|
1472 | 1875 | } |
---|
1473 | 1876 | } |
---|
.. | .. |
---|
1477 | 1880 | hdr_cfg->hdr_mode, w, h); |
---|
1478 | 1881 | ret = -EINVAL; |
---|
1479 | 1882 | } else { |
---|
1480 | | - w = os04a10->cur_mode->hts_def - os04a10->cur_mode->width; |
---|
1481 | | - h = os04a10->cur_mode->vts_def - os04a10->cur_mode->height; |
---|
| 1883 | + mode = os04a10->cur_mode; |
---|
| 1884 | + w = mode->hts_def - mode->width; |
---|
| 1885 | + h = mode->vts_def - mode->height; |
---|
1482 | 1886 | __v4l2_ctrl_modify_range(os04a10->hblank, w, w, 1, w); |
---|
1483 | 1887 | __v4l2_ctrl_modify_range(os04a10->vblank, h, |
---|
1484 | 1888 | OS04A10_VTS_MAX - os04a10->cur_mode->height, |
---|
1485 | 1889 | 1, h); |
---|
| 1890 | + dst_link_freq = mode->link_freq_idx; |
---|
| 1891 | + dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] / |
---|
| 1892 | + mode->bpp * 2 * lanes; |
---|
| 1893 | + __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate, |
---|
| 1894 | + dst_pixel_rate); |
---|
| 1895 | + __v4l2_ctrl_s_ctrl(os04a10->link_freq, |
---|
| 1896 | + dst_link_freq); |
---|
1486 | 1897 | dev_info(&os04a10->client->dev, |
---|
1487 | 1898 | "sensor mode: %d\n", |
---|
1488 | 1899 | os04a10->cur_mode->hdr_mode); |
---|
.. | .. |
---|
1535 | 1946 | { |
---|
1536 | 1947 | void __user *up = compat_ptr(arg); |
---|
1537 | 1948 | struct rkmodule_inf *inf; |
---|
1538 | | - struct rkmodule_awb_cfg *cfg; |
---|
1539 | 1949 | struct rkmodule_hdr_cfg *hdr; |
---|
1540 | 1950 | struct preisp_hdrae_exp_s *hdrae; |
---|
1541 | 1951 | struct rkmodule_dcg_ratio *dcg; |
---|
.. | .. |
---|
1552 | 1962 | } |
---|
1553 | 1963 | |
---|
1554 | 1964 | ret = os04a10_ioctl(sd, cmd, inf); |
---|
1555 | | - if (!ret) |
---|
| 1965 | + if (!ret) { |
---|
1556 | 1966 | ret = copy_to_user(up, inf, sizeof(*inf)); |
---|
1557 | | - kfree(inf); |
---|
1558 | | - break; |
---|
1559 | | - case RKMODULE_AWB_CFG: |
---|
1560 | | - cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); |
---|
1561 | | - if (!cfg) { |
---|
1562 | | - ret = -ENOMEM; |
---|
1563 | | - return ret; |
---|
| 1967 | + if (ret) |
---|
| 1968 | + ret = -EFAULT; |
---|
1564 | 1969 | } |
---|
1565 | | - |
---|
1566 | | - ret = copy_from_user(cfg, up, sizeof(*cfg)); |
---|
1567 | | - if (!ret) |
---|
1568 | | - ret = os04a10_ioctl(sd, cmd, cfg); |
---|
1569 | | - kfree(cfg); |
---|
| 1970 | + kfree(inf); |
---|
1570 | 1971 | break; |
---|
1571 | 1972 | case RKMODULE_GET_HDR_CFG: |
---|
1572 | 1973 | hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); |
---|
.. | .. |
---|
1576 | 1977 | } |
---|
1577 | 1978 | |
---|
1578 | 1979 | ret = os04a10_ioctl(sd, cmd, hdr); |
---|
1579 | | - if (!ret) |
---|
| 1980 | + if (!ret) { |
---|
1580 | 1981 | ret = copy_to_user(up, hdr, sizeof(*hdr)); |
---|
| 1982 | + if (ret) |
---|
| 1983 | + ret = -EFAULT; |
---|
| 1984 | + } |
---|
1581 | 1985 | kfree(hdr); |
---|
1582 | 1986 | break; |
---|
1583 | 1987 | case RKMODULE_SET_HDR_CFG: |
---|
.. | .. |
---|
1587 | 1991 | return ret; |
---|
1588 | 1992 | } |
---|
1589 | 1993 | |
---|
1590 | | - ret = copy_from_user(hdr, up, sizeof(*hdr)); |
---|
1591 | | - if (!ret) |
---|
1592 | | - ret = os04a10_ioctl(sd, cmd, hdr); |
---|
| 1994 | + if (copy_from_user(hdr, up, sizeof(*hdr))) |
---|
| 1995 | + return -EFAULT; |
---|
| 1996 | + |
---|
| 1997 | + ret = os04a10_ioctl(sd, cmd, hdr); |
---|
1593 | 1998 | kfree(hdr); |
---|
1594 | 1999 | break; |
---|
1595 | 2000 | case PREISP_CMD_SET_HDRAE_EXP: |
---|
.. | .. |
---|
1599 | 2004 | return ret; |
---|
1600 | 2005 | } |
---|
1601 | 2006 | |
---|
1602 | | - ret = copy_from_user(hdrae, up, sizeof(*hdrae)); |
---|
1603 | | - if (!ret) |
---|
1604 | | - ret = os04a10_ioctl(sd, cmd, hdrae); |
---|
| 2007 | + if (copy_from_user(hdrae, up, sizeof(*hdrae))) |
---|
| 2008 | + return -EFAULT; |
---|
| 2009 | + |
---|
| 2010 | + ret = os04a10_ioctl(sd, cmd, hdrae); |
---|
1605 | 2011 | kfree(hdrae); |
---|
1606 | 2012 | break; |
---|
1607 | 2013 | case RKMODULE_SET_CONVERSION_GAIN: |
---|
1608 | | - ret = copy_from_user(&cg, up, sizeof(cg)); |
---|
1609 | | - if (!ret) |
---|
1610 | | - ret = os04a10_ioctl(sd, cmd, &cg); |
---|
| 2014 | + if (copy_from_user(&cg, up, sizeof(cg))) |
---|
| 2015 | + return -EFAULT; |
---|
| 2016 | + |
---|
| 2017 | + ret = os04a10_ioctl(sd, cmd, &cg); |
---|
1611 | 2018 | break; |
---|
1612 | 2019 | case RKMODULE_SET_QUICK_STREAM: |
---|
1613 | | - ret = copy_from_user(&stream, up, sizeof(u32)); |
---|
1614 | | - if (!ret) |
---|
1615 | | - ret = os04a10_ioctl(sd, cmd, &stream); |
---|
| 2020 | + if (copy_from_user(&stream, up, sizeof(u32))) |
---|
| 2021 | + return -EFAULT; |
---|
| 2022 | + |
---|
| 2023 | + ret = os04a10_ioctl(sd, cmd, &stream); |
---|
1616 | 2024 | break; |
---|
1617 | 2025 | case RKMODULE_GET_DCG_RATIO: |
---|
1618 | 2026 | dcg = kzalloc(sizeof(*dcg), GFP_KERNEL); |
---|
.. | .. |
---|
1622 | 2030 | } |
---|
1623 | 2031 | |
---|
1624 | 2032 | ret = os04a10_ioctl(sd, cmd, dcg); |
---|
1625 | | - if (!ret) |
---|
| 2033 | + if (!ret) { |
---|
1626 | 2034 | ret = copy_to_user(up, dcg, sizeof(*dcg)); |
---|
| 2035 | + if (ret) |
---|
| 2036 | + return -EFAULT; |
---|
| 2037 | + } |
---|
1627 | 2038 | kfree(dcg); |
---|
1628 | 2039 | break; |
---|
1629 | 2040 | default: |
---|
.. | .. |
---|
1645 | 2056 | OS04A10_REG_HCG_SWITCH, |
---|
1646 | 2057 | OS04A10_REG_VALUE_08BIT, |
---|
1647 | 2058 | &val); |
---|
1648 | | - val |= 0x70; |
---|
| 2059 | + val &= ~0x70; |
---|
| 2060 | + if (!os04a10->long_hcg) |
---|
| 2061 | + val |= 0x10; |
---|
| 2062 | + if (!os04a10->middle_hcg) |
---|
| 2063 | + val |= 0x20; |
---|
| 2064 | + if (!os04a10->short_hcg) |
---|
| 2065 | + val |= 0x40; |
---|
1649 | 2066 | ret |= os04a10_write_reg(client, |
---|
1650 | 2067 | OS04A10_REG_HCG_SWITCH, |
---|
1651 | 2068 | OS04A10_REG_VALUE_08BIT, |
---|
1652 | 2069 | val); |
---|
1653 | | - os04a10->long_hcg = false; |
---|
1654 | | - os04a10->middle_hcg = false; |
---|
1655 | | - os04a10->short_hcg = false; |
---|
1656 | 2070 | return ret; |
---|
1657 | 2071 | } |
---|
1658 | 2072 | |
---|
.. | .. |
---|
1661 | 2075 | int ret; |
---|
1662 | 2076 | |
---|
1663 | 2077 | if (!os04a10->is_thunderboot) { |
---|
1664 | | - ret = os04a10_write_array(os04a10->client, os04a10_global_regs); |
---|
1665 | | - if (ret) { |
---|
1666 | | - dev_err(&os04a10->client->dev, |
---|
1667 | | - "could not set init registers\n"); |
---|
1668 | | - return ret; |
---|
1669 | | - } |
---|
1670 | | - |
---|
1671 | 2078 | ret = os04a10_write_array(os04a10->client, os04a10->cur_mode->reg_list); |
---|
1672 | 2079 | if (ret) |
---|
1673 | 2080 | return ret; |
---|
.. | .. |
---|
1768 | 2175 | OS04A10_REG_VALUE_08BIT, |
---|
1769 | 2176 | 0x01); |
---|
1770 | 2177 | usleep_range(100, 200); |
---|
| 2178 | + ret |= os04a10_write_array(os04a10->client, |
---|
| 2179 | + os04a10->cur_mode->global_reg_list); |
---|
| 2180 | + if (ret) { |
---|
| 2181 | + dev_err(&os04a10->client->dev, |
---|
| 2182 | + "could not set init registers\n"); |
---|
| 2183 | + goto unlock_and_return; |
---|
| 2184 | + } |
---|
1771 | 2185 | } |
---|
1772 | 2186 | |
---|
1773 | 2187 | os04a10->power_on = true; |
---|
.. | .. |
---|
1821 | 2235 | dev_err(dev, "Failed to enable regulators\n"); |
---|
1822 | 2236 | goto disable_clk; |
---|
1823 | 2237 | } |
---|
1824 | | - |
---|
| 2238 | + usleep_range(25000, 30000); |
---|
1825 | 2239 | if (!IS_ERR(os04a10->reset_gpio)) |
---|
1826 | 2240 | gpiod_direction_output(os04a10->reset_gpio, 0); |
---|
1827 | 2241 | |
---|
.. | .. |
---|
1881 | 2295 | os04a10->is_thunderboot_ng = false; |
---|
1882 | 2296 | regulator_bulk_disable(OS04A10_NUM_SUPPLIES, os04a10->supplies); |
---|
1883 | 2297 | } |
---|
| 2298 | + usleep_range(30000, 31000); |
---|
1884 | 2299 | } |
---|
1885 | 2300 | |
---|
1886 | | -static int os04a10_runtime_resume(struct device *dev) |
---|
| 2301 | +static int __maybe_unused os04a10_runtime_resume(struct device *dev) |
---|
1887 | 2302 | { |
---|
1888 | 2303 | struct i2c_client *client = to_i2c_client(dev); |
---|
1889 | 2304 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
---|
.. | .. |
---|
1892 | 2307 | return __os04a10_power_on(os04a10); |
---|
1893 | 2308 | } |
---|
1894 | 2309 | |
---|
1895 | | -static int os04a10_runtime_suspend(struct device *dev) |
---|
| 2310 | +static int __maybe_unused os04a10_runtime_suspend(struct device *dev) |
---|
1896 | 2311 | { |
---|
1897 | 2312 | struct i2c_client *client = to_i2c_client(dev); |
---|
1898 | 2313 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
---|
.. | .. |
---|
1909 | 2324 | struct os04a10 *os04a10 = to_os04a10(sd); |
---|
1910 | 2325 | struct v4l2_mbus_framefmt *try_fmt = |
---|
1911 | 2326 | v4l2_subdev_get_try_format(sd, fh->pad, 0); |
---|
1912 | | - const struct os04a10_mode *def_mode = &supported_modes[0]; |
---|
| 2327 | + const struct os04a10_mode *def_mode = &os04a10->supported_modes[0]; |
---|
1913 | 2328 | |
---|
1914 | 2329 | mutex_lock(&os04a10->mutex); |
---|
1915 | 2330 | /* Initialize try_fmt */ |
---|
.. | .. |
---|
1934 | 2349 | if (fie->index >= os04a10->cfg_num) |
---|
1935 | 2350 | return -EINVAL; |
---|
1936 | 2351 | |
---|
1937 | | - fie->code = supported_modes[fie->index].bus_fmt; |
---|
1938 | | - fie->width = supported_modes[fie->index].width; |
---|
1939 | | - fie->height = supported_modes[fie->index].height; |
---|
1940 | | - fie->interval = supported_modes[fie->index].max_fps; |
---|
1941 | | - fie->reserved[0] = supported_modes[fie->index].hdr_mode; |
---|
| 2352 | + fie->code = os04a10->supported_modes[fie->index].bus_fmt; |
---|
| 2353 | + fie->width = os04a10->supported_modes[fie->index].width; |
---|
| 2354 | + fie->height = os04a10->supported_modes[fie->index].height; |
---|
| 2355 | + fie->interval = os04a10->supported_modes[fie->index].max_fps; |
---|
| 2356 | + fie->reserved[0] = os04a10->supported_modes[fie->index].hdr_mode; |
---|
1942 | 2357 | return 0; |
---|
1943 | 2358 | } |
---|
1944 | 2359 | |
---|
.. | .. |
---|
1964 | 2379 | static const struct v4l2_subdev_video_ops os04a10_video_ops = { |
---|
1965 | 2380 | .s_stream = os04a10_s_stream, |
---|
1966 | 2381 | .g_frame_interval = os04a10_g_frame_interval, |
---|
1967 | | - .g_mbus_config = os04a10_g_mbus_config, |
---|
1968 | 2382 | }; |
---|
1969 | 2383 | |
---|
1970 | 2384 | static const struct v4l2_subdev_pad_ops os04a10_pad_ops = { |
---|
.. | .. |
---|
1973 | 2387 | .enum_frame_interval = os04a10_enum_frame_interval, |
---|
1974 | 2388 | .get_fmt = os04a10_get_fmt, |
---|
1975 | 2389 | .set_fmt = os04a10_set_fmt, |
---|
| 2390 | + .get_mbus_config = os04a10_g_mbus_config, |
---|
1976 | 2391 | }; |
---|
1977 | 2392 | |
---|
1978 | 2393 | static const struct v4l2_subdev_ops os04a10_subdev_ops = { |
---|
.. | .. |
---|
2052 | 2467 | val |= MIRROR_BIT_MASK; |
---|
2053 | 2468 | else |
---|
2054 | 2469 | val &= ~MIRROR_BIT_MASK; |
---|
2055 | | - ret = os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG, |
---|
| 2470 | + ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG, |
---|
2056 | 2471 | OS04A10_REG_VALUE_08BIT, |
---|
2057 | 2472 | val); |
---|
2058 | 2473 | if (ret == 0) |
---|
.. | .. |
---|
2066 | 2481 | val |= FLIP_BIT_MASK; |
---|
2067 | 2482 | else |
---|
2068 | 2483 | val &= ~FLIP_BIT_MASK; |
---|
2069 | | - ret = os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG, |
---|
| 2484 | + ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG, |
---|
2070 | 2485 | OS04A10_REG_VALUE_08BIT, |
---|
2071 | 2486 | val); |
---|
2072 | 2487 | if (ret == 0) |
---|
.. | .. |
---|
2096 | 2511 | int ret; |
---|
2097 | 2512 | u64 dst_link_freq = 0; |
---|
2098 | 2513 | u64 dst_pixel_rate = 0; |
---|
| 2514 | + u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes; |
---|
2099 | 2515 | |
---|
2100 | 2516 | handler = &os04a10->ctrl_handler; |
---|
2101 | 2517 | mode = os04a10->cur_mode; |
---|
.. | .. |
---|
2106 | 2522 | |
---|
2107 | 2523 | os04a10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, |
---|
2108 | 2524 | V4L2_CID_LINK_FREQ, |
---|
2109 | | - 1, 0, link_freq_menu_items); |
---|
| 2525 | + ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items); |
---|
2110 | 2526 | |
---|
2111 | | - if (os04a10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) { |
---|
2112 | | - dst_link_freq = 0; |
---|
2113 | | - dst_pixel_rate = PIXEL_RATE_WITH_360M; |
---|
2114 | | - } else { |
---|
2115 | | - dst_link_freq = 1; |
---|
2116 | | - dst_pixel_rate = PIXEL_RATE_WITH_648M; |
---|
2117 | | - } |
---|
| 2527 | + dst_link_freq = mode->link_freq_idx; |
---|
| 2528 | + dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] / |
---|
| 2529 | + mode->bpp * 2 * lanes; |
---|
2118 | 2530 | /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ |
---|
2119 | 2531 | os04a10->pixel_rate = v4l2_ctrl_new_std(handler, NULL, |
---|
2120 | 2532 | V4L2_CID_PIXEL_RATE, |
---|
2121 | 2533 | 0, PIXEL_RATE_WITH_648M, |
---|
2122 | 2534 | 1, dst_pixel_rate); |
---|
2123 | 2535 | |
---|
2124 | | - __v4l2_ctrl_s_ctrl(os04a10->link_freq, |
---|
2125 | | - dst_link_freq); |
---|
| 2536 | + __v4l2_ctrl_s_ctrl(os04a10->link_freq, dst_link_freq); |
---|
2126 | 2537 | |
---|
2127 | 2538 | h_blank = mode->hts_def - mode->width; |
---|
2128 | 2539 | os04a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, |
---|
.. | .. |
---|
2170 | 2581 | os04a10->long_hcg = false; |
---|
2171 | 2582 | os04a10->middle_hcg = false; |
---|
2172 | 2583 | os04a10->short_hcg = false; |
---|
| 2584 | + if (!os04a10->is_thunderboot) |
---|
| 2585 | + os04a10->is_thunderboot_ng = true; |
---|
2173 | 2586 | |
---|
2174 | 2587 | return 0; |
---|
2175 | 2588 | |
---|
.. | .. |
---|
2252 | 2665 | struct device_node *node = dev->of_node; |
---|
2253 | 2666 | struct os04a10 *os04a10; |
---|
2254 | 2667 | struct v4l2_subdev *sd; |
---|
| 2668 | + struct device_node *endpoint; |
---|
2255 | 2669 | char facing[2]; |
---|
2256 | 2670 | int ret; |
---|
2257 | 2671 | u32 i, hdr_mode = 0; |
---|
.. | .. |
---|
2285 | 2699 | hdr_mode = NO_HDR; |
---|
2286 | 2700 | dev_warn(dev, " Get hdr mode failed! no hdr default\n"); |
---|
2287 | 2701 | } |
---|
2288 | | - os04a10->cfg_num = ARRAY_SIZE(supported_modes); |
---|
| 2702 | + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); |
---|
| 2703 | + if (!endpoint) { |
---|
| 2704 | + dev_err(dev, "Failed to get endpoint\n"); |
---|
| 2705 | + return -EINVAL; |
---|
| 2706 | + } |
---|
| 2707 | + |
---|
| 2708 | + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), |
---|
| 2709 | + &os04a10->bus_cfg); |
---|
| 2710 | + if (ret) { |
---|
| 2711 | + dev_err(dev, "Failed to get bus config\n"); |
---|
| 2712 | + return -EINVAL; |
---|
| 2713 | + } |
---|
| 2714 | + if (os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) { |
---|
| 2715 | + os04a10->supported_modes = supported_modes; |
---|
| 2716 | + os04a10->cfg_num = ARRAY_SIZE(supported_modes); |
---|
| 2717 | + dev_info(dev, "detect os04a10 lane %d\n", |
---|
| 2718 | + os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes); |
---|
| 2719 | + } else { |
---|
| 2720 | + os04a10->supported_modes = supported_modes_2lane; |
---|
| 2721 | + os04a10->cfg_num = ARRAY_SIZE(supported_modes_2lane); |
---|
| 2722 | + dev_info(dev, "detect os04a10 lane %d\n", |
---|
| 2723 | + os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes); |
---|
| 2724 | + } |
---|
| 2725 | + |
---|
2289 | 2726 | for (i = 0; i < os04a10->cfg_num; i++) { |
---|
2290 | 2727 | if (hdr_mode == supported_modes[i].hdr_mode) { |
---|
2291 | | - os04a10->cur_mode = &supported_modes[i]; |
---|
| 2728 | + os04a10->cur_mode = &os04a10->supported_modes[i]; |
---|
2292 | 2729 | break; |
---|
2293 | 2730 | } |
---|
2294 | 2731 | } |
---|
.. | .. |
---|
2346 | 2783 | ret = os04a10_check_sensor_id(os04a10, client); |
---|
2347 | 2784 | if (ret) |
---|
2348 | 2785 | goto err_power_off; |
---|
| 2786 | + |
---|
2349 | 2787 | ret = os04a10_get_dcg_ratio(os04a10); |
---|
| 2788 | + if (ret) |
---|
| 2789 | + dev_warn(dev, "get dcg ratio failed\n"); |
---|
2350 | 2790 | |
---|
2351 | 2791 | #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API |
---|
2352 | 2792 | sd->internal_ops = &os04a10_internal_ops; |
---|