.. | .. |
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| 1 | +# SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | menu "IRQ chip support" |
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2 | 3 | |
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3 | 4 | config IRQCHIP |
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.. | .. |
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6 | 7 | |
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7 | 8 | config ARM_GIC |
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8 | 9 | bool |
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9 | | - select IRQ_DOMAIN |
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10 | 10 | select IRQ_DOMAIN_HIERARCHY |
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11 | 11 | select GENERIC_IRQ_MULTI_HANDLER |
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12 | 12 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
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.. | .. |
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15 | 15 | bool |
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16 | 16 | depends on PM |
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17 | 17 | select ARM_GIC |
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18 | | - select PM_CLK |
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19 | 18 | |
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20 | 19 | config ARM_GIC_MAX_NR |
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21 | 20 | int |
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| 21 | + depends on ARM_GIC |
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22 | 22 | default 2 if ARCH_REALVIEW |
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23 | 23 | default 1 |
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24 | 24 | |
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.. | .. |
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33 | 33 | |
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34 | 34 | config ARM_GIC_V3 |
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35 | 35 | bool |
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36 | | - select IRQ_DOMAIN |
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37 | 36 | select GENERIC_IRQ_MULTI_HANDLER |
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38 | 37 | select IRQ_DOMAIN_HIERARCHY |
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39 | 38 | select PARTITION_PERCPU |
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.. | .. |
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59 | 58 | |
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60 | 59 | config ARM_NVIC |
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61 | 60 | bool |
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62 | | - select IRQ_DOMAIN |
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63 | 61 | select IRQ_DOMAIN_HIERARCHY |
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64 | 62 | select GENERIC_IRQ_CHIP |
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65 | 63 | |
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.. | .. |
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88 | 86 | depends on PCI |
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89 | 87 | select PCI_MSI |
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90 | 88 | select GENERIC_IRQ_CHIP |
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| 89 | + |
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| 90 | +config AL_FIC |
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| 91 | + bool "Amazon's Annapurna Labs Fabric Interrupt Controller" |
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| 92 | + depends on OF || COMPILE_TEST |
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| 93 | + select GENERIC_IRQ_CHIP |
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| 94 | + select IRQ_DOMAIN |
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| 95 | + help |
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| 96 | + Support Amazon's Annapurna Labs Fabric Interrupt Controller. |
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91 | 97 | |
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92 | 98 | config ATMEL_AIC_IRQ |
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93 | 99 | bool |
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.. | .. |
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129 | 135 | select GENERIC_IRQ_CHIP |
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130 | 136 | select IRQ_DOMAIN |
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131 | 137 | |
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132 | | -config DW_APB_ICTL |
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| 138 | +config DAVINCI_AINTC |
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133 | 139 | bool |
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134 | 140 | select GENERIC_IRQ_CHIP |
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135 | 141 | select IRQ_DOMAIN |
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| 142 | + |
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| 143 | +config DAVINCI_CP_INTC |
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| 144 | + bool |
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| 145 | + select GENERIC_IRQ_CHIP |
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| 146 | + select IRQ_DOMAIN |
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| 147 | + |
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| 148 | +config DW_APB_ICTL |
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| 149 | + bool |
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| 150 | + select GENERIC_IRQ_CHIP |
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| 151 | + select IRQ_DOMAIN_HIERARCHY |
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136 | 152 | |
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137 | 153 | config FARADAY_FTINTC010 |
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138 | 154 | bool |
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.. | .. |
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150 | 166 | select GENERIC_IRQ_CHIP |
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151 | 167 | select IRQ_DOMAIN |
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152 | 168 | |
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| 169 | +config IXP4XX_IRQ |
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| 170 | + bool |
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| 171 | + select IRQ_DOMAIN |
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| 172 | + select GENERIC_IRQ_MULTI_HANDLER |
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| 173 | + select SPARSE_IRQ |
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| 174 | + |
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| 175 | +config MADERA_IRQ |
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| 176 | + tristate |
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| 177 | + |
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153 | 178 | config IRQ_MIPS_CPU |
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154 | 179 | bool |
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155 | 180 | select GENERIC_IRQ_CHIP |
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156 | | - select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING |
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| 181 | + select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING |
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157 | 182 | select IRQ_DOMAIN |
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158 | | - select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI |
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159 | 183 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
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160 | 184 | |
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161 | 185 | config CLPS711X_IRQCHIP |
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.. | .. |
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195 | 219 | help |
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196 | 220 | Support for the J-Core integrated AIC. |
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197 | 221 | |
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198 | | -config RENESAS_INTC_IRQPIN |
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| 222 | +config RDA_INTC |
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199 | 223 | bool |
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200 | 224 | select IRQ_DOMAIN |
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201 | 225 | |
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| 226 | +config RENESAS_INTC_IRQPIN |
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| 227 | + bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST |
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| 228 | + select IRQ_DOMAIN |
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| 229 | + help |
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| 230 | + Enable support for the Renesas Interrupt Controller for external |
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| 231 | + interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. |
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| 232 | + |
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202 | 233 | config RENESAS_IRQC |
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203 | | - bool |
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| 234 | + bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST |
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204 | 235 | select GENERIC_IRQ_CHIP |
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205 | 236 | select IRQ_DOMAIN |
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| 237 | + help |
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| 238 | + Enable support for the Renesas Interrupt Controller for external |
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| 239 | + devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. |
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| 240 | + |
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| 241 | +config RENESAS_RZA1_IRQC |
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| 242 | + bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST |
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| 243 | + select IRQ_DOMAIN_HIERARCHY |
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| 244 | + help |
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| 245 | + Enable support for the Renesas RZ/A1 Interrupt Controller, to use up |
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| 246 | + to 8 external interrupts with configurable sense select. |
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| 247 | + |
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| 248 | +config SL28CPLD_INTC |
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| 249 | + bool "Kontron sl28cpld IRQ controller" |
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| 250 | + depends on MFD_SL28CPLD=y || COMPILE_TEST |
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| 251 | + select REGMAP_IRQ |
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| 252 | + help |
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| 253 | + Interrupt controller driver for the board management controller |
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| 254 | + found on the Kontron sl28 CPLD. |
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206 | 255 | |
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207 | 256 | config ST_IRQCHIP |
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208 | 257 | bool |
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.. | .. |
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264 | 313 | |
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265 | 314 | config MIPS_GIC |
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266 | 315 | bool |
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267 | | - select GENERIC_IRQ_IPI |
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| 316 | + select GENERIC_IRQ_IPI if SMP |
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268 | 317 | select IRQ_DOMAIN_HIERARCHY |
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269 | 318 | select MIPS_CM |
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270 | 319 | |
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.. | .. |
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273 | 322 | depends on MACH_INGENIC |
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274 | 323 | default y |
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275 | 324 | |
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| 325 | +config INGENIC_TCU_IRQ |
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| 326 | + bool "Ingenic JZ47xx TCU interrupt controller" |
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| 327 | + default MACH_INGENIC |
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| 328 | + depends on MIPS || COMPILE_TEST |
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| 329 | + select MFD_SYSCON |
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| 330 | + select GENERIC_IRQ_CHIP |
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| 331 | + help |
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| 332 | + Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic |
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| 333 | + JZ47xx SoCs. |
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| 334 | + |
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| 335 | + If unsure, say N. |
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| 336 | + |
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276 | 337 | config RENESAS_H8300H_INTC |
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277 | 338 | bool |
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278 | 339 | select IRQ_DOMAIN |
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279 | 340 | |
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280 | 341 | config RENESAS_H8S_INTC |
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281 | | - bool |
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| 342 | + bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST |
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282 | 343 | select IRQ_DOMAIN |
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| 344 | + help |
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| 345 | + Enable support for the Renesas H8/300 Interrupt Controller, as found |
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| 346 | + on Renesas H8S SoCs. |
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283 | 347 | |
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284 | 348 | config IMX_GPCV2 |
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285 | 349 | bool |
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.. | .. |
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310 | 374 | config MVEBU_PIC |
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311 | 375 | bool |
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312 | 376 | |
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| 377 | +config MVEBU_SEI |
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| 378 | + bool |
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| 379 | + |
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| 380 | +config LS_EXTIRQ |
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| 381 | + def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE |
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| 382 | + select MFD_SYSCON |
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| 383 | + |
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313 | 384 | config LS_SCFG_MSI |
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314 | 385 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE |
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315 | 386 | depends on PCI && PCI_MSI |
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.. | .. |
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332 | 403 | config QCOM_IRQ_COMBINER |
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333 | 404 | bool "QCOM IRQ combiner support" |
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334 | 405 | depends on ARCH_QCOM && ACPI |
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335 | | - select IRQ_DOMAIN |
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336 | 406 | select IRQ_DOMAIN_HIERARCHY |
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337 | 407 | help |
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338 | 408 | Say yes here to add support for the IRQ combiner devices embedded |
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.. | .. |
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347 | 417 | Support for the UniPhier AIDET (ARM Interrupt Detector). |
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348 | 418 | |
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349 | 419 | config MESON_IRQ_GPIO |
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350 | | - bool "Meson GPIO Interrupt Multiplexer" |
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351 | | - depends on ARCH_MESON |
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352 | | - select IRQ_DOMAIN |
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| 420 | + tristate "Meson GPIO Interrupt Multiplexer" |
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| 421 | + depends on ARCH_MESON || COMPILE_TEST |
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| 422 | + default ARCH_MESON |
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353 | 423 | select IRQ_DOMAIN_HIERARCHY |
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354 | 424 | help |
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355 | 425 | Support Meson SoC Family GPIO Interrupt Multiplexer |
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.. | .. |
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364 | 434 | for Goldfish based virtual platforms. |
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365 | 435 | |
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366 | 436 | config QCOM_PDC |
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367 | | - bool "QCOM PDC" |
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| 437 | + tristate "QCOM PDC" |
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368 | 438 | depends on ARCH_QCOM |
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369 | | - select IRQ_DOMAIN |
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| 439 | + depends on QCOM_SCM || !QCOM_SCM |
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370 | 440 | select IRQ_DOMAIN_HIERARCHY |
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371 | 441 | help |
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372 | 442 | Power Domain Controller driver to manage and configure wakeup |
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373 | 443 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. |
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374 | 444 | |
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| 445 | +config CSKY_MPINTC |
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| 446 | + bool "C-SKY Multi Processor Interrupt Controller" |
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| 447 | + depends on CSKY |
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| 448 | + help |
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| 449 | + Say yes here to enable C-SKY SMP interrupt controller driver used |
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| 450 | + for C-SKY SMP system. |
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| 451 | + In fact it's not mmio map in hardware and it uses ld/st to visit the |
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| 452 | + controller's register inside CPU. |
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| 453 | + |
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| 454 | +config CSKY_APB_INTC |
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| 455 | + bool "C-SKY APB Interrupt Controller" |
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| 456 | + depends on CSKY |
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| 457 | + help |
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| 458 | + Say yes here to enable C-SKY APB interrupt controller driver used |
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| 459 | + by C-SKY single core SOC system. It uses mmio map apb-bus to visit |
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| 460 | + the controller's register. |
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| 461 | + |
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| 462 | +config IMX_IRQSTEER |
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| 463 | + bool "i.MX IRQSTEER support" |
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| 464 | + depends on ARCH_MXC || COMPILE_TEST |
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| 465 | + default ARCH_MXC |
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| 466 | + select IRQ_DOMAIN |
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| 467 | + help |
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| 468 | + Support for the i.MX IRQSTEER interrupt multiplexer/remapper. |
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| 469 | + |
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| 470 | +config IMX_INTMUX |
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| 471 | + bool "i.MX INTMUX support" if COMPILE_TEST |
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| 472 | + default y if ARCH_MXC |
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| 473 | + select IRQ_DOMAIN |
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| 474 | + help |
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| 475 | + Support for the i.MX INTMUX interrupt multiplexer. |
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| 476 | + |
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| 477 | +config LS1X_IRQ |
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| 478 | + bool "Loongson-1 Interrupt Controller" |
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| 479 | + depends on MACH_LOONGSON32 |
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| 480 | + default y |
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| 481 | + select IRQ_DOMAIN |
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| 482 | + select GENERIC_IRQ_CHIP |
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| 483 | + help |
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| 484 | + Support for the Loongson-1 platform Interrupt Controller. |
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| 485 | + |
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| 486 | +config TI_SCI_INTR_IRQCHIP |
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| 487 | + bool |
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| 488 | + depends on TI_SCI_PROTOCOL |
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| 489 | + select IRQ_DOMAIN_HIERARCHY |
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| 490 | + help |
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| 491 | + This enables the irqchip driver support for K3 Interrupt router |
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| 492 | + over TI System Control Interface available on some new TI's SoCs. |
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| 493 | + If you wish to use interrupt router irq resources managed by the |
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| 494 | + TI System Controller, say Y here. Otherwise, say N. |
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| 495 | + |
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| 496 | +config TI_SCI_INTA_IRQCHIP |
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| 497 | + bool |
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| 498 | + depends on TI_SCI_PROTOCOL |
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| 499 | + select IRQ_DOMAIN_HIERARCHY |
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| 500 | + select TI_SCI_INTA_MSI_DOMAIN |
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| 501 | + help |
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| 502 | + This enables the irqchip driver support for K3 Interrupt aggregator |
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| 503 | + over TI System Control Interface available on some new TI's SoCs. |
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| 504 | + If you wish to use interrupt aggregator irq resources managed by the |
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| 505 | + TI System Controller, say Y here. Otherwise, say N. |
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| 506 | + |
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| 507 | +config TI_PRUSS_INTC |
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| 508 | + tristate "TI PRU-ICSS Interrupt Controller" |
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| 509 | + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 |
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| 510 | + select IRQ_DOMAIN |
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| 511 | + help |
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| 512 | + This enables support for the PRU-ICSS Local Interrupt Controller |
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| 513 | + present within a PRU-ICSS subsystem present on various TI SoCs. |
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| 514 | + The PRUSS INTC enables various interrupts to be routed to multiple |
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| 515 | + different processors within the SoC. |
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| 516 | + |
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| 517 | +config RISCV_INTC |
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| 518 | + bool "RISC-V Local Interrupt Controller" |
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| 519 | + depends on RISCV |
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| 520 | + default y |
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| 521 | + help |
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| 522 | + This enables support for the per-HART local interrupt controller |
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| 523 | + found in standard RISC-V systems. The per-HART local interrupt |
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| 524 | + controller handles timer interrupts, software interrupts, and |
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| 525 | + hardware interrupts. Without a per-HART local interrupt controller, |
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| 526 | + a RISC-V system will be unable to handle any interrupts. |
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| 527 | + |
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| 528 | + If you don't know what to do here, say Y. |
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| 529 | + |
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375 | 530 | config SIFIVE_PLIC |
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376 | 531 | bool "SiFive Platform-Level Interrupt Controller" |
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377 | 532 | depends on RISCV |
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| 533 | + select IRQ_DOMAIN_HIERARCHY |
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378 | 534 | help |
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379 | 535 | This enables support for the PLIC chip found in SiFive (and |
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380 | 536 | potentially other) RISC-V systems. The PLIC controls devices |
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.. | .. |
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384 | 540 | |
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385 | 541 | If you don't know what to do here, say Y. |
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386 | 542 | |
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| 543 | +config EXYNOS_IRQ_COMBINER |
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| 544 | + bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST |
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| 545 | + depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST |
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| 546 | + help |
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| 547 | + Say yes here to add support for the IRQ combiner devices embedded |
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| 548 | + in Samsung Exynos chips. |
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| 549 | + |
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| 550 | +config LOONGSON_LIOINTC |
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| 551 | + bool "Loongson Local I/O Interrupt Controller" |
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| 552 | + depends on MACH_LOONGSON64 |
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| 553 | + default y |
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| 554 | + select IRQ_DOMAIN |
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| 555 | + select GENERIC_IRQ_CHIP |
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| 556 | + help |
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| 557 | + Support for the Loongson Local I/O Interrupt Controller. |
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| 558 | + |
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| 559 | +config LOONGSON_HTPIC |
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| 560 | + bool "Loongson3 HyperTransport PIC Controller" |
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| 561 | + depends on MACH_LOONGSON64 |
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| 562 | + default y |
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| 563 | + select IRQ_DOMAIN |
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| 564 | + select GENERIC_IRQ_CHIP |
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| 565 | + help |
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| 566 | + Support for the Loongson-3 HyperTransport PIC Controller. |
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| 567 | + |
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| 568 | +config LOONGSON_HTVEC |
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| 569 | + bool "Loongson3 HyperTransport Interrupt Vector Controller" |
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| 570 | + depends on MACH_LOONGSON64 |
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| 571 | + default MACH_LOONGSON64 |
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| 572 | + select IRQ_DOMAIN_HIERARCHY |
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| 573 | + help |
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| 574 | + Support for the Loongson3 HyperTransport Interrupt Vector Controller. |
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| 575 | + |
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| 576 | +config LOONGSON_PCH_PIC |
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| 577 | + bool "Loongson PCH PIC Controller" |
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| 578 | + depends on MACH_LOONGSON64 || COMPILE_TEST |
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| 579 | + default MACH_LOONGSON64 |
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| 580 | + select IRQ_DOMAIN_HIERARCHY |
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| 581 | + select IRQ_FASTEOI_HIERARCHY_HANDLERS |
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| 582 | + help |
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| 583 | + Support for the Loongson PCH PIC Controller. |
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| 584 | + |
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| 585 | +config LOONGSON_PCH_MSI |
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| 586 | + bool "Loongson PCH MSI Controller" |
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| 587 | + depends on MACH_LOONGSON64 || COMPILE_TEST |
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| 588 | + depends on PCI |
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| 589 | + default MACH_LOONGSON64 |
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| 590 | + select IRQ_DOMAIN_HIERARCHY |
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| 591 | + select PCI_MSI |
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| 592 | + help |
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| 593 | + Support for the Loongson PCH MSI Controller. |
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| 594 | + |
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| 595 | +config MST_IRQ |
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| 596 | + bool "MStar Interrupt Controller" |
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| 597 | + depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST |
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| 598 | + default ARCH_MEDIATEK |
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| 599 | + select IRQ_DOMAIN |
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| 600 | + select IRQ_DOMAIN_HIERARCHY |
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| 601 | + help |
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| 602 | + Support MStar Interrupt Controller. |
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| 603 | + |
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387 | 604 | endmenu |
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